drivers/clk/mediatek/clk-mt6735-vdecsys.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/platform_device.h>
   8
   9 #include "clk-gate.h"
  10 #include "clk-mtk.h"
  11
  12 #include <dt-bindings/clock/mediatek,mt6735-vdecsys.h>
  13 #include <dt-bindings/reset/mediatek,mt6735-vdecsys.h>
  14
  15 #define VDEC_CKEN_SET                   0x00
  16 #define VDEC_CKEN_CLR                   0x04
  17 #define SMI_LARB1_CKEN_SET              0x08
  18 #define SMI_LARB1_CKEN_CLR              0x0c
  19 #define VDEC_RESETB_CON                 0x10
  20 #define SMI_LARB1_RESETB_CON            0x14
  21
  22 #define RST_NR_PER_BANK                 32
  23
  24 static struct mtk_gate_regs vdec_cg_regs = {
  25         .set_ofs = VDEC_CKEN_SET,
  26         .clr_ofs = VDEC_CKEN_CLR,
  27         .sta_ofs = VDEC_CKEN_SET,
  28 };
  29
  30 static struct mtk_gate_regs smi_larb1_cg_regs = {
  31         .set_ofs = SMI_LARB1_CKEN_SET,
  32         .clr_ofs = SMI_LARB1_CKEN_CLR,
  33         .sta_ofs = SMI_LARB1_CKEN_SET,
  34 };
  35
  36 static const struct mtk_gate vdecsys_gates[] = {
  37         GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
  38         GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
  39 };
  40
  41 static u16 vdecsys_rst_bank_ofs[] = { VDEC_RESETB_CON, SMI_LARB1_RESETB_CON };
  42
  43 static u16 vdecsys_rst_idx_map[] = {
  44         [MT6735_VDEC_RST0_VDEC]         = 0 * RST_NR_PER_BANK + 0,
  45         [MT6735_VDEC_RST1_SMI_LARB1]    = 1 * RST_NR_PER_BANK + 0,
  46 };
  47
  48 static const struct mtk_clk_rst_desc vdecsys_resets = {
  49         .version = MTK_RST_SIMPLE,
  50         .rst_bank_ofs = vdecsys_rst_bank_ofs,
  51         .rst_bank_nr = ARRAY_SIZE(vdecsys_rst_bank_ofs),
  52         .rst_idx_map = vdecsys_rst_idx_map,
  53         .rst_idx_map_nr = ARRAY_SIZE(vdecsys_rst_idx_map)
  54 };
  55
  56 static const struct mtk_clk_desc vdecsys_clks = {
  57         .clks = vdecsys_gates,
  58         .num_clks = ARRAY_SIZE(vdecsys_gates),
  59         .rst_desc = &vdecsys_resets
  60 };
  61
  62 static const struct of_device_id of_match_mt6735_vdecsys[] = {
  63         { .compatible = "mediatek,mt6735-vdecsys", .data = &vdecsys_clks },
  64         { /* sentinel */ }
  65 };
  66
  67 static struct platform_driver clk_mt6735_vdecsys = {
  68         .probe = mtk_clk_simple_probe,
  69         .remove = mtk_clk_simple_remove,
  70         .driver = {
  71                 .name = "clk-mt6735-vdecsys",
  72                 .of_match_table = of_match_mt6735_vdecsys,
  73         },
  74 };
  75 module_platform_driver(clk_mt6735_vdecsys);
  76
  77 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
  78 MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver");
  79 MODULE_LICENSE("GPL");