drivers/clk/mediatek/clk-mt6795-mfg.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 Collabora Ltd.
   4  * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include "clk-gate.h"
  11 #include "clk-mtk.h"
  12
  13 static const struct mtk_gate_regs mfg_cg_regs = {
  14         .set_ofs = 0x4,
  15         .clr_ofs = 0x8,
  16         .sta_ofs = 0x0,
  17 };
  18
  19 #define GATE_MFG(_id, _name, _parent, _shift)                   \
  20         GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  21
  22 static const struct mtk_gate mfg_clks[] = {
  23         GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "axi_mfg_in_sel", 0),
  24         GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "mem_mfg_in_sel", 1),
  25         GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 2),
  26         GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m", 3),
  27 };
  28
  29 static const struct mtk_clk_desc mfg_desc = {
  30         .clks = mfg_clks,
  31         .num_clks = ARRAY_SIZE(mfg_clks),
  32 };
  33
  34 static const struct of_device_id of_match_clk_mt6795_mfg[] = {
  35         { .compatible = "mediatek,mt6795-mfgcfg", .data = &mfg_desc },
  36         { /* sentinel */ }
  37 };
  38 MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_mfg);
  39
  40 static struct platform_driver clk_mt6795_mfg_drv = {
  41         .driver = {
  42                 .name = "clk-mt6795-mfg",
  43                 .of_match_table = of_match_clk_mt6795_mfg,
  44         },
  45         .probe = mtk_clk_simple_probe,
  46         .remove = mtk_clk_simple_remove,
  47 };
  48 module_platform_driver(clk_mt6795_mfg_drv);
  49
  50 MODULE_DESCRIPTION("MediaTek MT6795 mfg clocks driver");
  51 MODULE_LICENSE("GPL");