?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
printf: Remove unused 'bprintf'
[drm/drm-misc.git] / drivers / iio / imu / adis16480.c
blob294181f2fcb31483b3b5149fe75998cd7fe400ef
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADIS16480 and similar IMUs driver
4 *
5 * Copyright 2012 Analog Devices Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/bitfield.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/math.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/lcm.h>
19 #include <linux/property.h>
20 #include <linux/swab.h>
21 #include <linux/crc32.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/imu/adis.h>
26 #include <linux/iio/trigger_consumer.h>
27
28 #include <linux/debugfs.h>
29
30 #define ADIS16480_PAGE_SIZE 0x80
31
32 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
33
34 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
35 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06)
36 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08)
37 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A)
38 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C)
39 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E)
40 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10)
41 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14)
42 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18)
43 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C)
44 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20)
45 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24)
46 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28)
47 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A)
48 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C)
49 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E)
50 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40)
51 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44)
52 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48)
53 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C)
54 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50)
55 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54)
56 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E)
57
58 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04)
59 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06)
60 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08)
61 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A)
62 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C)
63 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E)
64 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10)
65 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14)
66 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18)
67 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C)
68 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20)
69 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24)
70 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28)
71 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A)
72 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C)
73 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40)
74 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C)
75
76 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02)
77 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06)
78 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08)
79 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A)
80 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C)
81 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10)
82 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16)
83 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18)
84 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20)
85 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22)
86 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24)
87 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28)
88 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A)
89 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C)
90 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E)
91 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30)
92 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32)
93 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34)
94 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36)
95 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38)
96 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A)
97 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78)
98 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A)
99 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C)
100
101 /*
102 * External clock scaling in PPS mode.
103 * Available only for ADIS1649x devices
104 */
105 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
106 #define ADIS16495_REG_BURST_CMD ADIS16480_REG(0x00, 0x7C)
107 #define ADIS16495_GYRO_ACCEL_BURST_ID 0xA5A5
108 #define ADIS16545_DELTA_ANG_VEL_BURST_ID 0xC3C3
109 /* total number of segments in burst */
110 #define ADIS16495_BURST_MAX_DATA 20
111
112 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
113
114 /* Each filter coefficent bank spans two pages */
115 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
116 ADIS16480_REG((page) + 1, (x) - 60 + 8))
117 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x))
118 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x))
119 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x))
120 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x))
121
122 /* ADIS16480_REG_FNCTIO_CTRL */
123 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)
124 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
125 #define ADIS16480_DRDY_POL_MSK BIT(2)
126 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
127 #define ADIS16480_DRDY_EN_MSK BIT(3)
128 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
129 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)
130 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
131 #define ADIS16480_SYNC_EN_MSK BIT(7)
132 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
133 #define ADIS16480_SYNC_MODE_MSK BIT(8)
134 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
135
136 #define ADIS16545_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)
137 #define ADIS16545_BURST_DATA_SEL_1_CHN_MASK GENMASK(16, 11)
138 #define ADIS16545_BURST_DATA_SEL_MASK BIT(8)
139
140 struct adis16480_chip_info {
141 unsigned int num_channels;
142 const struct iio_chan_spec *channels;
143 unsigned int gyro_max_val;
144 unsigned int gyro_max_scale;
145 unsigned int accel_max_val;
146 unsigned int accel_max_scale;
147 unsigned int temp_scale;
148 unsigned int deltang_max_val;
149 unsigned int deltvel_max_val;
150 unsigned int int_clk;
151 unsigned int max_dec_rate;
152 const unsigned int *filter_freqs;
153 bool has_pps_clk_mode;
154 bool has_sleep_cnt;
155 bool has_burst_delta_data;
156 const struct adis_data adis_data;
157 };
158
159 enum adis16480_int_pin {
160 ADIS16480_PIN_DIO1,
161 ADIS16480_PIN_DIO2,
162 ADIS16480_PIN_DIO3,
163 ADIS16480_PIN_DIO4
164 };
165
166 enum adis16480_clock_mode {
167 ADIS16480_CLK_SYNC,
168 ADIS16480_CLK_PPS,
169 ADIS16480_CLK_INT
170 };
171
172 struct adis16480 {
173 const struct adis16480_chip_info *chip_info;
174
175 struct adis adis;
176 struct clk *ext_clk;
177 enum adis16480_clock_mode clk_mode;
178 unsigned int clk_freq;
179 u16 burst_id;
180 /* Alignment needed for the timestamp */
181 __be16 data[ADIS16495_BURST_MAX_DATA] __aligned(8);
182 };
183
184 static const char * const adis16480_int_pin_names[4] = {
185 [ADIS16480_PIN_DIO1] = "DIO1",
186 [ADIS16480_PIN_DIO2] = "DIO2",
187 [ADIS16480_PIN_DIO3] = "DIO3",
188 [ADIS16480_PIN_DIO4] = "DIO4",
189 };
190
191 static bool low_rate_allow;
192 module_param(low_rate_allow, bool, 0444);
193 MODULE_PARM_DESC(low_rate_allow,
194 "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
195
196 static ssize_t adis16480_show_firmware_revision(struct file *file,
197 char __user *userbuf, size_t count, loff_t *ppos)
198 {
199 struct adis16480 *adis16480 = file->private_data;
200 char buf[7];
201 size_t len;
202 u16 rev;
203 int ret;
204
205 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
206 if (ret)
207 return ret;
208
209 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
210
211 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
212 }
213
214 static const struct file_operations adis16480_firmware_revision_fops = {
215 .open = simple_open,
216 .read = adis16480_show_firmware_revision,
217 .llseek = default_llseek,
218 .owner = THIS_MODULE,
219 };
220
221 static ssize_t adis16480_show_firmware_date(struct file *file,
222 char __user *userbuf, size_t count, loff_t *ppos)
223 {
224 struct adis16480 *adis16480 = file->private_data;
225 u16 md, year;
226 char buf[12];
227 size_t len;
228 int ret;
229
230 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
231 if (ret)
232 return ret;
233
234 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
235 if (ret)
236 return ret;
237
238 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
239 md >> 8, md & 0xff, year);
240
241 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
242 }
243
244 static const struct file_operations adis16480_firmware_date_fops = {
245 .open = simple_open,
246 .read = adis16480_show_firmware_date,
247 .llseek = default_llseek,
248 .owner = THIS_MODULE,
249 };
250
251 static int adis16480_show_serial_number(void *arg, u64 *val)
252 {
253 struct adis16480 *adis16480 = arg;
254 u16 serial;
255 int ret;
256
257 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
258 &serial);
259 if (ret)
260 return ret;
261
262 *val = serial;
263
264 return 0;
265 }
266 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
267 adis16480_show_serial_number, NULL, "0x%.4llx\n");
268
269 static int adis16480_show_product_id(void *arg, u64 *val)
270 {
271 struct adis16480 *adis16480 = arg;
272 u16 prod_id;
273 int ret;
274
275 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
276 &prod_id);
277 if (ret)
278 return ret;
279
280 *val = prod_id;
281
282 return 0;
283 }
284 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
285 adis16480_show_product_id, NULL, "%llu\n");
286
287 static int adis16480_show_flash_count(void *arg, u64 *val)
288 {
289 struct adis16480 *adis16480 = arg;
290 u32 flash_count;
291 int ret;
292
293 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
294 &flash_count);
295 if (ret)
296 return ret;
297
298 *val = flash_count;
299
300 return 0;
301 }
302 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
303 adis16480_show_flash_count, NULL, "%lld\n");
304
305 static void adis16480_debugfs_init(struct iio_dev *indio_dev)
306 {
307 struct adis16480 *adis16480 = iio_priv(indio_dev);
308 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
309
310 if (!IS_ENABLED(CONFIG_DEBUG_FS))
311 return;
312
313 debugfs_create_file_unsafe("firmware_revision", 0400,
314 d, adis16480, &adis16480_firmware_revision_fops);
315 debugfs_create_file_unsafe("firmware_date", 0400,
316 d, adis16480, &adis16480_firmware_date_fops);
317 debugfs_create_file_unsafe("serial_number", 0400,
318 d, adis16480, &adis16480_serial_number_fops);
319 debugfs_create_file_unsafe("product_id", 0400,
320 d, adis16480, &adis16480_product_id_fops);
321 debugfs_create_file_unsafe("flash_count", 0400,
322 d, adis16480, &adis16480_flash_count_fops);
323 }
324
325 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
326 {
327 struct adis16480 *st = iio_priv(indio_dev);
328 unsigned int t, sample_rate = st->clk_freq;
329 int ret;
330
331 if (val < 0 || val2 < 0)
332 return -EINVAL;
333
334 t = val * 1000 + val2 / 1000;
335 if (t == 0)
336 return -EINVAL;
337
338 adis_dev_auto_lock(&st->adis);
339 /*
340 * When using PPS mode, the input clock needs to be scaled so that we have an IMU
341 * sample rate between (optimally) 4000 and 4250. After this, we can use the
342 * decimation filter to lower the sampling rate in order to get what the user wants.
343 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
344 * the input clock. Hence, calculating the sync_scale dynamically gives us better
345 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
346 * 1. lcm of the input clock and the desired output rate.
347 * 2. get the highest multiple of the previous result lower than the adis max rate.
348 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
349 * and DEC_RATE (to get the user output rate)
350 */
351 if (st->clk_mode == ADIS16480_CLK_PPS) {
352 unsigned long scaled_rate = lcm(st->clk_freq, t);
353 int sync_scale;
354
355 /*
356 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
357 * solution. In this case, we get the highest multiple of the input clock
358 * lower than the IMU max sample rate.
359 */
360 if (scaled_rate > st->chip_info->int_clk)
361 scaled_rate = st->chip_info->int_clk / st->clk_freq * st->clk_freq;
362 else
363 scaled_rate = st->chip_info->int_clk / scaled_rate * scaled_rate;
364
365 /*
366 * This is not an hard requirement but it's not advised to run the IMU
367 * with a sample rate lower than 4000Hz due to possible undersampling
368 * issues. However, there are users that might really want to take the risk.
369 * Hence, we provide a module parameter for them. If set, we allow sample
370 * rates lower than 4KHz. By default, we won't allow this and we just roundup
371 * the rate to the next multiple of the input clock bigger than 4KHz. This
372 * is done like this as in some cases (when DEC_RATE is 0) might give
373 * us the closest value to the one desired by the user...
374 */
375 if (scaled_rate < 4000000 && !low_rate_allow)
376 scaled_rate = roundup(4000000, st->clk_freq);
377
378 sync_scale = scaled_rate / st->clk_freq;
379 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
380 if (ret)
381 return ret;
382
383 sample_rate = scaled_rate;
384 }
385
386 t = DIV_ROUND_CLOSEST(sample_rate, t);
387 if (t)
388 t--;
389
390 if (t > st->chip_info->max_dec_rate)
391 t = st->chip_info->max_dec_rate;
392
393 return __adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t);
394 }
395
396 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
397 {
398 struct adis16480 *st = iio_priv(indio_dev);
399 uint16_t t;
400 int ret;
401 unsigned int freq, sample_rate = st->clk_freq;
402
403 adis_dev_auto_lock(&st->adis);
404
405 if (st->clk_mode == ADIS16480_CLK_PPS) {
406 u16 sync_scale;
407
408 ret = __adis_read_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, &sync_scale);
409 if (ret)
410 return ret;
411
412 sample_rate = st->clk_freq * sync_scale;
413 }
414
415 ret = __adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t);
416 if (ret)
417 return ret;
418
419 freq = DIV_ROUND_CLOSEST(sample_rate, (t + 1));
420
421 *val = freq / 1000;
422 *val2 = (freq % 1000) * 1000;
423
424 return IIO_VAL_INT_PLUS_MICRO;
425 }
426
427 enum {
428 ADIS16480_SCAN_GYRO_X,
429 ADIS16480_SCAN_GYRO_Y,
430 ADIS16480_SCAN_GYRO_Z,
431 ADIS16480_SCAN_ACCEL_X,
432 ADIS16480_SCAN_ACCEL_Y,
433 ADIS16480_SCAN_ACCEL_Z,
434 ADIS16480_SCAN_MAGN_X,
435 ADIS16480_SCAN_MAGN_Y,
436 ADIS16480_SCAN_MAGN_Z,
437 ADIS16480_SCAN_BARO,
438 ADIS16480_SCAN_TEMP,
439 ADIS16480_SCAN_DELTANG_X,
440 ADIS16480_SCAN_DELTANG_Y,
441 ADIS16480_SCAN_DELTANG_Z,
442 ADIS16480_SCAN_DELTVEL_X,
443 ADIS16480_SCAN_DELTVEL_Y,
444 ADIS16480_SCAN_DELTVEL_Z,
445 };
446
447 static const unsigned int adis16480_calibbias_regs[] = {
448 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
449 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
450 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
451 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
452 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
453 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
454 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
455 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
456 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
457 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
458 };
459
460 static const unsigned int adis16480_calibscale_regs[] = {
461 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
462 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
463 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
464 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
465 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
466 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
467 };
468
469 static int adis16480_set_calibbias(struct iio_dev *indio_dev,
470 const struct iio_chan_spec *chan, int bias)
471 {
472 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
473 struct adis16480 *st = iio_priv(indio_dev);
474
475 switch (chan->type) {
476 case IIO_MAGN:
477 case IIO_PRESSURE:
478 if (bias < -0x8000 || bias >= 0x8000)
479 return -EINVAL;
480 return adis_write_reg_16(&st->adis, reg, bias);
481 case IIO_ANGL_VEL:
482 case IIO_ACCEL:
483 return adis_write_reg_32(&st->adis, reg, bias);
484 default:
485 break;
486 }
487
488 return -EINVAL;
489 }
490
491 static int adis16480_get_calibbias(struct iio_dev *indio_dev,
492 const struct iio_chan_spec *chan, int *bias)
493 {
494 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
495 struct adis16480 *st = iio_priv(indio_dev);
496 uint16_t val16;
497 uint32_t val32;
498 int ret;
499
500 switch (chan->type) {
501 case IIO_MAGN:
502 case IIO_PRESSURE:
503 ret = adis_read_reg_16(&st->adis, reg, &val16);
504 if (ret == 0)
505 *bias = sign_extend32(val16, 15);
506 break;
507 case IIO_ANGL_VEL:
508 case IIO_ACCEL:
509 ret = adis_read_reg_32(&st->adis, reg, &val32);
510 if (ret == 0)
511 *bias = sign_extend32(val32, 31);
512 break;
513 default:
514 ret = -EINVAL;
515 }
516
517 if (ret)
518 return ret;
519
520 return IIO_VAL_INT;
521 }
522
523 static int adis16480_set_calibscale(struct iio_dev *indio_dev,
524 const struct iio_chan_spec *chan, int scale)
525 {
526 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
527 struct adis16480 *st = iio_priv(indio_dev);
528
529 if (scale < -0x8000 || scale >= 0x8000)
530 return -EINVAL;
531
532 return adis_write_reg_16(&st->adis, reg, scale);
533 }
534
535 static int adis16480_get_calibscale(struct iio_dev *indio_dev,
536 const struct iio_chan_spec *chan, int *scale)
537 {
538 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
539 struct adis16480 *st = iio_priv(indio_dev);
540 uint16_t val16;
541 int ret;
542
543 ret = adis_read_reg_16(&st->adis, reg, &val16);
544 if (ret)
545 return ret;
546
547 *scale = sign_extend32(val16, 15);
548 return IIO_VAL_INT;
549 }
550
551 static const unsigned int adis16480_def_filter_freqs[] = {
552 310,
553 55,
554 275,
555 63,
556 };
557
558 static const unsigned int adis16495_def_filter_freqs[] = {
559 300,
560 100,
561 300,
562 100,
563 };
564
565 static const unsigned int ad16480_filter_data[][2] = {
566 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 },
567 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 },
568 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 },
569 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 },
570 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 },
571 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 },
572 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 },
573 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 },
574 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 },
575 };
576
577 static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
578 const struct iio_chan_spec *chan, int *freq)
579 {
580 struct adis16480 *st = iio_priv(indio_dev);
581 unsigned int enable_mask, offset, reg;
582 uint16_t val;
583 int ret;
584
585 reg = ad16480_filter_data[chan->scan_index][0];
586 offset = ad16480_filter_data[chan->scan_index][1];
587 enable_mask = BIT(offset + 2);
588
589 ret = adis_read_reg_16(&st->adis, reg, &val);
590 if (ret)
591 return ret;
592
593 if (!(val & enable_mask))
594 *freq = 0;
595 else
596 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
597
598 return IIO_VAL_INT;
599 }
600
601 static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
602 const struct iio_chan_spec *chan, unsigned int freq)
603 {
604 struct adis16480 *st = iio_priv(indio_dev);
605 unsigned int enable_mask, offset, reg;
606 unsigned int diff, best_diff;
607 unsigned int i, best_freq;
608 uint16_t val;
609 int ret;
610
611 reg = ad16480_filter_data[chan->scan_index][0];
612 offset = ad16480_filter_data[chan->scan_index][1];
613 enable_mask = BIT(offset + 2);
614
615 adis_dev_auto_lock(&st->adis);
616
617 ret = __adis_read_reg_16(&st->adis, reg, &val);
618 if (ret)
619 return ret;
620
621 if (freq == 0) {
622 val &= ~enable_mask;
623 } else {
624 best_freq = 0;
625 best_diff = st->chip_info->filter_freqs[0];
626 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
627 if (st->chip_info->filter_freqs[i] >= freq) {
628 diff = st->chip_info->filter_freqs[i] - freq;
629 if (diff < best_diff) {
630 best_diff = diff;
631 best_freq = i;
632 }
633 }
634 }
635
636 val &= ~(0x3 << offset);
637 val |= best_freq << offset;
638 val |= enable_mask;
639 }
640
641 return __adis_write_reg_16(&st->adis, reg, val);
642 }
643
644 static int adis16480_read_raw(struct iio_dev *indio_dev,
645 const struct iio_chan_spec *chan, int *val, int *val2, long info)
646 {
647 struct adis16480 *st = iio_priv(indio_dev);
648 unsigned int temp;
649
650 switch (info) {
651 case IIO_CHAN_INFO_RAW:
652 return adis_single_conversion(indio_dev, chan, 0, val);
653 case IIO_CHAN_INFO_SCALE:
654 switch (chan->type) {
655 case IIO_ANGL_VEL:
656 *val = st->chip_info->gyro_max_scale;
657 *val2 = st->chip_info->gyro_max_val;
658 return IIO_VAL_FRACTIONAL;
659 case IIO_ACCEL:
660 *val = st->chip_info->accel_max_scale;
661 *val2 = st->chip_info->accel_max_val;
662 return IIO_VAL_FRACTIONAL;
663 case IIO_MAGN:
664 *val = 0;
665 *val2 = 100; /* 0.0001 gauss */
666 return IIO_VAL_INT_PLUS_MICRO;
667 case IIO_TEMP:
668 /*
669 * +85 degrees Celsius = temp_max_scale
670 * +25 degrees Celsius = 0
671 * LSB, 25 degrees Celsius = 60 / temp_max_scale
672 */
673 *val = st->chip_info->temp_scale / 1000;
674 *val2 = (st->chip_info->temp_scale % 1000) * 1000;
675 return IIO_VAL_INT_PLUS_MICRO;
676 case IIO_PRESSURE:
677 /*
678 * max scale is 1310 mbar
679 * max raw value is 32767 shifted for 32bits
680 */
681 *val = 131; /* 1310mbar = 131 kPa */
682 *val2 = 32767 << 16;
683 return IIO_VAL_FRACTIONAL;
684 case IIO_DELTA_ANGL:
685 *val = st->chip_info->deltang_max_val;
686 *val2 = 31;
687 return IIO_VAL_FRACTIONAL_LOG2;
688 case IIO_DELTA_VELOCITY:
689 *val = st->chip_info->deltvel_max_val;
690 *val2 = 31;
691 return IIO_VAL_FRACTIONAL_LOG2;
692 default:
693 return -EINVAL;
694 }
695 case IIO_CHAN_INFO_OFFSET:
696 /* Only the temperature channel has a offset */
697 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
698 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
699 return IIO_VAL_INT;
700 case IIO_CHAN_INFO_CALIBBIAS:
701 return adis16480_get_calibbias(indio_dev, chan, val);
702 case IIO_CHAN_INFO_CALIBSCALE:
703 return adis16480_get_calibscale(indio_dev, chan, val);
704 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
705 return adis16480_get_filter_freq(indio_dev, chan, val);
706 case IIO_CHAN_INFO_SAMP_FREQ:
707 return adis16480_get_freq(indio_dev, val, val2);
708 default:
709 return -EINVAL;
710 }
711 }
712
713 static int adis16480_write_raw(struct iio_dev *indio_dev,
714 const struct iio_chan_spec *chan, int val, int val2, long info)
715 {
716 switch (info) {
717 case IIO_CHAN_INFO_CALIBBIAS:
718 return adis16480_set_calibbias(indio_dev, chan, val);
719 case IIO_CHAN_INFO_CALIBSCALE:
720 return adis16480_set_calibscale(indio_dev, chan, val);
721 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
722 return adis16480_set_filter_freq(indio_dev, chan, val);
723 case IIO_CHAN_INFO_SAMP_FREQ:
724 return adis16480_set_freq(indio_dev, val, val2);
725
726 default:
727 return -EINVAL;
728 }
729 }
730
731 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
732 { \
733 .type = (_type), \
734 .modified = 1, \
735 .channel2 = (_mod), \
736 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
737 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
738 _info_sep, \
739 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
740 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
741 .address = (_address), \
742 .scan_index = (_si), \
743 .scan_type = { \
744 .sign = 's', \
745 .realbits = (_bits), \
746 .storagebits = (_bits), \
747 .endianness = IIO_BE, \
748 }, \
749 }
750
751 #define ADIS16480_GYRO_CHANNEL(_mod) \
752 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
753 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
754 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
755 BIT(IIO_CHAN_INFO_CALIBSCALE), \
756 32)
757
758 #define ADIS16480_ACCEL_CHANNEL(_mod) \
759 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
760 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
761 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
762 BIT(IIO_CHAN_INFO_CALIBSCALE), \
763 32)
764
765 #define ADIS16480_DELTANG_CHANNEL(_mod) \
766 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
767 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, ADIS16480_SCAN_DELTANG_ ## _mod, \
768 0, 32)
769
770 #define ADIS16480_DELTANG_CHANNEL_NO_SCAN(_mod) \
771 ADIS16480_MOD_CHANNEL(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
772 ADIS16480_REG_ ## _mod ## _DELTAANG_OUT, -1, 0, 32)
773
774 #define ADIS16480_DELTVEL_CHANNEL(_mod) \
775 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
776 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, ADIS16480_SCAN_DELTVEL_ ## _mod, \
777 0, 32)
778
779 #define ADIS16480_DELTVEL_CHANNEL_NO_SCAN(_mod) \
780 ADIS16480_MOD_CHANNEL(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
781 ADIS16480_REG_ ## _mod ## _DELTAVEL_OUT, -1, 0, 32)
782
783 #define ADIS16480_MAGN_CHANNEL(_mod) \
784 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
785 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
786 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
787 16)
788
789 #define ADIS16480_PRESSURE_CHANNEL() \
790 { \
791 .type = IIO_PRESSURE, \
792 .indexed = 1, \
793 .channel = 0, \
794 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
795 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
796 BIT(IIO_CHAN_INFO_SCALE), \
797 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
798 .address = ADIS16480_REG_BAROM_OUT, \
799 .scan_index = ADIS16480_SCAN_BARO, \
800 .scan_type = { \
801 .sign = 's', \
802 .realbits = 32, \
803 .storagebits = 32, \
804 .endianness = IIO_BE, \
805 }, \
806 }
807
808 #define ADIS16480_TEMP_CHANNEL() { \
809 .type = IIO_TEMP, \
810 .indexed = 1, \
811 .channel = 0, \
812 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
813 BIT(IIO_CHAN_INFO_SCALE) | \
814 BIT(IIO_CHAN_INFO_OFFSET), \
815 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
816 .address = ADIS16480_REG_TEMP_OUT, \
817 .scan_index = ADIS16480_SCAN_TEMP, \
818 .scan_type = { \
819 .sign = 's', \
820 .realbits = 16, \
821 .storagebits = 16, \
822 .endianness = IIO_BE, \
823 }, \
824 }
825
826 static const struct iio_chan_spec adis16480_channels[] = {
827 ADIS16480_GYRO_CHANNEL(X),
828 ADIS16480_GYRO_CHANNEL(Y),
829 ADIS16480_GYRO_CHANNEL(Z),
830 ADIS16480_ACCEL_CHANNEL(X),
831 ADIS16480_ACCEL_CHANNEL(Y),
832 ADIS16480_ACCEL_CHANNEL(Z),
833 ADIS16480_MAGN_CHANNEL(X),
834 ADIS16480_MAGN_CHANNEL(Y),
835 ADIS16480_MAGN_CHANNEL(Z),
836 ADIS16480_PRESSURE_CHANNEL(),
837 ADIS16480_TEMP_CHANNEL(),
838 IIO_CHAN_SOFT_TIMESTAMP(11),
839 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
840 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
841 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
842 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
843 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
844 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
845 };
846
847 static const struct iio_chan_spec adis16485_channels[] = {
848 ADIS16480_GYRO_CHANNEL(X),
849 ADIS16480_GYRO_CHANNEL(Y),
850 ADIS16480_GYRO_CHANNEL(Z),
851 ADIS16480_ACCEL_CHANNEL(X),
852 ADIS16480_ACCEL_CHANNEL(Y),
853 ADIS16480_ACCEL_CHANNEL(Z),
854 ADIS16480_TEMP_CHANNEL(),
855 IIO_CHAN_SOFT_TIMESTAMP(7),
856 ADIS16480_DELTANG_CHANNEL_NO_SCAN(X),
857 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Y),
858 ADIS16480_DELTANG_CHANNEL_NO_SCAN(Z),
859 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(X),
860 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Y),
861 ADIS16480_DELTVEL_CHANNEL_NO_SCAN(Z),
862 };
863
864 static const struct iio_chan_spec adis16545_channels[] = {
865 ADIS16480_GYRO_CHANNEL(X),
866 ADIS16480_GYRO_CHANNEL(Y),
867 ADIS16480_GYRO_CHANNEL(Z),
868 ADIS16480_ACCEL_CHANNEL(X),
869 ADIS16480_ACCEL_CHANNEL(Y),
870 ADIS16480_ACCEL_CHANNEL(Z),
871 ADIS16480_TEMP_CHANNEL(),
872 ADIS16480_DELTANG_CHANNEL(X),
873 ADIS16480_DELTANG_CHANNEL(Y),
874 ADIS16480_DELTANG_CHANNEL(Z),
875 ADIS16480_DELTVEL_CHANNEL(X),
876 ADIS16480_DELTVEL_CHANNEL(Y),
877 ADIS16480_DELTVEL_CHANNEL(Z),
878 IIO_CHAN_SOFT_TIMESTAMP(17),
879 };
880
881 enum adis16480_variant {
882 ADIS16375,
883 ADIS16480,
884 ADIS16485,
885 ADIS16488,
886 ADIS16490,
887 ADIS16495_1,
888 ADIS16495_2,
889 ADIS16495_3,
890 ADIS16497_1,
891 ADIS16497_2,
892 ADIS16497_3,
893 ADIS16545_1,
894 ADIS16545_2,
895 ADIS16545_3,
896 ADIS16547_1,
897 ADIS16547_2,
898 ADIS16547_3
899 };
900
901 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
902 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
903 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
904 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
905 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
906 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
907 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
908 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
909 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
910 #define ADIS16480_DIAG_STAT_BARO_FAIL 11
911
912 static const char * const adis16480_status_error_msgs[] = {
913 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
914 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
915 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
916 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
917 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
918 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
919 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
920 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
921 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
922 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
923 };
924
925 static int adis16480_enable_irq(struct adis *adis, bool enable);
926
927 #define ADIS16480_DATA(_prod_id, _timeouts, _burst_len, _burst_max_speed) \
928 { \
929 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \
930 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \
931 .prod_id_reg = ADIS16480_REG_PROD_ID, \
932 .prod_id = (_prod_id), \
933 .has_paging = true, \
934 .read_delay = 5, \
935 .write_delay = 5, \
936 .self_test_mask = BIT(1), \
937 .self_test_reg = ADIS16480_REG_GLOB_CMD, \
938 .status_error_msgs = adis16480_status_error_msgs, \
939 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \
940 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \
941 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \
942 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \
943 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \
944 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \
945 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \
946 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \
947 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \
948 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \
949 .enable_irq = adis16480_enable_irq, \
950 .timeouts = (_timeouts), \
951 .burst_reg_cmd = ADIS16495_REG_BURST_CMD, \
952 .burst_len = (_burst_len), \
953 .burst_max_speed_hz = _burst_max_speed \
954 }
955
956 static const struct adis_timeout adis16485_timeouts = {
957 .reset_ms = 560,
958 .sw_reset_ms = 120,
959 .self_test_ms = 12,
960 };
961
962 static const struct adis_timeout adis16480_timeouts = {
963 .reset_ms = 560,
964 .sw_reset_ms = 560,
965 .self_test_ms = 12,
966 };
967
968 static const struct adis_timeout adis16495_timeouts = {
969 .reset_ms = 170,
970 .sw_reset_ms = 130,
971 .self_test_ms = 40,
972 };
973
974 static const struct adis_timeout adis16495_1_timeouts = {
975 .reset_ms = 250,
976 .sw_reset_ms = 210,
977 .self_test_ms = 20,
978 };
979
980 static const struct adis_timeout adis16545_timeouts = {
981 .reset_ms = 315,
982 .sw_reset_ms = 270,
983 .self_test_ms = 35,
984 };
985
986 static const struct adis16480_chip_info adis16480_chip_info[] = {
987 [ADIS16375] = {
988 .channels = adis16485_channels,
989 .num_channels = ARRAY_SIZE(adis16485_channels),
990 /*
991 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which
992 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since
993 * it gives better approximation. However, in this case we
994 * cannot do it since it would not fit in a 32bit variable.
995 */
996 .gyro_max_val = 22887 << 16,
997 .gyro_max_scale = IIO_DEGREE_TO_RAD(300),
998 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
999 .accel_max_scale = 18,
1000 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1001 .deltang_max_val = IIO_DEGREE_TO_RAD(180),
1002 .deltvel_max_val = 100,
1003 .int_clk = 2460000,
1004 .max_dec_rate = 2048,
1005 .has_sleep_cnt = true,
1006 .filter_freqs = adis16480_def_filter_freqs,
1007 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts, 0, 0),
1008 },
1009 [ADIS16480] = {
1010 .channels = adis16480_channels,
1011 .num_channels = ARRAY_SIZE(adis16480_channels),
1012 .gyro_max_val = 22500 << 16,
1013 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1014 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
1015 .accel_max_scale = 10,
1016 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1017 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1018 .deltvel_max_val = 200,
1019 .int_clk = 2460000,
1020 .max_dec_rate = 2048,
1021 .has_sleep_cnt = true,
1022 .filter_freqs = adis16480_def_filter_freqs,
1023 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts, 0, 0),
1024 },
1025 [ADIS16485] = {
1026 .channels = adis16485_channels,
1027 .num_channels = ARRAY_SIZE(adis16485_channels),
1028 .gyro_max_val = 22500 << 16,
1029 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1030 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
1031 .accel_max_scale = 5,
1032 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1033 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1034 .deltvel_max_val = 50,
1035 .int_clk = 2460000,
1036 .max_dec_rate = 2048,
1037 .has_sleep_cnt = true,
1038 .filter_freqs = adis16480_def_filter_freqs,
1039 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts, 0, 0),
1040 },
1041 [ADIS16488] = {
1042 .channels = adis16480_channels,
1043 .num_channels = ARRAY_SIZE(adis16480_channels),
1044 .gyro_max_val = 22500 << 16,
1045 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1046 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
1047 .accel_max_scale = 18,
1048 .temp_scale = 5650, /* 5.65 milli degree Celsius */
1049 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1050 .deltvel_max_val = 200,
1051 .int_clk = 2460000,
1052 .max_dec_rate = 2048,
1053 .has_sleep_cnt = true,
1054 .filter_freqs = adis16480_def_filter_freqs,
1055 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts, 0, 0),
1056 },
1057 [ADIS16490] = {
1058 .channels = adis16485_channels,
1059 .num_channels = ARRAY_SIZE(adis16485_channels),
1060 .gyro_max_val = 20000 << 16,
1061 .gyro_max_scale = IIO_DEGREE_TO_RAD(100),
1062 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
1063 .accel_max_scale = 8,
1064 .temp_scale = 14285, /* 14.285 milli degree Celsius */
1065 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1066 .deltvel_max_val = 200,
1067 .int_clk = 4250000,
1068 .max_dec_rate = 4250,
1069 .filter_freqs = adis16495_def_filter_freqs,
1070 .has_pps_clk_mode = true,
1071 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts, 0, 0),
1072 },
1073 [ADIS16495_1] = {
1074 .channels = adis16485_channels,
1075 .num_channels = ARRAY_SIZE(adis16485_channels),
1076 .gyro_max_val = 20000 << 16,
1077 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1078 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1079 .accel_max_scale = 8,
1080 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1081 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1082 .deltvel_max_val = 100,
1083 .int_clk = 4250000,
1084 .max_dec_rate = 4250,
1085 .filter_freqs = adis16495_def_filter_freqs,
1086 .has_pps_clk_mode = true,
1087 /* 20 elements of 16bits */
1088 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1089 ADIS16495_BURST_MAX_DATA * 2,
1090 6000000),
1091 },
1092 [ADIS16495_2] = {
1093 .channels = adis16485_channels,
1094 .num_channels = ARRAY_SIZE(adis16485_channels),
1095 .gyro_max_val = 18000 << 16,
1096 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1097 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1098 .accel_max_scale = 8,
1099 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1100 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1101 .deltvel_max_val = 100,
1102 .int_clk = 4250000,
1103 .max_dec_rate = 4250,
1104 .filter_freqs = adis16495_def_filter_freqs,
1105 .has_pps_clk_mode = true,
1106 /* 20 elements of 16bits */
1107 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1108 ADIS16495_BURST_MAX_DATA * 2,
1109 6000000),
1110 },
1111 [ADIS16495_3] = {
1112 .channels = adis16485_channels,
1113 .num_channels = ARRAY_SIZE(adis16485_channels),
1114 .gyro_max_val = 20000 << 16,
1115 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1116 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1117 .accel_max_scale = 8,
1118 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1119 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1120 .deltvel_max_val = 100,
1121 .int_clk = 4250000,
1122 .max_dec_rate = 4250,
1123 .filter_freqs = adis16495_def_filter_freqs,
1124 .has_pps_clk_mode = true,
1125 /* 20 elements of 16bits */
1126 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts,
1127 ADIS16495_BURST_MAX_DATA * 2,
1128 6000000),
1129 },
1130 [ADIS16497_1] = {
1131 .channels = adis16485_channels,
1132 .num_channels = ARRAY_SIZE(adis16485_channels),
1133 .gyro_max_val = 20000 << 16,
1134 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1135 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1136 .accel_max_scale = 40,
1137 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1138 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1139 .deltvel_max_val = 400,
1140 .int_clk = 4250000,
1141 .max_dec_rate = 4250,
1142 .filter_freqs = adis16495_def_filter_freqs,
1143 .has_pps_clk_mode = true,
1144 /* 20 elements of 16bits */
1145 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1146 ADIS16495_BURST_MAX_DATA * 2,
1147 6000000),
1148 },
1149 [ADIS16497_2] = {
1150 .channels = adis16485_channels,
1151 .num_channels = ARRAY_SIZE(adis16485_channels),
1152 .gyro_max_val = 18000 << 16,
1153 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1154 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1155 .accel_max_scale = 40,
1156 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1157 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1158 .deltvel_max_val = 400,
1159 .int_clk = 4250000,
1160 .max_dec_rate = 4250,
1161 .filter_freqs = adis16495_def_filter_freqs,
1162 .has_pps_clk_mode = true,
1163 /* 20 elements of 16bits */
1164 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1165 ADIS16495_BURST_MAX_DATA * 2,
1166 6000000),
1167 },
1168 [ADIS16497_3] = {
1169 .channels = adis16485_channels,
1170 .num_channels = ARRAY_SIZE(adis16485_channels),
1171 .gyro_max_val = 20000 << 16,
1172 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1173 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1174 .accel_max_scale = 40,
1175 .temp_scale = 12500, /* 12.5 milli degree Celsius */
1176 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1177 .deltvel_max_val = 400,
1178 .int_clk = 4250000,
1179 .max_dec_rate = 4250,
1180 .filter_freqs = adis16495_def_filter_freqs,
1181 .has_pps_clk_mode = true,
1182 /* 20 elements of 16bits */
1183 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts,
1184 ADIS16495_BURST_MAX_DATA * 2,
1185 6000000),
1186 },
1187 [ADIS16545_1] = {
1188 .channels = adis16545_channels,
1189 .num_channels = ARRAY_SIZE(adis16545_channels),
1190 .gyro_max_val = 20000 << 16,
1191 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1192 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1193 .accel_max_scale = 8,
1194 .temp_scale = 7000, /* 7 milli degree Celsius */
1195 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1196 .deltvel_max_val = 100,
1197 .int_clk = 4250000,
1198 .max_dec_rate = 4250,
1199 .filter_freqs = adis16495_def_filter_freqs,
1200 .has_pps_clk_mode = true,
1201 .has_burst_delta_data = true,
1202 /* 20 elements of 16bits */
1203 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1204 ADIS16495_BURST_MAX_DATA * 2,
1205 6500000),
1206 },
1207 [ADIS16545_2] = {
1208 .channels = adis16545_channels,
1209 .num_channels = ARRAY_SIZE(adis16545_channels),
1210 .gyro_max_val = 18000 << 16,
1211 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1212 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1213 .accel_max_scale = 8,
1214 .temp_scale = 7000, /* 7 milli degree Celsius */
1215 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1216 .deltvel_max_val = 100,
1217 .int_clk = 4250000,
1218 .max_dec_rate = 4250,
1219 .filter_freqs = adis16495_def_filter_freqs,
1220 .has_pps_clk_mode = true,
1221 .has_burst_delta_data = true,
1222 /* 20 elements of 16bits */
1223 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1224 ADIS16495_BURST_MAX_DATA * 2,
1225 6500000),
1226 },
1227 [ADIS16545_3] = {
1228 .channels = adis16545_channels,
1229 .num_channels = ARRAY_SIZE(adis16545_channels),
1230 .gyro_max_val = 20000 << 16,
1231 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1232 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1233 .accel_max_scale = 8,
1234 .temp_scale = 7000, /* 7 milli degree Celsius */
1235 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1236 .deltvel_max_val = 100,
1237 .int_clk = 4250000,
1238 .max_dec_rate = 4250,
1239 .filter_freqs = adis16495_def_filter_freqs,
1240 .has_pps_clk_mode = true,
1241 .has_burst_delta_data = true,
1242 /* 20 elements of 16bits */
1243 .adis_data = ADIS16480_DATA(16545, &adis16545_timeouts,
1244 ADIS16495_BURST_MAX_DATA * 2,
1245 6500000),
1246 },
1247 [ADIS16547_1] = {
1248 .channels = adis16545_channels,
1249 .num_channels = ARRAY_SIZE(adis16545_channels),
1250 .gyro_max_val = 20000 << 16,
1251 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
1252 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1253 .accel_max_scale = 40,
1254 .temp_scale = 7000, /* 7 milli degree Celsius */
1255 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1256 .deltvel_max_val = 400,
1257 .int_clk = 4250000,
1258 .max_dec_rate = 4250,
1259 .filter_freqs = adis16495_def_filter_freqs,
1260 .has_pps_clk_mode = true,
1261 .has_burst_delta_data = true,
1262 /* 20 elements of 16bits */
1263 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1264 ADIS16495_BURST_MAX_DATA * 2,
1265 6500000),
1266 },
1267 [ADIS16547_2] = {
1268 .channels = adis16545_channels,
1269 .num_channels = ARRAY_SIZE(adis16545_channels),
1270 .gyro_max_val = 18000 << 16,
1271 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
1272 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1273 .accel_max_scale = 40,
1274 .temp_scale = 7000, /* 7 milli degree Celsius */
1275 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1276 .deltvel_max_val = 400,
1277 .int_clk = 4250000,
1278 .max_dec_rate = 4250,
1279 .filter_freqs = adis16495_def_filter_freqs,
1280 .has_pps_clk_mode = true,
1281 .has_burst_delta_data = true,
1282 /* 20 elements of 16bits */
1283 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1284 ADIS16495_BURST_MAX_DATA * 2,
1285 6500000),
1286 },
1287 [ADIS16547_3] = {
1288 .channels = adis16545_channels,
1289 .num_channels = ARRAY_SIZE(adis16545_channels),
1290 .gyro_max_val = 20000 << 16,
1291 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
1292 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
1293 .accel_max_scale = 40,
1294 .temp_scale = 7000, /* 7 milli degree Celsius */
1295 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1296 .deltvel_max_val = 400,
1297 .int_clk = 4250000,
1298 .max_dec_rate = 4250,
1299 .filter_freqs = adis16495_def_filter_freqs,
1300 .has_pps_clk_mode = true,
1301 .has_burst_delta_data = true,
1302 /* 20 elements of 16bits */
1303 .adis_data = ADIS16480_DATA(16547, &adis16545_timeouts,
1304 ADIS16495_BURST_MAX_DATA * 2,
1305 6500000),
1306 },
1307 };
1308
1309 static bool adis16480_validate_crc(const u16 *buf, const u8 n_elem, const u32 crc)
1310 {
1311 u32 crc_calc;
1312 u16 crc_buf[15];
1313 int j;
1314
1315 for (j = 0; j < n_elem; j++)
1316 crc_buf[j] = swab16(buf[j]);
1317
1318 crc_calc = crc32(~0, crc_buf, n_elem * 2);
1319 crc_calc ^= ~0;
1320
1321 return (crc == crc_calc);
1322 }
1323
1324 static irqreturn_t adis16480_trigger_handler(int irq, void *p)
1325 {
1326 struct iio_poll_func *pf = p;
1327 struct iio_dev *indio_dev = pf->indio_dev;
1328 struct adis16480 *st = iio_priv(indio_dev);
1329 struct adis *adis = &st->adis;
1330 struct device *dev = &adis->spi->dev;
1331 int ret, bit, offset, i = 0, buff_offset = 0;
1332 __be16 *buffer;
1333 u32 crc;
1334 bool valid;
1335
1336 adis_dev_auto_scoped_lock(adis) {
1337 if (adis->current_page != 0) {
1338 adis->tx[0] = ADIS_WRITE_REG(ADIS_REG_PAGE_ID);
1339 adis->tx[1] = 0;
1340 ret = spi_write(adis->spi, adis->tx, 2);
1341 if (ret) {
1342 dev_err(dev, "Failed to change device page: %d\n", ret);
1343 goto irq_done;
1344 }
1345
1346 adis->current_page = 0;
1347 }
1348
1349 ret = spi_sync(adis->spi, &adis->msg);
1350 if (ret) {
1351 dev_err(dev, "Failed to read data: %d\n", ret);
1352 goto irq_done;
1353 }
1354 }
1355
1356 /*
1357 * After making the burst request, the response can have one or two
1358 * 16-bit responses containing the BURST_ID depending on the sclk. If
1359 * clk > 3.6MHz, then we will have two BURST_ID in a row. If clk < 3MHZ,
1360 * we have only one. To manage that variation, we use the transition from the
1361 * BURST_ID to the SYS_E_FLAG register, which will not be equal to 0xA5A5/0xC3C3.
1362 * If we not find this variation in the first 4 segments, then the data should
1363 * not be valid.
1364 */
1365 buffer = adis->buffer;
1366 for (offset = 0; offset < 4; offset++) {
1367 u16 curr = be16_to_cpu(buffer[offset]);
1368 u16 next = be16_to_cpu(buffer[offset + 1]);
1369
1370 if (curr == st->burst_id && next != st->burst_id) {
1371 offset++;
1372 break;
1373 }
1374 }
1375
1376 if (offset == 4) {
1377 dev_err(dev, "Invalid burst data\n");
1378 goto irq_done;
1379 }
1380
1381 crc = be16_to_cpu(buffer[offset + 16]) << 16 | be16_to_cpu(buffer[offset + 15]);
1382 valid = adis16480_validate_crc((u16 *)&buffer[offset], 15, crc);
1383 if (!valid) {
1384 dev_err(dev, "Invalid crc\n");
1385 goto irq_done;
1386 }
1387
1388 iio_for_each_active_channel(indio_dev, bit) {
1389 /*
1390 * When burst mode is used, temperature is the first data
1391 * channel in the sequence, but the temperature scan index
1392 * is 10.
1393 */
1394 switch (bit) {
1395 case ADIS16480_SCAN_TEMP:
1396 st->data[i++] = buffer[offset + 1];
1397 /*
1398 * The temperature channel has 16-bit storage size.
1399 * We need to perform the padding to have the buffer
1400 * elements naturally aligned in case there are any
1401 * 32-bit storage size channels enabled which are added
1402 * in the buffer after the temprature data. In case
1403 * there is no data being added after the temperature
1404 * data, the padding is harmless.
1405 */
1406 st->data[i++] = 0;
1407 break;
1408 case ADIS16480_SCAN_DELTANG_X ... ADIS16480_SCAN_DELTVEL_Z:
1409 buff_offset = ADIS16480_SCAN_DELTANG_X;
1410 fallthrough;
1411 case ADIS16480_SCAN_GYRO_X ... ADIS16480_SCAN_ACCEL_Z:
1412 /* The lower register data is sequenced first */
1413 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 3];
1414 st->data[i++] = buffer[2 * (bit - buff_offset) + offset + 2];
1415 break;
1416 }
1417 }
1418
1419 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1420 irq_done:
1421 iio_trigger_notify_done(indio_dev->trig);
1422
1423 return IRQ_HANDLED;
1424 }
1425
1426 static const unsigned long adis16545_channel_masks[] = {
1427 ADIS16545_BURST_DATA_SEL_0_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1428 ADIS16545_BURST_DATA_SEL_1_CHN_MASK | BIT(ADIS16480_SCAN_TEMP) | BIT(17),
1429 0,
1430 };
1431
1432 static int adis16480_update_scan_mode(struct iio_dev *indio_dev,
1433 const unsigned long *scan_mask)
1434 {
1435 u16 en;
1436 int ret;
1437 struct adis16480 *st = iio_priv(indio_dev);
1438
1439 if (st->chip_info->has_burst_delta_data) {
1440 if (*scan_mask & ADIS16545_BURST_DATA_SEL_0_CHN_MASK) {
1441 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 0);
1442 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1443 } else {
1444 en = FIELD_PREP(ADIS16545_BURST_DATA_SEL_MASK, 1);
1445 st->burst_id = ADIS16545_DELTA_ANG_VEL_BURST_ID;
1446 }
1447
1448 ret = __adis_update_bits(&st->adis, ADIS16480_REG_CONFIG,
1449 ADIS16545_BURST_DATA_SEL_MASK, en);
1450 if (ret)
1451 return ret;
1452 }
1453
1454 return adis_update_scan_mode(indio_dev, scan_mask);
1455 }
1456
1457 static const struct iio_info adis16480_info = {
1458 .read_raw = &adis16480_read_raw,
1459 .write_raw = &adis16480_write_raw,
1460 .update_scan_mode = &adis16480_update_scan_mode,
1461 .debugfs_reg_access = adis_debugfs_reg_access,
1462 };
1463
1464 static int adis16480_stop_device(struct iio_dev *indio_dev)
1465 {
1466 struct adis16480 *st = iio_priv(indio_dev);
1467 struct device *dev = &st->adis.spi->dev;
1468 int ret;
1469
1470 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
1471 if (ret)
1472 dev_err(dev, "Could not power down device: %d\n", ret);
1473
1474 return ret;
1475 }
1476
1477 static int adis16480_enable_irq(struct adis *adis, bool enable)
1478 {
1479 uint16_t val;
1480 int ret;
1481
1482 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1483 if (ret)
1484 return ret;
1485
1486 val &= ~ADIS16480_DRDY_EN_MSK;
1487 val |= ADIS16480_DRDY_EN(enable);
1488
1489 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
1490 }
1491
1492 static int adis16480_config_irq_pin(struct adis16480 *st)
1493 {
1494 struct device *dev = &st->adis.spi->dev;
1495 struct fwnode_handle *fwnode = dev_fwnode(dev);
1496 enum adis16480_int_pin pin;
1497 unsigned int irq_type;
1498 uint16_t val;
1499 int i, irq = 0;
1500
1501 /* Disable data ready since the default after reset is on */
1502 val = ADIS16480_DRDY_EN(0);
1503
1504 /*
1505 * Get the interrupt from the devicetre by reading the interrupt-names
1506 * property. If it is not specified, use DIO1 pin as default.
1507 * According to the datasheet, the factory default assigns DIO2 as data
1508 * ready signal. However, in the previous versions of the driver, DIO1
1509 * pin was used. So, we should leave it as is since some devices might
1510 * be expecting the interrupt on the wrong physical pin.
1511 */
1512 pin = ADIS16480_PIN_DIO1;
1513 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1514 irq = fwnode_irq_get_byname(fwnode, adis16480_int_pin_names[i]);
1515 if (irq > 0) {
1516 pin = i;
1517 break;
1518 }
1519 }
1520
1521 val |= ADIS16480_DRDY_SEL(pin);
1522
1523 /*
1524 * Get the interrupt line behaviour. The data ready polarity can be
1525 * configured as positive or negative, corresponding to
1526 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively.
1527 */
1528 irq_type = irq_get_trigger_type(st->adis.spi->irq);
1529 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */
1530 val |= ADIS16480_DRDY_POL(1);
1531 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1532 val |= ADIS16480_DRDY_POL(0);
1533 } else {
1534 dev_err(dev, "Invalid interrupt type 0x%x specified\n", irq_type);
1535 return -EINVAL;
1536 }
1537 /* Write the data ready configuration to the FNCTIO_CTRL register */
1538 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1539 }
1540
1541 static int adis16480_fw_get_ext_clk_pin(struct adis16480 *st)
1542 {
1543 struct device *dev = &st->adis.spi->dev;
1544 const char *ext_clk_pin;
1545 enum adis16480_int_pin pin;
1546 int i;
1547
1548 pin = ADIS16480_PIN_DIO2;
1549 if (device_property_read_string(dev, "adi,ext-clk-pin", &ext_clk_pin))
1550 goto clk_input_not_found;
1551
1552 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1553 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1554 return i;
1555 }
1556
1557 clk_input_not_found:
1558 dev_info(dev, "clk input line not specified, using DIO2\n");
1559 return pin;
1560 }
1561
1562 static int adis16480_ext_clk_config(struct adis16480 *st, bool enable)
1563 {
1564 struct device *dev = &st->adis.spi->dev;
1565 unsigned int mode, mask;
1566 enum adis16480_int_pin pin;
1567 uint16_t val;
1568 int ret;
1569
1570 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1571 if (ret)
1572 return ret;
1573
1574 pin = adis16480_fw_get_ext_clk_pin(st);
1575 /*
1576 * Each DIOx pin supports only one function at a time. When a single pin
1577 * has two assignments, the enable bit for a lower priority function
1578 * automatically resets to zero (disabling the lower priority function).
1579 */
1580 if (pin == ADIS16480_DRDY_SEL(val))
1581 dev_warn(dev, "DIO%x pin supports only one function at a time\n", pin + 1);
1582
1583 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1584 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1585 /* Only ADIS1649x devices support pps ext clock mode */
1586 if (st->chip_info->has_pps_clk_mode) {
1587 mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1588 mask |= ADIS16480_SYNC_MODE_MSK;
1589 }
1590
1591 val &= ~mask;
1592 val |= mode;
1593
1594 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1595 if (ret)
1596 return ret;
1597
1598 return clk_prepare_enable(st->ext_clk);
1599 }
1600
1601 static int adis16480_get_ext_clocks(struct adis16480 *st)
1602 {
1603 struct device *dev = &st->adis.spi->dev;
1604
1605 st->ext_clk = devm_clk_get_optional(dev, "sync");
1606 if (IS_ERR(st->ext_clk))
1607 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1608 if (st->ext_clk) {
1609 st->clk_mode = ADIS16480_CLK_SYNC;
1610 return 0;
1611 }
1612
1613 if (st->chip_info->has_pps_clk_mode) {
1614 st->ext_clk = devm_clk_get_optional(dev, "pps");
1615 if (IS_ERR(st->ext_clk))
1616 return dev_err_probe(dev, PTR_ERR(st->ext_clk), "failed to get ext clk\n");
1617 if (st->ext_clk) {
1618 st->clk_mode = ADIS16480_CLK_PPS;
1619 return 0;
1620 }
1621 }
1622
1623 st->clk_mode = ADIS16480_CLK_INT;
1624 return 0;
1625 }
1626
1627 static void adis16480_stop(void *data)
1628 {
1629 adis16480_stop_device(data);
1630 }
1631
1632 static void adis16480_clk_disable(void *data)
1633 {
1634 clk_disable_unprepare(data);
1635 }
1636
1637 static int adis16480_probe(struct spi_device *spi)
1638 {
1639 const struct spi_device_id *id = spi_get_device_id(spi);
1640 const struct adis_data *adis16480_data;
1641 irq_handler_t trigger_handler = NULL;
1642 struct device *dev = &spi->dev;
1643 struct iio_dev *indio_dev;
1644 struct adis16480 *st;
1645 int ret;
1646
1647 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1648 if (indio_dev == NULL)
1649 return -ENOMEM;
1650
1651 st = iio_priv(indio_dev);
1652
1653 st->chip_info = &adis16480_chip_info[id->driver_data];
1654 indio_dev->name = spi_get_device_id(spi)->name;
1655 indio_dev->channels = st->chip_info->channels;
1656 indio_dev->num_channels = st->chip_info->num_channels;
1657 if (st->chip_info->has_burst_delta_data)
1658 indio_dev->available_scan_masks = adis16545_channel_masks;
1659 indio_dev->info = &adis16480_info;
1660 indio_dev->modes = INDIO_DIRECT_MODE;
1661
1662 adis16480_data = &st->chip_info->adis_data;
1663
1664 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
1665 if (ret)
1666 return ret;
1667
1668 ret = __adis_initial_startup(&st->adis);
1669 if (ret)
1670 return ret;
1671
1672 /*
1673 * By default, use burst id for gyroscope and accelerometer data.
1674 * This is the only option for devices which do not offer delta angle
1675 * and delta velocity burst readings.
1676 */
1677 st->burst_id = ADIS16495_GYRO_ACCEL_BURST_ID;
1678
1679 if (st->chip_info->has_sleep_cnt) {
1680 ret = devm_add_action_or_reset(dev, adis16480_stop, indio_dev);
1681 if (ret)
1682 return ret;
1683 }
1684
1685 ret = adis16480_config_irq_pin(st);
1686 if (ret)
1687 return ret;
1688
1689 ret = adis16480_get_ext_clocks(st);
1690 if (ret)
1691 return ret;
1692
1693 if (st->ext_clk) {
1694 ret = adis16480_ext_clk_config(st, true);
1695 if (ret)
1696 return ret;
1697
1698 ret = devm_add_action_or_reset(dev, adis16480_clk_disable, st->ext_clk);
1699 if (ret)
1700 return ret;
1701
1702 st->clk_freq = clk_get_rate(st->ext_clk);
1703 st->clk_freq *= 1000; /* micro */
1704 if (st->clk_mode == ADIS16480_CLK_PPS) {
1705 u16 sync_scale;
1706
1707 /*
1708 * In PPS mode, the IMU sample rate is the clk_freq * sync_scale. Hence,
1709 * default the IMU sample rate to the highest multiple of the input clock
1710 * lower than the IMU max sample rate. The internal sample rate is the
1711 * max...
1712 */
1713 sync_scale = st->chip_info->int_clk / st->clk_freq;
1714 ret = __adis_write_reg_16(&st->adis, ADIS16495_REG_SYNC_SCALE, sync_scale);
1715 if (ret)
1716 return ret;
1717 }
1718 } else {
1719 st->clk_freq = st->chip_info->int_clk;
1720 }
1721
1722 /* Only use our trigger handler if burst mode is supported */
1723 if (adis16480_data->burst_len)
1724 trigger_handler = adis16480_trigger_handler;
1725
1726 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1727 trigger_handler);
1728 if (ret)
1729 return ret;
1730
1731 ret = devm_iio_device_register(dev, indio_dev);
1732 if (ret)
1733 return ret;
1734
1735 adis16480_debugfs_init(indio_dev);
1736
1737 return 0;
1738 }
1739
1740 static const struct spi_device_id adis16480_ids[] = {
1741 { "adis16375", ADIS16375 },
1742 { "adis16480", ADIS16480 },
1743 { "adis16485", ADIS16485 },
1744 { "adis16488", ADIS16488 },
1745 { "adis16490", ADIS16490 },
1746 { "adis16495-1", ADIS16495_1 },
1747 { "adis16495-2", ADIS16495_2 },
1748 { "adis16495-3", ADIS16495_3 },
1749 { "adis16497-1", ADIS16497_1 },
1750 { "adis16497-2", ADIS16497_2 },
1751 { "adis16497-3", ADIS16497_3 },
1752 { "adis16545-1", ADIS16545_1 },
1753 { "adis16545-2", ADIS16545_2 },
1754 { "adis16545-3", ADIS16545_3 },
1755 { "adis16547-1", ADIS16547_1 },
1756 { "adis16547-2", ADIS16547_2 },
1757 { "adis16547-3", ADIS16547_3 },
1758 { }
1759 };
1760 MODULE_DEVICE_TABLE(spi, adis16480_ids);
1761
1762 static const struct of_device_id adis16480_of_match[] = {
1763 { .compatible = "adi,adis16375" },
1764 { .compatible = "adi,adis16480" },
1765 { .compatible = "adi,adis16485" },
1766 { .compatible = "adi,adis16488" },
1767 { .compatible = "adi,adis16490" },
1768 { .compatible = "adi,adis16495-1" },
1769 { .compatible = "adi,adis16495-2" },
1770 { .compatible = "adi,adis16495-3" },
1771 { .compatible = "adi,adis16497-1" },
1772 { .compatible = "adi,adis16497-2" },
1773 { .compatible = "adi,adis16497-3" },
1774 { .compatible = "adi,adis16545-1" },
1775 { .compatible = "adi,adis16545-2" },
1776 { .compatible = "adi,adis16545-3" },
1777 { .compatible = "adi,adis16547-1" },
1778 { .compatible = "adi,adis16547-2" },
1779 { .compatible = "adi,adis16547-3" },
1780 { },
1781 };
1782 MODULE_DEVICE_TABLE(of, adis16480_of_match);
1783
1784 static struct spi_driver adis16480_driver = {
1785 .driver = {
1786 .name = "adis16480",
1787 .of_match_table = adis16480_of_match,
1788 },
1789 .id_table = adis16480_ids,
1790 .probe = adis16480_probe,
1791 };
1792 module_spi_driver(adis16480_driver);
1793
1794 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1795 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1796 MODULE_LICENSE("GPL v2");
1797 MODULE_IMPORT_NS(IIO_ADISLIB);
Kernel DRM miscellaneous fixes and cross-tree changes