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printf: Remove unused 'bprintf'
[drm/drm-misc.git] / drivers / mmc / host / renesas_sdhi_core.c
blobf73b84bae0c4c7311a8728e8e4eb68a9530f0a14
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas SDHI
4 *
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
9 *
10 * Based on "Compaq ASIC3 support":
11 *
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
15 *
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
18 *
19 */
20
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/kernel.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/module.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/pinctrl/pinctrl-state.h>
31 #include <linux/platform_data/tmio.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_domain.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/reset.h>
36 #include <linux/sh_dma.h>
37 #include <linux/slab.h>
38
39 #include "renesas_sdhi.h"
40 #include "tmio_mmc.h"
41
42 #define CTL_HOST_MODE 0xe4
43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0)
44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
45 #define HOST_MODE_GEN3_WMODE BIT(0)
46 #define HOST_MODE_GEN3_BUSWIDTH BIT(8)
47
48 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE
49 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
50 #define HOST_MODE_GEN3_64BIT 0
51
52 #define SDHI_VER_GEN2_SDR50 0x490c
53 #define SDHI_VER_RZ_A1 0x820b
54 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
55 #define SDHI_VER_GEN2_SDR104 0xcb0d
56 #define SDHI_VER_GEN3_SD 0xcc10
57 #define SDHI_VER_GEN3_SDMMC 0xcd10
58
59 #define SDHI_GEN3_MMC0_ADDR 0xee140000
60
61 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
62 {
63 u32 val;
64
65 /*
66 * see also
67 * renesas_sdhi_of_data :: dma_buswidth
68 */
69 switch (sd_ctrl_read16(host, CTL_VERSION)) {
70 case SDHI_VER_GEN2_SDR50:
71 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
72 break;
73 case SDHI_VER_GEN2_SDR104:
74 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
75 break;
76 case SDHI_VER_GEN3_SD:
77 case SDHI_VER_GEN3_SDMMC:
78 if (width == 64)
79 val = HOST_MODE_GEN3_64BIT;
80 else if (width == 32)
81 val = HOST_MODE_GEN3_32BIT;
82 else
83 val = HOST_MODE_GEN3_16BIT;
84 break;
85 default:
86 /* nothing to do */
87 return;
88 }
89
90 sd_ctrl_write16(host, CTL_HOST_MODE, val);
91 }
92
93 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
94 {
95 struct mmc_host *mmc = host->mmc;
96 struct renesas_sdhi *priv = host_to_priv(host);
97 int ret;
98
99 ret = clk_prepare_enable(priv->clk_cd);
100 if (ret < 0)
101 return ret;
102
103 /*
104 * The clock driver may not know what maximum frequency
105 * actually works, so it should be set with the max-frequency
106 * property which will already have been read to f_max. If it
107 * was missing, assume the current frequency is the maximum.
108 */
109 if (!mmc->f_max)
110 mmc->f_max = clk_get_rate(priv->clk);
111
112 /*
113 * Minimum frequency is the minimum input clock frequency
114 * divided by our maximum divider.
115 */
116 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
117
118 /* enable 16bit data access on SDBUF as default */
119 renesas_sdhi_sdbuf_width(host, 16);
120
121 return 0;
122 }
123
124 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
125 unsigned int wanted_clock)
126 {
127 struct renesas_sdhi *priv = host_to_priv(host);
128 struct clk *ref_clk = priv->clk;
129 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
130 unsigned int new_clock, clkh_shift = 0;
131 unsigned int new_upper_limit;
132 int i;
133
134 /*
135 * We simply return the current rate if a) we are not on a R-Car Gen2+
136 * SoC (may work for others, but untested) or b) if the SCC needs its
137 * clock during tuning, so we don't change the external clock setup.
138 */
139 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
140 return clk_get_rate(priv->clk);
141
142 if (priv->clkh) {
143 /* HS400 with 4TAP needs different clock settings */
144 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
145 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400;
146 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2;
147 ref_clk = priv->clkh;
148 }
149
150 new_clock = wanted_clock << clkh_shift;
151
152 /*
153 * We want the bus clock to be as close as possible to, but no
154 * greater than, new_clock. As we can divide by 1 << i for
155 * any i in [0, 9] we want the input clock to be as close as
156 * possible, but no greater than, new_clock << i.
157 *
158 * Add an upper limit of 1/1024 rate higher to the clock rate to fix
159 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has
160 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request
161 * for 533.333333 MHz will selects a slower 400 MHz due to rounding
162 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)).
163 */
164 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
165 freq = clk_round_rate(ref_clk, new_clock << i);
166 new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10);
167 if (freq > new_upper_limit) {
168 /* Too fast; look for a slightly slower option */
169 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
170 if (freq > new_upper_limit)
171 continue;
172 }
173
174 diff = new_clock - (freq >> i);
175 if (diff <= diff_min) {
176 best_freq = freq;
177 diff_min = diff;
178 }
179 }
180
181 clk_set_rate(ref_clk, best_freq);
182
183 if (priv->clkh)
184 clk_set_rate(priv->clk, best_freq >> clkh_shift);
185
186 return clk_get_rate(priv->clk);
187 }
188
189 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
190 unsigned int new_clock)
191 {
192 unsigned int clk_margin;
193 u32 clk = 0, clock;
194
195 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
196 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
197
198 if (new_clock == 0) {
199 host->mmc->actual_clock = 0;
200 goto out;
201 }
202
203 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
204 clock = host->mmc->actual_clock / 512;
205
206 /*
207 * Add a margin of 1/1024 rate higher to the clock rate in order
208 * to avoid clk variable setting a value of 0 due to the margin
209 * provided for actual_clock in renesas_sdhi_clk_update().
210 */
211 clk_margin = new_clock >> 10;
212 for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1)
213 clock <<= 1;
214
215 /* 1/1 clock is option */
216 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
217 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
218 clk |= 0xff;
219 else
220 clk &= ~0xff;
221 }
222
223 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
224 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
225 usleep_range(10000, 11000);
226
227 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
228 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
229
230 out:
231 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
232 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
233 usleep_range(10000, 11000);
234 }
235
236 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
237 {
238 struct renesas_sdhi *priv = host_to_priv(host);
239
240 clk_disable_unprepare(priv->clk_cd);
241 }
242
243 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
244 {
245 struct tmio_mmc_host *host = mmc_priv(mmc);
246
247 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
248 TMIO_STAT_DAT0);
249 }
250
251 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
252 struct mmc_ios *ios)
253 {
254 struct tmio_mmc_host *host = mmc_priv(mmc);
255 struct renesas_sdhi *priv = host_to_priv(host);
256 struct pinctrl_state *pin_state;
257 int ret;
258
259 switch (ios->signal_voltage) {
260 case MMC_SIGNAL_VOLTAGE_330:
261 pin_state = priv->pins_default;
262 break;
263 case MMC_SIGNAL_VOLTAGE_180:
264 pin_state = priv->pins_uhs;
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 /*
271 * If anything is missing, assume signal voltage is fixed at
272 * 3.3V and succeed/fail accordingly.
273 */
274 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
275 return ios->signal_voltage ==
276 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
277
278 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
279 if (ret < 0)
280 return ret;
281
282 return pinctrl_select_state(priv->pinctrl, pin_state);
283 }
284
285 /* SCC registers */
286 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
287 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
288 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
289 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
290 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
291 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
292 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
293 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
294 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
295 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
296 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
297 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
298 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
299
300 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
301 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
302 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
303
304 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
305
306 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
307
308 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
309 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
310 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
311
312 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
313 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
314 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
315
316 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
317 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
318
319 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
320 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
321
322 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
323 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
324 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
325 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
326
327 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
328 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
329 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
330 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
331
332 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
333 struct renesas_sdhi *priv, int addr)
334 {
335 return readl(priv->scc_ctl + (addr << host->bus_shift));
336 }
337
338 static inline void sd_scc_write32(struct tmio_mmc_host *host,
339 struct renesas_sdhi *priv,
340 int addr, u32 val)
341 {
342 writel(val, priv->scc_ctl + (addr << host->bus_shift));
343 }
344
345 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
346 {
347 struct renesas_sdhi *priv;
348
349 priv = host_to_priv(host);
350
351 /* Initialize SCC */
352 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
353
354 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
355 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
356
357 /* set sampling clock selection range */
358 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
359 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
360 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
361
362 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
363 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
364 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
365
366 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
367 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
368 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
369
370 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
371
372 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
373 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
374
375 /* Read TAPNUM */
376 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
377 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
378 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
379 }
380
381 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
382 {
383 struct tmio_mmc_host *host = mmc_priv(mmc);
384 struct renesas_sdhi *priv = host_to_priv(host);
385 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
386 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
387
388 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
389 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
390
391 /* Set HS400 mode */
392 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
393 sd_ctrl_read16(host, CTL_SDIF_MODE));
394
395 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
396 priv->scc_tappos_hs400);
397
398 if (sdhi_has_quirk(priv, manual_tap_correction))
399 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
400 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
401 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
402
403 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
404 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
405 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
406 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
407
408 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
409 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
410 sd_scc_read32(host, priv,
411 SH_MOBILE_SDHI_SCC_DTCNTL));
412
413 /* Avoid bad TAP */
414 if (bad_taps & BIT(priv->tap_set)) {
415 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
416
417 if (bad_taps & BIT(new_tap))
418 new_tap = (priv->tap_set - 1) % priv->tap_num;
419
420 if (bad_taps & BIT(new_tap)) {
421 new_tap = priv->tap_set;
422 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
423 }
424
425 priv->tap_set = new_tap;
426 }
427
428 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
429 priv->tap_set / (use_4tap ? 2 : 1));
430
431 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
432 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
433 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
434
435 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
436 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
437
438 if (priv->adjust_hs400_calib_table)
439 priv->needs_adjust_hs400 = true;
440 }
441
442 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
443 {
444 struct tmio_mmc_host *host = mmc_priv(mmc);
445 struct renesas_sdhi *priv = host_to_priv(host);
446
447 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
448 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
449
450 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
451 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
452 sd_scc_read32(host, priv,
453 SH_MOBILE_SDHI_SCC_CKSEL));
454
455 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
456 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
457 sd_scc_read32(host, priv,
458 SH_MOBILE_SDHI_SCC_DTCNTL));
459
460 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
461 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
462 }
463
464 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
465 struct renesas_sdhi *priv, u32 addr)
466 {
467 /* read mode */
468 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
469 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
470 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
471
472 /* access start and stop */
473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
474 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
476
477 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
478 }
479
480 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
481 struct renesas_sdhi *priv, u32 addr, u32 val)
482 {
483 /* write mode */
484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
485 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
486 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
487
488 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
489
490 /* access start and stop */
491 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
492 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
493 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
494 }
495
496 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
497 {
498 struct renesas_sdhi *priv = host_to_priv(host);
499 u32 calib_code;
500
501 /* disable write protect */
502 sd_scc_tmpport_write32(host, priv, 0x00,
503 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
504 /* read calibration code and adjust */
505 calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
506 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
507
508 sd_scc_tmpport_write32(host, priv, 0x22,
509 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
510 priv->adjust_hs400_calib_table[calib_code]);
511
512 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
513 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
514
515 /* adjustment done, clear flag */
516 priv->needs_adjust_hs400 = false;
517 }
518
519 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
520 {
521 struct renesas_sdhi *priv = host_to_priv(host);
522
523 /* disable write protect */
524 sd_scc_tmpport_write32(host, priv, 0x00,
525 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
526 /* disable manual calibration */
527 sd_scc_tmpport_write32(host, priv, 0x22, 0);
528 /* clear offset value of TMPPORT3 */
529 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
530 }
531
532 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
533 struct renesas_sdhi *priv)
534 {
535 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
536 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
537
538 /* Reset HS400 mode */
539 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
540 sd_ctrl_read16(host, CTL_SDIF_MODE));
541
542 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
543
544 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
545 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
546 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
547 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
548
549 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps))
550 renesas_sdhi_adjust_hs400_mode_disable(host);
551
552 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
553 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
554 }
555
556 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
557 {
558 struct tmio_mmc_host *host = mmc_priv(mmc);
559
560 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
561 return 0;
562 }
563
564 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
565 {
566 renesas_sdhi_disable_scc(host->mmc);
567 renesas_sdhi_reset_hs400_mode(host, priv);
568 priv->needs_adjust_hs400 = false;
569
570 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
571 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
572 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
573 }
574
575 /* only populated for TMIO_MMC_MIN_RCAR2 */
576 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve)
577 {
578 struct renesas_sdhi *priv = host_to_priv(host);
579 int ret;
580 u16 val;
581
582 if (!preserve) {
583 if (priv->rstc) {
584 reset_control_reset(priv->rstc);
585 /* Unknown why but without polling reset status, it will hang */
586 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
587 false, priv->rstc);
588 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
589 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
590 priv->needs_adjust_hs400 = false;
591 renesas_sdhi_set_clock(host, host->clk_cache);
592
593 /* Ensure default value for this driver. */
594 renesas_sdhi_sdbuf_width(host, 16);
595 } else if (priv->scc_ctl) {
596 renesas_sdhi_scc_reset(host, priv);
597 }
598 }
599
600 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
601 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
602 val |= CARD_OPT_EXTOP;
603 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
604 }
605 }
606
607 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
608 {
609 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
610
611 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
612 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
613
614 }
615
616 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
617
618 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
619 {
620 struct renesas_sdhi *priv = host_to_priv(host);
621 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
622 unsigned int taps_size = priv->tap_num * 2, min_tap_row;
623 unsigned long *bitmap;
624
625 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
626
627 /*
628 * When tuning CMD19 is issued twice for each tap, merge the
629 * result requiring the tap to be good in both runs before
630 * considering it for tuning selection.
631 */
632 for (i = 0; i < taps_size; i++) {
633 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
634
635 if (!test_bit(i, priv->taps))
636 clear_bit(i + offset, priv->taps);
637
638 if (!test_bit(i, priv->smpcmp))
639 clear_bit(i + offset, priv->smpcmp);
640 }
641
642 /*
643 * If all TAP are OK, the sampling clock position is selected by
644 * identifying the change point of data.
645 */
646 if (bitmap_full(priv->taps, taps_size)) {
647 bitmap = priv->smpcmp;
648 min_tap_row = 1;
649 } else {
650 bitmap = priv->taps;
651 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
652 }
653
654 /*
655 * Find the longest consecutive run of successful probes. If that
656 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
657 * center index as the tap, otherwise bail out.
658 */
659 for_each_set_bitrange(rs, re, bitmap, taps_size) {
660 if (re - rs > tap_cnt) {
661 tap_end = re;
662 tap_start = rs;
663 tap_cnt = tap_end - tap_start;
664 }
665 }
666
667 if (tap_cnt >= min_tap_row)
668 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
669 else
670 return -EIO;
671
672 /* Set SCC */
673 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
674
675 /* Enable auto re-tuning */
676 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
677 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
678 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
679
680 return 0;
681 }
682
683 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
684 {
685 struct tmio_mmc_host *host = mmc_priv(mmc);
686 struct renesas_sdhi *priv = host_to_priv(host);
687 int i, ret;
688
689 priv->tap_num = renesas_sdhi_init_tuning(host);
690 if (!priv->tap_num)
691 return 0; /* Tuning is not supported */
692
693 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
694 dev_err(&host->pdev->dev,
695 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
696 return -EINVAL;
697 }
698
699 bitmap_zero(priv->taps, priv->tap_num * 2);
700 bitmap_zero(priv->smpcmp, priv->tap_num * 2);
701
702 /* Issue CMD19 twice for each tap */
703 for (i = 0; i < 2 * priv->tap_num; i++) {
704 int cmd_error = 0;
705
706 /* Set sampling clock position */
707 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
708
709 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
710 set_bit(i, priv->taps);
711
712 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
713 set_bit(i, priv->smpcmp);
714
715 if (cmd_error)
716 mmc_send_abort_tuning(mmc, opcode);
717 }
718
719 ret = renesas_sdhi_select_tuning(host);
720 if (ret < 0)
721 renesas_sdhi_scc_reset(host, priv);
722 return ret;
723 }
724
725 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
726 {
727 struct renesas_sdhi *priv = host_to_priv(host);
728 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
729 u32 val;
730
731 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
732 if (!val)
733 return false;
734
735 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
736
737 /* Change TAP position according to correction status */
738 if (sdhi_has_quirk(priv, manual_tap_correction) &&
739 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
740 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
741 /*
742 * With HS400, the DAT signal is based on DS, not CLK.
743 * Therefore, use only CMD status.
744 */
745 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
746 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
747 if (!smpcmp) {
748 return false; /* no error in CMD signal */
749 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
750 new_tap++;
751 error_tap--;
752 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
753 new_tap--;
754 error_tap++;
755 } else {
756 return true; /* need retune */
757 }
758
759 /*
760 * When new_tap is a bad tap, we cannot change. Then, we compare
761 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
762 * we can at least retune.
763 */
764 if (bad_taps & BIT(new_tap % priv->tap_num))
765 return test_bit(error_tap % priv->tap_num, priv->smpcmp);
766 } else {
767 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
768 return true; /* need retune */
769 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
770 new_tap++;
771 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
772 new_tap--;
773 else
774 return false;
775 }
776
777 priv->tap_set = (new_tap % priv->tap_num);
778 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
779 priv->tap_set / (use_4tap ? 2 : 1));
780
781 return false;
782 }
783
784 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
785 {
786 struct renesas_sdhi *priv = host_to_priv(host);
787
788 /* Check SCC error */
789 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
790 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
791 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
792 return true;
793 }
794
795 return false;
796 }
797
798 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
799 struct mmc_request *mrq)
800 {
801 struct renesas_sdhi *priv = host_to_priv(host);
802 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
803 bool ret = false;
804
805 /*
806 * Skip checking SCC errors when running on 4 taps in HS400 mode as
807 * any retuning would still result in the same 4 taps being used.
808 */
809 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
810 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
811 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
812 return false;
813
814 if (mmc_doing_tune(host->mmc))
815 return false;
816
817 if (((mrq->cmd->error == -ETIMEDOUT) ||
818 (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
819 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
820 (host->ops.get_cd && host->ops.get_cd(host->mmc))))
821 ret |= true;
822
823 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
824 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
825 ret |= renesas_sdhi_auto_correction(host);
826 else
827 ret |= renesas_sdhi_manual_correction(host, use_4tap);
828
829 return ret;
830 }
831
832 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
833 {
834 int timeout = 1000;
835 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
836 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
837
838 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
839 & bit) == wait_state)
840 udelay(1);
841
842 if (!timeout) {
843 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
844 return -EBUSY;
845 }
846
847 return 0;
848 }
849
850 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
851 {
852 u32 bit = TMIO_STAT_SCLKDIVEN;
853
854 switch (addr) {
855 case CTL_SD_CMD:
856 case CTL_STOP_INTERNAL_ACTION:
857 case CTL_XFER_BLK_COUNT:
858 case CTL_SD_XFER_LEN:
859 case CTL_SD_MEM_CARD_OPT:
860 case CTL_TRANSACTION_CTL:
861 case CTL_DMA_ENABLE:
862 case CTL_HOST_MODE:
863 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
864 bit = TMIO_STAT_CMD_BUSY;
865 fallthrough;
866 case CTL_SD_CARD_CLK_CTL:
867 return renesas_sdhi_wait_idle(host, bit);
868 }
869
870 return 0;
871 }
872
873 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
874 unsigned int direction, int blk_size)
875 {
876 /*
877 * In Renesas controllers, when performing a
878 * multiple block read of one or two blocks,
879 * depending on the timing with which the
880 * response register is read, the response
881 * value may not be read properly.
882 * Use single block read for this HW bug
883 */
884 if ((direction == MMC_DATA_READ) &&
885 blk_size == 2)
886 return 1;
887
888 return blk_size;
889 }
890
891 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
892 {
893 struct renesas_sdhi *priv = host_to_priv(host);
894
895 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
896 renesas_sdhi_adjust_hs400_mode_enable(host);
897 }
898 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
899 {
900 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
901 int width = (host->bus_shift == 2) ? 64 : 32;
902
903 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
904 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
905 }
906
907 int renesas_sdhi_probe(struct platform_device *pdev,
908 const struct tmio_mmc_dma_ops *dma_ops,
909 const struct renesas_sdhi_of_data *of_data,
910 const struct renesas_sdhi_quirks *quirks)
911 {
912 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
913 struct tmio_mmc_data *mmc_data;
914 struct renesas_sdhi_dma *dma_priv;
915 struct tmio_mmc_host *host;
916 struct renesas_sdhi *priv;
917 int num_irqs, irq, ret, i;
918 struct resource *res;
919 u16 ver;
920
921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 if (!res)
923 return -EINVAL;
924
925 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
926 GFP_KERNEL);
927 if (!priv)
928 return -ENOMEM;
929
930 priv->quirks = quirks;
931 mmc_data = &priv->mmc_data;
932 dma_priv = &priv->dma_priv;
933
934 priv->clk = devm_clk_get(&pdev->dev, NULL);
935 if (IS_ERR(priv->clk))
936 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock");
937
938 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
939 if (IS_ERR(priv->clkh))
940 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh");
941
942 /*
943 * Some controllers provide a 2nd clock just to run the internal card
944 * detection logic. Unfortunately, the existing driver architecture does
945 * not support a separation of clocks for runtime PM usage. When
946 * native hotplug is used, the tmio driver assumes that the core
947 * must continue to run for card detect to stay active, so we cannot
948 * disable it.
949 * Additionally, it is prohibited to supply a clock to the core but not
950 * to the card detect circuit. That leaves us with if separate clocks
951 * are presented, we must treat them both as virtually 1 clock.
952 */
953 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd");
954 if (IS_ERR(priv->clk_cd))
955 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock");
956
957 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
958 if (IS_ERR(priv->rstc))
959 return PTR_ERR(priv->rstc);
960
961 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
962 if (!IS_ERR(priv->pinctrl)) {
963 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
964 PINCTRL_STATE_DEFAULT);
965 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
966 "state_uhs");
967 }
968
969 host = tmio_mmc_host_alloc(pdev, mmc_data);
970 if (IS_ERR(host))
971 return PTR_ERR(host);
972
973 priv->host = host;
974
975 if (of_data) {
976 mmc_data->flags |= of_data->tmio_flags;
977 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
978 mmc_data->capabilities |= of_data->capabilities;
979 mmc_data->capabilities2 |= of_data->capabilities2;
980 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
981 mmc_data->max_blk_count = of_data->max_blk_count;
982 mmc_data->max_segs = of_data->max_segs;
983 dma_priv->dma_buswidth = of_data->dma_buswidth;
984 host->bus_shift = of_data->bus_shift;
985 /* Fallback for old DTs */
986 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK)
987 priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
988
989 }
990
991 host->write16_hook = renesas_sdhi_write16_hook;
992 host->clk_enable = renesas_sdhi_clk_enable;
993 host->clk_disable = renesas_sdhi_clk_disable;
994 host->set_clock = renesas_sdhi_set_clock;
995 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
996 host->dma_ops = dma_ops;
997
998 if (sdhi_has_quirk(priv, hs400_disabled))
999 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1000
1001 /* For some SoC, we disable internal WP. GPIO may override this */
1002 if (mmc_can_gpio_ro(host->mmc))
1003 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1004
1005 /* SDR speeds are only available on Gen2+ */
1006 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1007 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1008 host->ops.card_busy = renesas_sdhi_card_busy;
1009 host->ops.start_signal_voltage_switch =
1010 renesas_sdhi_start_signal_voltage_switch;
1011 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1012 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
1013 host->reset = renesas_sdhi_reset;
1014 } else {
1015 host->sdcard_irq_mask_all = TMIO_MASK_ALL;
1016 }
1017
1018 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1019 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1020 host->bus_shift = 1;
1021
1022 if (mmd)
1023 *mmc_data = *mmd;
1024
1025 dma_priv->filter = shdma_chan_filter;
1026 dma_priv->enable = renesas_sdhi_enable_dma;
1027
1028 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1029
1030 /*
1031 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1032 * bus width mode.
1033 */
1034 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1035
1036 /*
1037 * All SDHI blocks support SDIO IRQ signalling.
1038 */
1039 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1040
1041 /* All SDHI have CMD12 control bit */
1042 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1043
1044 /* All SDHI have SDIO status bits which must be 1 */
1045 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1046
1047 /* All SDHI support HW busy detection */
1048 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1049
1050 dev_pm_domain_start(&pdev->dev);
1051
1052 ret = renesas_sdhi_clk_enable(host);
1053 if (ret)
1054 goto efree;
1055
1056 ver = sd_ctrl_read16(host, CTL_VERSION);
1057 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1058 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1059 mmc_data->max_blk_count = U16_MAX;
1060
1061 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1062 if (ver == SDHI_VER_GEN2_SDR50)
1063 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1064
1065 if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) {
1066 host->fixup_request = renesas_sdhi_fixup_request;
1067 priv->adjust_hs400_calib_table = *(
1068 res->start == SDHI_GEN3_MMC0_ADDR ?
1069 quirks->hs400_calib_table :
1070 quirks->hs400_calib_table + 1);
1071 }
1072
1073 /* these have an EXTOP bit */
1074 if (ver >= SDHI_VER_GEN3_SD)
1075 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1076
1077 /* Check for SCC so we can reset it if needed */
1078 if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104)
1079 priv->scc_ctl = host->ctl + of_data->scc_offset;
1080
1081 /* Enable tuning iff we have an SCC and a supported mode */
1082 if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1083 host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) {
1084 const struct renesas_sdhi_scc *taps = of_data->taps;
1085 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
1086 bool hit = false;
1087
1088 for (i = 0; i < of_data->taps_num; i++) {
1089 if (taps[i].clk_rate == 0 ||
1090 taps[i].clk_rate == host->mmc->f_max) {
1091 priv->scc_tappos = taps->tap;
1092 priv->scc_tappos_hs400 = use_4tap ?
1093 taps->tap_hs400_4tap :
1094 taps->tap;
1095 hit = true;
1096 break;
1097 }
1098 }
1099
1100 if (!hit)
1101 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1102
1103 host->check_retune = renesas_sdhi_check_scc_error;
1104 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1105 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1106 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1107 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1108 }
1109
1110 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
1111
1112 num_irqs = platform_irq_count(pdev);
1113 if (num_irqs < 0) {
1114 ret = num_irqs;
1115 goto eirq;
1116 }
1117
1118 /* There must be at least one IRQ source */
1119 if (!num_irqs) {
1120 ret = -ENXIO;
1121 goto eirq;
1122 }
1123
1124 for (i = 0; i < num_irqs; i++) {
1125 irq = platform_get_irq(pdev, i);
1126 if (irq < 0) {
1127 ret = irq;
1128 goto eirq;
1129 }
1130
1131 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1132 dev_name(&pdev->dev), host);
1133 if (ret)
1134 goto eirq;
1135 }
1136
1137 ret = tmio_mmc_host_probe(host);
1138 if (ret < 0)
1139 goto edisclk;
1140
1141 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1142 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1143
1144 return ret;
1145
1146 eirq:
1147 tmio_mmc_host_remove(host);
1148 edisclk:
1149 renesas_sdhi_clk_disable(host);
1150 efree:
1151 tmio_mmc_host_free(host);
1152
1153 return ret;
1154 }
1155 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1156
1157 void renesas_sdhi_remove(struct platform_device *pdev)
1158 {
1159 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1160
1161 tmio_mmc_host_remove(host);
1162 renesas_sdhi_clk_disable(host);
1163 tmio_mmc_host_free(host);
1164 }
1165 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1166
1167 MODULE_DESCRIPTION("Renesas SDHI core driver");
1168 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes