1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
5 * Copyright (C) 2018 Synaptics Incorporated
7 * Author: Jisheng Zhang <jszhang@kernel.org>
10 #include <linux/acpi.h>
11 #include <linux/arm-smccc.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/sizes.h>
24 #include "sdhci-pltfm.h"
27 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
29 /* DWCMSHC specific Mode Select value */
30 #define DWCMSHC_CTRL_HS400 0x7
32 /* DWC IP vendor area 1 pointer */
33 #define DWCMSHC_P_VENDOR_AREA1 0xe8
34 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
35 /* Offset inside the vendor area 1 */
36 #define DWCMSHC_HOST_CTRL3 0x8
37 #define DWCMSHC_EMMC_CONTROL 0x2c
38 #define DWCMSHC_CARD_IS_EMMC BIT(0)
39 #define DWCMSHC_ENHANCED_STROBE BIT(8)
40 #define DWCMSHC_EMMC_ATCTRL 0x40
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
42 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */
43 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */
44 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */
45 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */
46 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */
47 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */
48 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */
49 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */
50 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
52 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
54 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
55 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
57 /* DWC IP vendor area 2 pointer */
58 #define DWCMSHC_P_VENDOR_AREA2 0xea
60 /* Sophgo CV18XX specific Registers */
61 #define CV18XX_SDHCI_MSHC_CTRL 0x00
62 #define CV18XX_EMMC_FUNC_EN BIT(0)
63 #define CV18XX_LATANCY_1T BIT(1)
64 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40
65 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)
66 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)
67 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1
68 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)
69 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)
70 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1
71 #define CV18XX_SDHCI_PHY_CONFIG 0x4c
72 #define CV18XX_PHY_TX_BPS BIT(0)
74 #define CV18XX_TUNE_MAX 128
75 #define CV18XX_TUNE_STEP 1
76 #define CV18XX_RETRY_TUNING_MAX 50
78 /* Rockchip specific Registers */
79 #define DWCMSHC_EMMC_DLL_CTRL 0x800
80 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
81 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
82 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
83 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
84 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
85 #define DWCMSHC_EMMC_DLL_START BIT(0)
86 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
87 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
88 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
89 #define DWCMSHC_EMMC_DLL_START_POINT 16
90 #define DWCMSHC_EMMC_DLL_INC 8
91 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
92 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
93 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
94 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
95 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
96 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
97 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
98 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
99 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
100 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
101 #define DLL_RXCLK_NO_INVERTER 1
102 #define DLL_RXCLK_INVERTER 0
103 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
104 #define DLL_RXCLK_ORI_GATE BIT(31)
105 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
106 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
107 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
109 #define DLL_LOCK_WO_TMOUT(x) \
110 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
111 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
113 /* PHY register area pointer */
114 #define DWC_MSHC_PTR_PHY_R 0x300
116 /* PHY general configuration */
117 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)
118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
119 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */
120 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */
121 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */
122 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */
123 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */
124 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */
125 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */
127 /* PHY command/response pad settings */
128 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)
130 /* PHY data pad settings */
131 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)
133 /* PHY clock pad settings */
134 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)
136 /* PHY strobe pad settings */
137 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)
139 /* PHY reset pad settings */
140 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)
142 /* Bitfields are common for all pad settings */
143 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */
144 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */
146 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */
147 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */
148 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */
150 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */
151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
152 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */
153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
154 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
156 /* PHY CLK delay line settings */
157 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)
158 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0)
159 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */
161 /* PHY CLK delay line delay code */
162 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)
163 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */
164 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */
165 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */
167 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20)
168 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1)
170 /* PHY drift_cclk_rx delay line configuration setting */
171 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)
172 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */
173 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */
174 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */
176 /* PHY DLL control settings */
177 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)
178 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
179 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
181 /* PHY DLL configuration register 1 */
182 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)
183 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */
184 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
185 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
187 /* PHY DLL configuration register 2 */
188 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)
189 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
191 /* PHY DLL master and slave delay line configuration settings */
192 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)
193 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */
194 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */
196 #define FLAG_IO_FIXED_1V8 BIT(0)
198 #define BOUNDARY_OK(addr, len) \
199 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
201 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
202 SDHCI_TRNS_BLK_CNT_EN | \
205 /* SMC call for BlueField-3 eMMC RST_N */
206 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007
208 enum dwcmshc_rk_type
{
214 struct reset_control
*reset
;
215 enum dwcmshc_rk_type devtype
;
219 #define DWCMSHC_MAX_OTHER_CLKS 3
221 struct dwcmshc_priv
{
223 int vendor_specific_area1
; /* P_VENDOR_SPECIFIC_AREA1 reg */
224 int vendor_specific_area2
; /* P_VENDOR_SPECIFIC_AREA2 reg */
227 struct clk_bulk_data other_clks
[DWCMSHC_MAX_OTHER_CLKS
];
229 void *priv
; /* pointer to SoC private stuff */
234 struct dwcmshc_pltfm_data
{
235 const struct sdhci_pltfm_data pdata
;
236 int (*init
)(struct device
*dev
, struct sdhci_host
*host
, struct dwcmshc_priv
*dwc_priv
);
237 void (*postinit
)(struct sdhci_host
*host
, struct dwcmshc_priv
*dwc_priv
);
240 static int dwcmshc_get_enable_other_clks(struct device
*dev
,
241 struct dwcmshc_priv
*priv
,
243 const char * const clk_ids
[])
247 if (num_clks
> DWCMSHC_MAX_OTHER_CLKS
)
250 for (int i
= 0; i
< num_clks
; i
++)
251 priv
->other_clks
[i
].id
= clk_ids
[i
];
253 err
= devm_clk_bulk_get_optional(dev
, num_clks
, priv
->other_clks
);
255 dev_err(dev
, "failed to get clocks %d\n", err
);
259 err
= clk_bulk_prepare_enable(num_clks
, priv
->other_clks
);
261 dev_err(dev
, "failed to enable clocks %d\n", err
);
263 priv
->num_other_clks
= num_clks
;
269 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
270 * so that each DMA transfer doesn't exceed the boundary.
272 static void dwcmshc_adma_write_desc(struct sdhci_host
*host
, void **desc
,
273 dma_addr_t addr
, int len
, unsigned int cmd
)
277 if (likely(!len
|| BOUNDARY_OK(addr
, len
))) {
278 sdhci_adma_write_desc(host
, desc
, addr
, len
, cmd
);
282 offset
= addr
& (SZ_128M
- 1);
283 tmplen
= SZ_128M
- offset
;
284 sdhci_adma_write_desc(host
, desc
, addr
, tmplen
, cmd
);
288 sdhci_adma_write_desc(host
, desc
, addr
, len
, cmd
);
291 static unsigned int dwcmshc_get_max_clock(struct sdhci_host
*host
)
293 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
296 return sdhci_pltfm_clk_get_max_clock(host
);
298 return pltfm_host
->clock
;
301 static unsigned int rk35xx_get_max_clock(struct sdhci_host
*host
)
303 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
305 return clk_round_rate(pltfm_host
->clk
, ULONG_MAX
);
308 static void dwcmshc_check_auto_cmd23(struct mmc_host
*mmc
,
309 struct mmc_request
*mrq
)
311 struct sdhci_host
*host
= mmc_priv(mmc
);
314 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
315 * block count register which doesn't support stuff bits of
316 * CMD23 argument on dwcmsch host controller.
318 if (mrq
->sbc
&& (mrq
->sbc
->arg
& SDHCI_DWCMSHC_ARG2_STUFF
))
319 host
->flags
&= ~SDHCI_AUTO_CMD23
;
321 host
->flags
|= SDHCI_AUTO_CMD23
;
324 static void dwcmshc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
326 dwcmshc_check_auto_cmd23(mmc
, mrq
);
328 sdhci_request(mmc
, mrq
);
331 static void dwcmshc_phy_1_8v_init(struct sdhci_host
*host
)
333 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
334 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
337 /* deassert phy reset & set tx drive strength */
338 val
= PHY_CNFG_RSTN_DEASSERT
;
339 val
|= FIELD_PREP(PHY_CNFG_PAD_SP_MASK
, PHY_CNFG_PAD_SP
);
340 val
|= FIELD_PREP(PHY_CNFG_PAD_SN_MASK
, PHY_CNFG_PAD_SN
);
341 sdhci_writel(host
, val
, PHY_CNFG_R
);
343 /* disable delay line */
344 sdhci_writeb(host
, PHY_SDCLKDL_CNFG_UPDATE
, PHY_SDCLKDL_CNFG_R
);
347 sdhci_writeb(host
, priv
->delay_line
, PHY_SDCLKDL_DC_R
);
348 sdhci_writeb(host
, PHY_DLL_CNFG2_JUMPSTEP
, PHY_DLL_CNFG2_R
);
350 /* enable delay lane */
351 val
= sdhci_readb(host
, PHY_SDCLKDL_CNFG_R
);
352 val
&= ~(PHY_SDCLKDL_CNFG_UPDATE
);
353 sdhci_writeb(host
, val
, PHY_SDCLKDL_CNFG_R
);
355 /* configure phy pads */
356 val
= PHY_PAD_RXSEL_1V8
;
357 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLUP
);
358 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
359 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
360 sdhci_writew(host
, val
, PHY_CMDPAD_CNFG_R
);
361 sdhci_writew(host
, val
, PHY_DATAPAD_CNFG_R
);
362 sdhci_writew(host
, val
, PHY_RSTNPAD_CNFG_R
);
364 val
= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
365 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
366 sdhci_writew(host
, val
, PHY_CLKPAD_CNFG_R
);
368 val
= PHY_PAD_RXSEL_1V8
;
369 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLDOWN
);
370 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
371 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
372 sdhci_writew(host
, val
, PHY_STBPAD_CNFG_R
);
374 /* enable data strobe mode */
375 sdhci_writeb(host
, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK
, PHY_DLLDL_CNFG_SLV_INPSEL
),
379 sdhci_writeb(host
, PHY_DLL_CTRL_ENABLE
, PHY_DLL_CTRL_R
);
382 static void dwcmshc_phy_3_3v_init(struct sdhci_host
*host
)
384 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
385 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
388 /* deassert phy reset & set tx drive strength */
389 val
= PHY_CNFG_RSTN_DEASSERT
;
390 val
|= FIELD_PREP(PHY_CNFG_PAD_SP_MASK
, PHY_CNFG_PAD_SP
);
391 val
|= FIELD_PREP(PHY_CNFG_PAD_SN_MASK
, PHY_CNFG_PAD_SN
);
392 sdhci_writel(host
, val
, PHY_CNFG_R
);
394 /* disable delay line */
395 sdhci_writeb(host
, PHY_SDCLKDL_CNFG_UPDATE
, PHY_SDCLKDL_CNFG_R
);
398 sdhci_writeb(host
, priv
->delay_line
, PHY_SDCLKDL_DC_R
);
399 sdhci_writeb(host
, PHY_DLL_CNFG2_JUMPSTEP
, PHY_DLL_CNFG2_R
);
401 /* enable delay lane */
402 val
= sdhci_readb(host
, PHY_SDCLKDL_CNFG_R
);
403 val
&= ~(PHY_SDCLKDL_CNFG_UPDATE
);
404 sdhci_writeb(host
, val
, PHY_SDCLKDL_CNFG_R
);
406 /* configure phy pads */
407 val
= PHY_PAD_RXSEL_3V3
;
408 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLUP
);
409 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
410 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
411 sdhci_writew(host
, val
, PHY_CMDPAD_CNFG_R
);
412 sdhci_writew(host
, val
, PHY_DATAPAD_CNFG_R
);
413 sdhci_writew(host
, val
, PHY_RSTNPAD_CNFG_R
);
415 val
= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
416 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
417 sdhci_writew(host
, val
, PHY_CLKPAD_CNFG_R
);
419 val
= PHY_PAD_RXSEL_3V3
;
420 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLDOWN
);
421 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
422 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N
);
423 sdhci_writew(host
, val
, PHY_STBPAD_CNFG_R
);
426 sdhci_writeb(host
, PHY_DLL_CTRL_ENABLE
, PHY_DLL_CTRL_R
);
429 static void th1520_sdhci_set_phy(struct sdhci_host
*host
)
431 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
432 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
433 u32 emmc_caps
= MMC_CAP2_NO_SD
| MMC_CAP2_NO_SDIO
;
436 /* Before power on, set PHY configs */
437 if (priv
->flags
& FLAG_IO_FIXED_1V8
)
438 dwcmshc_phy_1_8v_init(host
);
440 dwcmshc_phy_3_3v_init(host
);
442 if ((host
->mmc
->caps2
& emmc_caps
) == emmc_caps
) {
443 emmc_ctrl
= sdhci_readw(host
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_CONTROL
);
444 emmc_ctrl
|= DWCMSHC_CARD_IS_EMMC
;
445 sdhci_writew(host
, emmc_ctrl
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_CONTROL
);
448 sdhci_writeb(host
, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK
, PHY_DLL_CNFG1_SLVDLY
) |
449 PHY_DLL_CNFG1_WAITCYCLE
, PHY_DLL_CNFG1_R
);
452 static void dwcmshc_set_uhs_signaling(struct sdhci_host
*host
,
455 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
456 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
459 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
460 /* Select Bus Speed Mode for host */
461 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
462 if ((timing
== MMC_TIMING_MMC_HS200
) ||
463 (timing
== MMC_TIMING_UHS_SDR104
))
464 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
465 else if (timing
== MMC_TIMING_UHS_SDR12
)
466 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
467 else if ((timing
== MMC_TIMING_UHS_SDR25
) ||
468 (timing
== MMC_TIMING_MMC_HS
))
469 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
470 else if (timing
== MMC_TIMING_UHS_SDR50
)
471 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
472 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
473 (timing
== MMC_TIMING_MMC_DDR52
))
474 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
475 else if (timing
== MMC_TIMING_MMC_HS400
) {
476 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
477 ctrl
= sdhci_readw(host
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_CONTROL
);
478 ctrl
|= DWCMSHC_CARD_IS_EMMC
;
479 sdhci_writew(host
, ctrl
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_CONTROL
);
481 ctrl_2
|= DWCMSHC_CTRL_HS400
;
484 if (priv
->flags
& FLAG_IO_FIXED_1V8
)
485 ctrl_2
|= SDHCI_CTRL_VDD_180
;
486 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
489 static void th1520_set_uhs_signaling(struct sdhci_host
*host
,
492 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
493 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
495 dwcmshc_set_uhs_signaling(host
, timing
);
496 if (timing
== MMC_TIMING_MMC_HS400
)
497 priv
->delay_line
= PHY_SDCLKDL_DC_HS400
;
499 sdhci_writeb(host
, 0, PHY_DLLDL_CNFG_R
);
500 th1520_sdhci_set_phy(host
);
503 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host
*mmc
,
507 struct sdhci_host
*host
= mmc_priv(mmc
);
508 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
509 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
510 int reg
= priv
->vendor_specific_area1
+ DWCMSHC_EMMC_CONTROL
;
512 vendor
= sdhci_readl(host
, reg
);
513 if (ios
->enhanced_strobe
)
514 vendor
|= DWCMSHC_ENHANCED_STROBE
;
516 vendor
&= ~DWCMSHC_ENHANCED_STROBE
;
518 sdhci_writel(host
, vendor
, reg
);
521 static int dwcmshc_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
523 int err
= sdhci_execute_tuning(mmc
, opcode
);
524 struct sdhci_host
*host
= mmc_priv(mmc
);
530 * Tuning can leave the IP in an active state (Buffer Read Enable bit
531 * set) which prevents the entry to low power states (i.e. S0i3). Data
532 * reset will clear it.
534 sdhci_reset(host
, SDHCI_RESET_DATA
);
539 static u32
dwcmshc_cqe_irq_handler(struct sdhci_host
*host
, u32 intmask
)
544 if (!sdhci_cqe_irq(host
, intmask
, &cmd_error
, &data_error
))
547 cqhci_irq(host
->mmc
, intmask
, cmd_error
, data_error
);
552 static void dwcmshc_sdhci_cqe_enable(struct mmc_host
*mmc
)
554 struct sdhci_host
*host
= mmc_priv(mmc
);
557 sdhci_writew(host
, DWCMSHC_SDHCI_CQE_TRNS_MODE
, SDHCI_TRANSFER_MODE
);
559 sdhci_cqe_enable(mmc
);
562 * The "DesignWare Cores Mobile Storage Host Controller
563 * DWC_mshc / DWC_mshc_lite Databook" says:
564 * when Host Version 4 Enable" is 1 in Host Control 2 register,
565 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected.
566 * Selection of 32-bit/64-bit System Addressing:
567 * either 32-bit or 64-bit system addressing is selected by
568 * 64-bit Addressing bit in Host Control 2 register.
570 * On the other hand the "DesignWare Cores Mobile Storage Host
571 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to
572 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register.
574 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
575 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
576 ctrl
|= SDHCI_CTRL_ADMA32
;
577 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
580 static void dwcmshc_set_tran_desc(struct cqhci_host
*cq_host
, u8
**desc
,
581 dma_addr_t addr
, int len
, bool end
, bool dma64
)
585 if (likely(!len
|| BOUNDARY_OK(addr
, len
))) {
586 cqhci_set_tran_desc(*desc
, addr
, len
, end
, dma64
);
590 offset
= addr
& (SZ_128M
- 1);
591 tmplen
= SZ_128M
- offset
;
592 cqhci_set_tran_desc(*desc
, addr
, tmplen
, false, dma64
);
596 *desc
+= cq_host
->trans_desc_len
;
597 cqhci_set_tran_desc(*desc
, addr
, len
, end
, dma64
);
600 static void dwcmshc_cqhci_dumpregs(struct mmc_host
*mmc
)
602 sdhci_dumpregs(mmc_priv(mmc
));
605 static void dwcmshc_rk3568_set_clock(struct sdhci_host
*host
, unsigned int clock
)
607 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
608 struct dwcmshc_priv
*dwc_priv
= sdhci_pltfm_priv(pltfm_host
);
609 struct rk35xx_priv
*priv
= dwc_priv
->priv
;
610 u8 txclk_tapnum
= DLL_TXCLK_TAPNUM_DEFAULT
;
614 host
->mmc
->actual_clock
= 0;
617 /* Disable interface clock at initial state. */
618 sdhci_set_clock(host
, clock
);
622 /* Rockchip platform only support 375KHz for identify mode */
626 err
= clk_set_rate(pltfm_host
->clk
, clock
);
628 dev_err(mmc_dev(host
->mmc
), "fail to set clock %d", clock
);
630 sdhci_set_clock(host
, clock
);
632 /* Disable cmd conflict check */
633 reg
= dwc_priv
->vendor_specific_area1
+ DWCMSHC_HOST_CTRL3
;
634 extra
= sdhci_readl(host
, reg
);
636 sdhci_writel(host
, extra
, reg
);
638 if (clock
<= 52000000) {
640 * Disable DLL and reset both of sample and drive clock.
641 * The bypass bit and start bit need to be set if DLL is not locked.
643 sdhci_writel(host
, DWCMSHC_EMMC_DLL_BYPASS
| DWCMSHC_EMMC_DLL_START
, DWCMSHC_EMMC_DLL_CTRL
);
644 sdhci_writel(host
, DLL_RXCLK_ORI_GATE
, DWCMSHC_EMMC_DLL_RXCLK
);
645 sdhci_writel(host
, 0, DWCMSHC_EMMC_DLL_TXCLK
);
646 sdhci_writel(host
, 0, DECMSHC_EMMC_DLL_CMDOUT
);
648 * Before switching to hs400es mode, the driver will enable
649 * enhanced strobe first. PHY needs to configure the parameters
650 * of enhanced strobe first.
652 extra
= DWCMSHC_EMMC_DLL_DLYENA
|
653 DLL_STRBIN_DELAY_NUM_SEL
|
654 DLL_STRBIN_DELAY_NUM_DEFAULT
<< DLL_STRBIN_DELAY_NUM_OFFSET
;
655 sdhci_writel(host
, extra
, DWCMSHC_EMMC_DLL_STRBIN
);
660 sdhci_writel(host
, BIT(1), DWCMSHC_EMMC_DLL_CTRL
);
662 sdhci_writel(host
, 0x0, DWCMSHC_EMMC_DLL_CTRL
);
665 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
666 * we must set it in higher speed mode.
668 extra
= DWCMSHC_EMMC_DLL_DLYENA
;
669 if (priv
->devtype
== DWCMSHC_RK3568
)
670 extra
|= DLL_RXCLK_NO_INVERTER
<< DWCMSHC_EMMC_DLL_RXCLK_SRCSEL
;
671 sdhci_writel(host
, extra
, DWCMSHC_EMMC_DLL_RXCLK
);
673 /* Init DLL settings */
674 extra
= 0x5 << DWCMSHC_EMMC_DLL_START_POINT
|
675 0x2 << DWCMSHC_EMMC_DLL_INC
|
676 DWCMSHC_EMMC_DLL_START
;
677 sdhci_writel(host
, extra
, DWCMSHC_EMMC_DLL_CTRL
);
678 err
= readl_poll_timeout(host
->ioaddr
+ DWCMSHC_EMMC_DLL_STATUS0
,
679 extra
, DLL_LOCK_WO_TMOUT(extra
), 1,
680 500 * USEC_PER_MSEC
);
682 dev_err(mmc_dev(host
->mmc
), "DLL lock timeout!\n");
686 extra
= 0x1 << 16 | /* tune clock stop en */
687 0x3 << 17 | /* pre-change delay */
688 0x3 << 19; /* post-change delay */
689 sdhci_writel(host
, extra
, dwc_priv
->vendor_specific_area1
+ DWCMSHC_EMMC_ATCTRL
);
691 if (host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS200
||
692 host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
)
693 txclk_tapnum
= priv
->txclk_tapnum
;
695 if ((priv
->devtype
== DWCMSHC_RK3588
) && host
->mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
) {
696 txclk_tapnum
= DLL_TXCLK_TAPNUM_90_DEGREES
;
698 extra
= DLL_CMDOUT_SRC_CLK_NEG
|
699 DLL_CMDOUT_EN_SRC_CLK_NEG
|
700 DWCMSHC_EMMC_DLL_DLYENA
|
701 DLL_CMDOUT_TAPNUM_90_DEGREES
|
702 DLL_CMDOUT_TAPNUM_FROM_SW
;
703 sdhci_writel(host
, extra
, DECMSHC_EMMC_DLL_CMDOUT
);
706 extra
= DWCMSHC_EMMC_DLL_DLYENA
|
707 DLL_TXCLK_TAPNUM_FROM_SW
|
708 DLL_RXCLK_NO_INVERTER
<< DWCMSHC_EMMC_DLL_RXCLK_SRCSEL
|
710 sdhci_writel(host
, extra
, DWCMSHC_EMMC_DLL_TXCLK
);
712 extra
= DWCMSHC_EMMC_DLL_DLYENA
|
713 DLL_STRBIN_TAPNUM_DEFAULT
|
714 DLL_STRBIN_TAPNUM_FROM_SW
;
715 sdhci_writel(host
, extra
, DWCMSHC_EMMC_DLL_STRBIN
);
718 static void rk35xx_sdhci_reset(struct sdhci_host
*host
, u8 mask
)
720 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
721 struct dwcmshc_priv
*dwc_priv
= sdhci_pltfm_priv(pltfm_host
);
722 struct rk35xx_priv
*priv
= dwc_priv
->priv
;
724 if (mask
& SDHCI_RESET_ALL
&& priv
->reset
) {
725 reset_control_assert(priv
->reset
);
727 reset_control_deassert(priv
->reset
);
730 sdhci_reset(host
, mask
);
733 static int dwcmshc_rk35xx_init(struct device
*dev
, struct sdhci_host
*host
,
734 struct dwcmshc_priv
*dwc_priv
)
736 static const char * const clk_ids
[] = {"axi", "block", "timer"};
737 struct rk35xx_priv
*priv
;
740 priv
= devm_kzalloc(dev
, sizeof(struct rk35xx_priv
), GFP_KERNEL
);
744 if (of_device_is_compatible(dev
->of_node
, "rockchip,rk3588-dwcmshc"))
745 priv
->devtype
= DWCMSHC_RK3588
;
747 priv
->devtype
= DWCMSHC_RK3568
;
749 priv
->reset
= devm_reset_control_array_get_optional_exclusive(mmc_dev(host
->mmc
));
750 if (IS_ERR(priv
->reset
)) {
751 err
= PTR_ERR(priv
->reset
);
752 dev_err(mmc_dev(host
->mmc
), "failed to get reset control %d\n", err
);
756 err
= dwcmshc_get_enable_other_clks(mmc_dev(host
->mmc
), dwc_priv
,
757 ARRAY_SIZE(clk_ids
), clk_ids
);
761 if (of_property_read_u8(mmc_dev(host
->mmc
)->of_node
, "rockchip,txclk-tapnum",
762 &priv
->txclk_tapnum
))
763 priv
->txclk_tapnum
= DLL_TXCLK_TAPNUM_DEFAULT
;
765 /* Disable cmd conflict check */
766 sdhci_writel(host
, 0x0, dwc_priv
->vendor_specific_area1
+ DWCMSHC_HOST_CTRL3
);
767 /* Reset previous settings */
768 sdhci_writel(host
, 0, DWCMSHC_EMMC_DLL_TXCLK
);
769 sdhci_writel(host
, 0, DWCMSHC_EMMC_DLL_STRBIN
);
771 dwc_priv
->priv
= priv
;
776 static void dwcmshc_rk35xx_postinit(struct sdhci_host
*host
, struct dwcmshc_priv
*dwc_priv
)
779 * Don't support highspeed bus mode with low clk speed as we
780 * cannot use DLL for this condition.
782 if (host
->mmc
->f_max
<= 52000000) {
783 dev_info(mmc_dev(host
->mmc
), "Disabling HS200/HS400, frequency too low (%d)\n",
785 host
->mmc
->caps2
&= ~(MMC_CAP2_HS200
| MMC_CAP2_HS400
);
786 host
->mmc
->caps
&= ~(MMC_CAP_3_3V_DDR
| MMC_CAP_1_8V_DDR
);
790 static int th1520_execute_tuning(struct sdhci_host
*host
, u32 opcode
)
792 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
793 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
796 if (host
->flags
& SDHCI_HS400_TUNING
)
799 sdhci_writeb(host
, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK
, PHY_ATDL_CNFG_INPSEL
),
801 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_ATCTRL
);
804 * configure tuning settings:
805 * - center phase select code driven in block gap interval
806 * - disable reporting of framing errors
807 * - disable software managed tuning
808 * - disable user selection of sampling window edges,
809 * instead tuning calculated edges are used
811 val
&= ~(AT_CTRL_CI_SEL
| AT_CTRL_RPT_TUNE_ERR
| AT_CTRL_SW_TUNE_EN
|
812 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK
, AT_CTRL_WIN_EDGE_SEL
));
815 * configure tuning settings:
816 * - enable auto-tuning
817 * - enable sampling window threshold
818 * - stop clocks during phase code change
819 * - set max latency in cycles between tx and rx clocks
820 * - set max latency in cycles to switch output phase
821 * - set max sampling window threshold value
823 val
|= AT_CTRL_AT_EN
| AT_CTRL_SWIN_TH_EN
| AT_CTRL_TUNE_CLK_STOP_EN
;
824 val
|= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK
, AT_CTRL_PRE_CHANGE_DLY
);
825 val
|= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK
, AT_CTRL_POST_CHANGE_DLY
);
826 val
|= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK
, AT_CTRL_SWIN_TH_VAL
);
828 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_ATCTRL
);
829 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_ATCTRL
);
832 sdhci_start_tuning(host
);
833 host
->tuning_loop_count
= 128;
834 host
->tuning_err
= __sdhci_execute_tuning(host
, opcode
);
835 if (host
->tuning_err
) {
836 /* disable auto-tuning upon tuning error */
837 val
&= ~AT_CTRL_AT_EN
;
838 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ DWCMSHC_EMMC_ATCTRL
);
839 dev_err(mmc_dev(host
->mmc
), "tuning failed: %d\n", host
->tuning_err
);
842 sdhci_end_tuning(host
);
847 static void th1520_sdhci_reset(struct sdhci_host
*host
, u8 mask
)
849 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
850 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
853 sdhci_reset(host
, mask
);
855 /* The T-Head 1520 SoC does not comply with the SDHCI specification
856 * regarding the "Software Reset for CMD line should clear 'Command
857 * Complete' in the Normal Interrupt Status Register." Clear the bit
858 * here to compensate for this quirk.
860 if (mask
& SDHCI_RESET_CMD
)
861 sdhci_writel(host
, SDHCI_INT_RESPONSE
, SDHCI_INT_STATUS
);
863 if (priv
->flags
& FLAG_IO_FIXED_1V8
) {
864 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
865 if (!(ctrl_2
& SDHCI_CTRL_VDD_180
)) {
866 ctrl_2
|= SDHCI_CTRL_VDD_180
;
867 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
872 static int th1520_init(struct device
*dev
,
873 struct sdhci_host
*host
,
874 struct dwcmshc_priv
*dwc_priv
)
876 dwc_priv
->delay_line
= PHY_SDCLKDL_DC_DEFAULT
;
878 if (device_property_read_bool(dev
, "mmc-ddr-1_8v") ||
879 device_property_read_bool(dev
, "mmc-hs200-1_8v") ||
880 device_property_read_bool(dev
, "mmc-hs400-1_8v"))
881 dwc_priv
->flags
|= FLAG_IO_FIXED_1V8
;
883 dwc_priv
->flags
&= ~FLAG_IO_FIXED_1V8
;
886 * start_signal_voltage_switch() will try 3.3V first
887 * then 1.8V. Use SDHCI_SIGNALING_180 rather than
888 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V
889 * in sdhci_start_signal_voltage_switch().
891 if (dwc_priv
->flags
& FLAG_IO_FIXED_1V8
) {
892 host
->flags
&= ~SDHCI_SIGNALING_330
;
893 host
->flags
|= SDHCI_SIGNALING_180
;
896 sdhci_enable_v4_mode(host
);
901 static void cv18xx_sdhci_reset(struct sdhci_host
*host
, u8 mask
)
903 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
904 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
905 u32 val
, emmc_caps
= MMC_CAP2_NO_SD
| MMC_CAP2_NO_SDIO
;
907 sdhci_reset(host
, mask
);
909 if ((host
->mmc
->caps2
& emmc_caps
) == emmc_caps
) {
910 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
911 val
|= CV18XX_EMMC_FUNC_EN
;
912 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
915 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
916 val
|= CV18XX_LATANCY_1T
;
917 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
919 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_PHY_CONFIG
);
920 val
|= CV18XX_PHY_TX_BPS
;
921 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_PHY_CONFIG
);
923 val
= (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK
, 0) |
924 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK
, CV18XX_PHY_TX_SRC_INVERT_CLK_TX
) |
925 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK
, 0) |
926 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK
, CV18XX_PHY_RX_SRC_INVERT_RX_CLK
));
927 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_PHY_TX_RX_DLY
);
930 static void cv18xx_sdhci_set_tap(struct sdhci_host
*host
, int tap
)
932 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
933 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
937 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
938 clk
&= ~SDHCI_CLOCK_CARD_EN
;
939 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
941 val
= sdhci_readl(host
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
942 val
&= ~CV18XX_LATANCY_1T
;
943 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_MSHC_CTRL
);
945 val
= (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK
, 0) |
946 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK
, CV18XX_PHY_TX_SRC_INVERT_CLK_TX
) |
947 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK
, tap
));
948 sdhci_writel(host
, val
, priv
->vendor_specific_area1
+ CV18XX_SDHCI_PHY_TX_RX_DLY
);
950 sdhci_writel(host
, 0, priv
->vendor_specific_area1
+ CV18XX_SDHCI_PHY_CONFIG
);
952 clk
|= SDHCI_CLOCK_CARD_EN
;
953 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
954 usleep_range(1000, 2000);
957 static int cv18xx_retry_tuning(struct mmc_host
*mmc
, u32 opcode
, int *cmd_error
)
961 while (retry
< CV18XX_RETRY_TUNING_MAX
) {
962 ret
= mmc_send_tuning(mmc
, opcode
, NULL
);
971 static void cv18xx_sdhci_post_tuning(struct sdhci_host
*host
)
975 val
= sdhci_readl(host
, SDHCI_INT_STATUS
);
976 val
|= SDHCI_INT_DATA_AVAIL
;
977 sdhci_writel(host
, val
, SDHCI_INT_STATUS
);
979 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
982 static int cv18xx_sdhci_execute_tuning(struct sdhci_host
*host
, u32 opcode
)
984 int min
, max
, avg
, ret
;
985 int win_length
, target_min
, target_max
, target_win_length
;
988 target_win_length
= 0;
990 sdhci_reset_tuning(host
);
992 while (max
< CV18XX_TUNE_MAX
) {
993 /* find the mininum delay first which can pass tuning */
994 while (min
< CV18XX_TUNE_MAX
) {
995 cv18xx_sdhci_set_tap(host
, min
);
996 if (!cv18xx_retry_tuning(host
->mmc
, opcode
, NULL
))
998 min
+= CV18XX_TUNE_STEP
;
1001 /* find the maxinum delay which can not pass tuning */
1002 max
= min
+ CV18XX_TUNE_STEP
;
1003 while (max
< CV18XX_TUNE_MAX
) {
1004 cv18xx_sdhci_set_tap(host
, max
);
1005 if (cv18xx_retry_tuning(host
->mmc
, opcode
, NULL
)) {
1006 max
-= CV18XX_TUNE_STEP
;
1009 max
+= CV18XX_TUNE_STEP
;
1012 win_length
= max
- min
+ 1;
1013 /* get the largest pass window */
1014 if (win_length
> target_win_length
) {
1015 target_win_length
= win_length
;
1020 /* continue to find the next pass window */
1021 min
= max
+ CV18XX_TUNE_STEP
;
1024 cv18xx_sdhci_post_tuning(host
);
1026 /* use average delay to get the best timing */
1027 avg
= (target_min
+ target_max
) / 2;
1028 cv18xx_sdhci_set_tap(host
, avg
);
1029 ret
= mmc_send_tuning(host
->mmc
, opcode
, NULL
);
1031 dev_dbg(mmc_dev(host
->mmc
), "tuning %s at 0x%x ret %d\n",
1032 ret
? "failed" : "passed", avg
, ret
);
1037 static inline void sg2042_sdhci_phy_init(struct sdhci_host
*host
)
1041 /* Asset phy reset & set tx drive strength */
1042 val
= sdhci_readl(host
, PHY_CNFG_R
);
1043 val
&= ~PHY_CNFG_RSTN_DEASSERT
;
1044 val
|= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK
, 1);
1045 val
|= FIELD_PREP(PHY_CNFG_PAD_SP_MASK
, PHY_CNFG_PAD_SP_SG2042
);
1046 val
|= FIELD_PREP(PHY_CNFG_PAD_SN_MASK
, PHY_CNFG_PAD_SN_SG2042
);
1047 sdhci_writel(host
, val
, PHY_CNFG_R
);
1049 /* Configure phy pads */
1050 val
= PHY_PAD_RXSEL_3V3
;
1051 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLUP
);
1052 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
1053 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N_SG2042
);
1054 sdhci_writew(host
, val
, PHY_CMDPAD_CNFG_R
);
1055 sdhci_writew(host
, val
, PHY_DATAPAD_CNFG_R
);
1056 sdhci_writew(host
, val
, PHY_RSTNPAD_CNFG_R
);
1058 val
= PHY_PAD_RXSEL_3V3
;
1059 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
1060 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N_SG2042
);
1061 sdhci_writew(host
, val
, PHY_CLKPAD_CNFG_R
);
1063 val
= PHY_PAD_RXSEL_3V3
;
1064 val
|= FIELD_PREP(PHY_PAD_WEAKPULL_MASK
, PHY_PAD_WEAKPULL_PULLDOWN
);
1065 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK
, PHY_PAD_TXSLEW_CTRL_P
);
1066 val
|= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK
, PHY_PAD_TXSLEW_CTRL_N_SG2042
);
1067 sdhci_writew(host
, val
, PHY_STBPAD_CNFG_R
);
1069 /* Configure delay line */
1070 /* Enable fixed delay */
1071 sdhci_writeb(host
, PHY_SDCLKDL_CNFG_EXTDLY_EN
, PHY_SDCLKDL_CNFG_R
);
1074 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written.
1075 * Ensure UPDATE_DC[4] is '0' when not updating code.
1077 val
= sdhci_readb(host
, PHY_SDCLKDL_CNFG_R
);
1078 val
|= PHY_SDCLKDL_CNFG_UPDATE
;
1079 sdhci_writeb(host
, val
, PHY_SDCLKDL_CNFG_R
);
1080 /* Add 10 * 70ps = 0.7ns for output delay */
1081 sdhci_writeb(host
, 10, PHY_SDCLKDL_DC_R
);
1082 val
= sdhci_readb(host
, PHY_SDCLKDL_CNFG_R
);
1083 val
&= ~(PHY_SDCLKDL_CNFG_UPDATE
);
1084 sdhci_writeb(host
, val
, PHY_SDCLKDL_CNFG_R
);
1086 /* Set SMPLDL_CNFG, Bypass */
1087 sdhci_writeb(host
, PHY_SMPLDL_CNFG_BYPASS_EN
, PHY_SMPLDL_CNFG_R
);
1089 /* Set ATDL_CNFG, tuning clk not use for init */
1090 val
= FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK
, PHY_ATDL_CNFG_INPSEL_SG2042
);
1091 sdhci_writeb(host
, val
, PHY_ATDL_CNFG_R
);
1093 /* Deasset phy reset */
1094 val
= sdhci_readl(host
, PHY_CNFG_R
);
1095 val
|= PHY_CNFG_RSTN_DEASSERT
;
1096 sdhci_writel(host
, val
, PHY_CNFG_R
);
1099 static void sg2042_sdhci_reset(struct sdhci_host
*host
, u8 mask
)
1101 sdhci_reset(host
, mask
);
1103 if (mask
& SDHCI_RESET_ALL
)
1104 sg2042_sdhci_phy_init(host
);
1107 static int sg2042_init(struct device
*dev
, struct sdhci_host
*host
,
1108 struct dwcmshc_priv
*dwc_priv
)
1110 static const char * const clk_ids
[] = {"timer"};
1112 return dwcmshc_get_enable_other_clks(mmc_dev(host
->mmc
), dwc_priv
,
1113 ARRAY_SIZE(clk_ids
), clk_ids
);
1116 static const struct sdhci_ops sdhci_dwcmshc_ops
= {
1117 .set_clock
= sdhci_set_clock
,
1118 .set_bus_width
= sdhci_set_bus_width
,
1119 .set_uhs_signaling
= dwcmshc_set_uhs_signaling
,
1120 .get_max_clock
= dwcmshc_get_max_clock
,
1121 .reset
= sdhci_reset
,
1122 .adma_write_desc
= dwcmshc_adma_write_desc
,
1123 .irq
= dwcmshc_cqe_irq_handler
,
1127 static void dwcmshc_bf3_hw_reset(struct sdhci_host
*host
)
1129 struct arm_smccc_res res
= { 0 };
1131 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N
, 0, 0, 0, 0, 0, 0, 0, &res
);
1134 pr_err("%s: RST_N failed.\n", mmc_hostname(host
->mmc
));
1137 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops
= {
1138 .set_clock
= sdhci_set_clock
,
1139 .set_bus_width
= sdhci_set_bus_width
,
1140 .set_uhs_signaling
= dwcmshc_set_uhs_signaling
,
1141 .get_max_clock
= dwcmshc_get_max_clock
,
1142 .reset
= sdhci_reset
,
1143 .adma_write_desc
= dwcmshc_adma_write_desc
,
1144 .irq
= dwcmshc_cqe_irq_handler
,
1145 .hw_reset
= dwcmshc_bf3_hw_reset
,
1149 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops
= {
1150 .set_clock
= dwcmshc_rk3568_set_clock
,
1151 .set_bus_width
= sdhci_set_bus_width
,
1152 .set_uhs_signaling
= dwcmshc_set_uhs_signaling
,
1153 .get_max_clock
= rk35xx_get_max_clock
,
1154 .reset
= rk35xx_sdhci_reset
,
1155 .adma_write_desc
= dwcmshc_adma_write_desc
,
1156 .irq
= dwcmshc_cqe_irq_handler
,
1159 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops
= {
1160 .set_clock
= sdhci_set_clock
,
1161 .set_bus_width
= sdhci_set_bus_width
,
1162 .set_uhs_signaling
= th1520_set_uhs_signaling
,
1163 .get_max_clock
= dwcmshc_get_max_clock
,
1164 .reset
= th1520_sdhci_reset
,
1165 .adma_write_desc
= dwcmshc_adma_write_desc
,
1166 .voltage_switch
= dwcmshc_phy_1_8v_init
,
1167 .platform_execute_tuning
= th1520_execute_tuning
,
1170 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops
= {
1171 .set_clock
= sdhci_set_clock
,
1172 .set_bus_width
= sdhci_set_bus_width
,
1173 .set_uhs_signaling
= dwcmshc_set_uhs_signaling
,
1174 .get_max_clock
= dwcmshc_get_max_clock
,
1175 .reset
= cv18xx_sdhci_reset
,
1176 .adma_write_desc
= dwcmshc_adma_write_desc
,
1177 .platform_execute_tuning
= cv18xx_sdhci_execute_tuning
,
1180 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops
= {
1181 .set_clock
= sdhci_set_clock
,
1182 .set_bus_width
= sdhci_set_bus_width
,
1183 .set_uhs_signaling
= dwcmshc_set_uhs_signaling
,
1184 .get_max_clock
= dwcmshc_get_max_clock
,
1185 .reset
= sg2042_sdhci_reset
,
1186 .adma_write_desc
= dwcmshc_adma_write_desc
,
1187 .platform_execute_tuning
= th1520_execute_tuning
,
1190 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata
= {
1192 .ops
= &sdhci_dwcmshc_ops
,
1193 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1194 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1199 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata
= {
1201 .ops
= &sdhci_dwcmshc_bf3_ops
,
1202 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1203 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
|
1204 SDHCI_QUIRK2_ACMD23_BROKEN
,
1209 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata
= {
1211 .ops
= &sdhci_dwcmshc_rk35xx_ops
,
1212 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
|
1213 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
,
1214 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
|
1215 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
,
1217 .init
= dwcmshc_rk35xx_init
,
1218 .postinit
= dwcmshc_rk35xx_postinit
,
1221 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata
= {
1223 .ops
= &sdhci_dwcmshc_th1520_ops
,
1224 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1225 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1227 .init
= th1520_init
,
1230 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata
= {
1232 .ops
= &sdhci_dwcmshc_cv18xx_ops
,
1233 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1234 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1238 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata
= {
1240 .ops
= &sdhci_dwcmshc_sg2042_ops
,
1241 .quirks
= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1242 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1244 .init
= sg2042_init
,
1247 static const struct cqhci_host_ops dwcmshc_cqhci_ops
= {
1248 .enable
= dwcmshc_sdhci_cqe_enable
,
1249 .disable
= sdhci_cqe_disable
,
1250 .dumpregs
= dwcmshc_cqhci_dumpregs
,
1251 .set_tran_desc
= dwcmshc_set_tran_desc
,
1254 static void dwcmshc_cqhci_init(struct sdhci_host
*host
, struct platform_device
*pdev
)
1256 struct cqhci_host
*cq_host
;
1257 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1258 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
1263 host
->mmc
->caps2
|= MMC_CAP2_CQE
| MMC_CAP2_CQE_DCMD
;
1264 cq_host
= devm_kzalloc(&pdev
->dev
, sizeof(*cq_host
), GFP_KERNEL
);
1266 dev_err(mmc_dev(host
->mmc
), "Unable to setup CQE: not enough memory\n");
1271 * For dwcmshc host controller we have to enable internal clock
1272 * before access to some registers from Vendor Specific Area 2.
1274 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1275 clk
|= SDHCI_CLOCK_INT_EN
;
1276 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1277 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1278 if (!(clk
& SDHCI_CLOCK_INT_EN
)) {
1279 dev_err(mmc_dev(host
->mmc
), "Unable to setup CQE: internal clock enable error\n");
1283 cq_host
->mmio
= host
->ioaddr
+ priv
->vendor_specific_area2
;
1284 cq_host
->ops
= &dwcmshc_cqhci_ops
;
1286 /* Enable using of 128-bit task descriptors */
1287 dma64
= host
->flags
& SDHCI_USE_64_BIT_DMA
;
1289 dev_dbg(mmc_dev(host
->mmc
), "128-bit task descriptors\n");
1290 cq_host
->caps
|= CQHCI_TASK_DESC_SZ_128
;
1292 err
= cqhci_init(cq_host
, host
->mmc
, dma64
);
1294 dev_err(mmc_dev(host
->mmc
), "Unable to setup CQE: error %d\n", err
);
1295 goto int_clock_disable
;
1298 dev_dbg(mmc_dev(host
->mmc
), "CQE init done\n");
1303 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1304 clk
&= ~SDHCI_CLOCK_INT_EN
;
1305 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1308 devm_kfree(&pdev
->dev
, cq_host
);
1311 host
->mmc
->caps2
&= ~(MMC_CAP2_CQE
| MMC_CAP2_CQE_DCMD
);
1314 static const struct of_device_id sdhci_dwcmshc_dt_ids
[] = {
1316 .compatible
= "rockchip,rk3588-dwcmshc",
1317 .data
= &sdhci_dwcmshc_rk35xx_pdata
,
1320 .compatible
= "rockchip,rk3568-dwcmshc",
1321 .data
= &sdhci_dwcmshc_rk35xx_pdata
,
1324 .compatible
= "snps,dwcmshc-sdhci",
1325 .data
= &sdhci_dwcmshc_pdata
,
1328 .compatible
= "sophgo,cv1800b-dwcmshc",
1329 .data
= &sdhci_dwcmshc_cv18xx_pdata
,
1332 .compatible
= "sophgo,sg2002-dwcmshc",
1333 .data
= &sdhci_dwcmshc_cv18xx_pdata
,
1336 .compatible
= "thead,th1520-dwcmshc",
1337 .data
= &sdhci_dwcmshc_th1520_pdata
,
1340 .compatible
= "sophgo,sg2042-dwcmshc",
1341 .data
= &sdhci_dwcmshc_sg2042_pdata
,
1345 MODULE_DEVICE_TABLE(of
, sdhci_dwcmshc_dt_ids
);
1348 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids
[] = {
1351 .driver_data
= (kernel_ulong_t
)&sdhci_dwcmshc_bf3_pdata
,
1355 MODULE_DEVICE_TABLE(acpi
, sdhci_dwcmshc_acpi_ids
);
1358 static int dwcmshc_probe(struct platform_device
*pdev
)
1360 struct device
*dev
= &pdev
->dev
;
1361 struct sdhci_pltfm_host
*pltfm_host
;
1362 struct sdhci_host
*host
;
1363 struct dwcmshc_priv
*priv
;
1364 const struct dwcmshc_pltfm_data
*pltfm_data
;
1368 pltfm_data
= device_get_match_data(&pdev
->dev
);
1370 dev_err(&pdev
->dev
, "Error: No device match data found\n");
1374 host
= sdhci_pltfm_init(pdev
, &pltfm_data
->pdata
,
1375 sizeof(struct dwcmshc_priv
));
1377 return PTR_ERR(host
);
1380 * extra adma table cnt for cross 128M boundary handling.
1382 extra
= DIV_ROUND_UP_ULL(dma_get_required_mask(dev
), SZ_128M
);
1383 if (extra
> SDHCI_MAX_SEGS
)
1384 extra
= SDHCI_MAX_SEGS
;
1385 host
->adma_table_cnt
+= extra
;
1387 pltfm_host
= sdhci_priv(host
);
1388 priv
= sdhci_pltfm_priv(pltfm_host
);
1391 pltfm_host
->clk
= devm_clk_get(dev
, "core");
1392 if (IS_ERR(pltfm_host
->clk
)) {
1393 err
= PTR_ERR(pltfm_host
->clk
);
1394 dev_err(dev
, "failed to get core clk: %d\n", err
);
1397 err
= clk_prepare_enable(pltfm_host
->clk
);
1401 priv
->bus_clk
= devm_clk_get(dev
, "bus");
1402 if (!IS_ERR(priv
->bus_clk
))
1403 clk_prepare_enable(priv
->bus_clk
);
1406 err
= mmc_of_parse(host
->mmc
);
1410 sdhci_get_of_property(pdev
);
1412 priv
->vendor_specific_area1
=
1413 sdhci_readl(host
, DWCMSHC_P_VENDOR_AREA1
) & DWCMSHC_AREA1_MASK
;
1415 host
->mmc_host_ops
.request
= dwcmshc_request
;
1416 host
->mmc_host_ops
.hs400_enhanced_strobe
= dwcmshc_hs400_enhanced_strobe
;
1417 host
->mmc_host_ops
.execute_tuning
= dwcmshc_execute_tuning
;
1419 if (pltfm_data
->init
) {
1420 err
= pltfm_data
->init(&pdev
->dev
, host
, priv
);
1426 if (pltfm_data
== &sdhci_dwcmshc_bf3_pdata
)
1427 sdhci_enable_v4_mode(host
);
1430 caps
= sdhci_readl(host
, SDHCI_CAPABILITIES
);
1431 if (caps
& SDHCI_CAN_64BIT_V4
)
1432 sdhci_enable_v4_mode(host
);
1434 host
->mmc
->caps
|= MMC_CAP_WAIT_WHILE_BUSY
;
1436 pm_runtime_get_noresume(dev
);
1437 pm_runtime_set_active(dev
);
1438 pm_runtime_enable(dev
);
1440 err
= sdhci_setup_host(host
);
1444 /* Setup Command Queue Engine if enabled */
1445 if (device_property_read_bool(&pdev
->dev
, "supports-cqe")) {
1446 priv
->vendor_specific_area2
=
1447 sdhci_readw(host
, DWCMSHC_P_VENDOR_AREA2
);
1449 dwcmshc_cqhci_init(host
, pdev
);
1452 if (pltfm_data
->postinit
)
1453 pltfm_data
->postinit(host
, priv
);
1455 err
= __sdhci_add_host(host
);
1457 goto err_setup_host
;
1459 pm_runtime_put(dev
);
1464 sdhci_cleanup_host(host
);
1466 pm_runtime_disable(dev
);
1467 pm_runtime_put_noidle(dev
);
1469 clk_disable_unprepare(pltfm_host
->clk
);
1470 clk_disable_unprepare(priv
->bus_clk
);
1471 clk_bulk_disable_unprepare(priv
->num_other_clks
, priv
->other_clks
);
1473 sdhci_pltfm_free(pdev
);
1477 static void dwcmshc_disable_card_clk(struct sdhci_host
*host
)
1481 ctrl
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1482 if (ctrl
& SDHCI_CLOCK_CARD_EN
) {
1483 ctrl
&= ~SDHCI_CLOCK_CARD_EN
;
1484 sdhci_writew(host
, ctrl
, SDHCI_CLOCK_CONTROL
);
1488 static void dwcmshc_remove(struct platform_device
*pdev
)
1490 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
1491 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1492 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
1494 pm_runtime_get_sync(&pdev
->dev
);
1495 pm_runtime_disable(&pdev
->dev
);
1496 pm_runtime_put_noidle(&pdev
->dev
);
1498 sdhci_remove_host(host
, 0);
1500 dwcmshc_disable_card_clk(host
);
1502 clk_disable_unprepare(pltfm_host
->clk
);
1503 clk_disable_unprepare(priv
->bus_clk
);
1504 clk_bulk_disable_unprepare(priv
->num_other_clks
, priv
->other_clks
);
1505 sdhci_pltfm_free(pdev
);
1508 #ifdef CONFIG_PM_SLEEP
1509 static int dwcmshc_suspend(struct device
*dev
)
1511 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1512 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1513 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
1516 pm_runtime_resume(dev
);
1518 if (host
->mmc
->caps2
& MMC_CAP2_CQE
) {
1519 ret
= cqhci_suspend(host
->mmc
);
1524 ret
= sdhci_suspend_host(host
);
1528 clk_disable_unprepare(pltfm_host
->clk
);
1529 if (!IS_ERR(priv
->bus_clk
))
1530 clk_disable_unprepare(priv
->bus_clk
);
1532 clk_bulk_disable_unprepare(priv
->num_other_clks
, priv
->other_clks
);
1537 static int dwcmshc_resume(struct device
*dev
)
1539 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1540 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1541 struct dwcmshc_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
1544 ret
= clk_prepare_enable(pltfm_host
->clk
);
1548 if (!IS_ERR(priv
->bus_clk
)) {
1549 ret
= clk_prepare_enable(priv
->bus_clk
);
1554 ret
= clk_bulk_prepare_enable(priv
->num_other_clks
, priv
->other_clks
);
1556 goto disable_bus_clk
;
1558 ret
= sdhci_resume_host(host
);
1560 goto disable_other_clks
;
1562 if (host
->mmc
->caps2
& MMC_CAP2_CQE
) {
1563 ret
= cqhci_resume(host
->mmc
);
1565 goto disable_other_clks
;
1571 clk_bulk_disable_unprepare(priv
->num_other_clks
, priv
->other_clks
);
1573 if (!IS_ERR(priv
->bus_clk
))
1574 clk_disable_unprepare(priv
->bus_clk
);
1576 clk_disable_unprepare(pltfm_host
->clk
);
1583 static void dwcmshc_enable_card_clk(struct sdhci_host
*host
)
1587 ctrl
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1588 if ((ctrl
& SDHCI_CLOCK_INT_EN
) && !(ctrl
& SDHCI_CLOCK_CARD_EN
)) {
1589 ctrl
|= SDHCI_CLOCK_CARD_EN
;
1590 sdhci_writew(host
, ctrl
, SDHCI_CLOCK_CONTROL
);
1594 static int dwcmshc_runtime_suspend(struct device
*dev
)
1596 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1598 dwcmshc_disable_card_clk(host
);
1603 static int dwcmshc_runtime_resume(struct device
*dev
)
1605 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1607 dwcmshc_enable_card_clk(host
);
1614 static const struct dev_pm_ops dwcmshc_pmops
= {
1615 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend
, dwcmshc_resume
)
1616 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend
,
1617 dwcmshc_runtime_resume
, NULL
)
1620 static struct platform_driver sdhci_dwcmshc_driver
= {
1622 .name
= "sdhci-dwcmshc",
1623 .probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
1624 .of_match_table
= sdhci_dwcmshc_dt_ids
,
1625 .acpi_match_table
= ACPI_PTR(sdhci_dwcmshc_acpi_ids
),
1626 .pm
= &dwcmshc_pmops
,
1628 .probe
= dwcmshc_probe
,
1629 .remove
= dwcmshc_remove
,
1631 module_platform_driver(sdhci_dwcmshc_driver
);
1633 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
1634 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
1635 MODULE_LICENSE("GPL v2");