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printf: Remove unused 'bprintf'
[drm/drm-misc.git] / drivers / pci / controller / pcie-rockchip-ep.c
blob1064b7b06cef64f0848d9b22d4edce5994d8f054
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip AXI PCIe endpoint controller driver
4 *
5 * Copyright (c) 2018 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/configfs.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/irq.h>
17 #include <linux/of.h>
18 #include <linux/pci-epc.h>
19 #include <linux/platform_device.h>
20 #include <linux/pci-epf.h>
21 #include <linux/sizes.h>
22 #include <linux/workqueue.h>
23
24 #include "pcie-rockchip.h"
25
26 /**
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
28 * @rockchip: Rockchip PCIe controller
29 * @epc: PCI EPC device
30 * @max_regions: maximum number of regions supported by hardware
31 * @ob_region_map: bitmask of mapped outbound regions
32 * @ob_addr: base addresses in the AXI bus where the outbound regions start
33 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
34 * dedicated outbound regions is mapped.
35 * @irq_cpu_addr: base address in the CPU space where a write access triggers
36 * the sending of a memory write (MSI) / normal message (INTX
37 * IRQ) TLP through the PCIe bus.
38 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
39 * dedicated outbound region.
40 * @irq_pci_fn: the latest PCI function that has updated the mapping of
41 * the MSI/INTX IRQ dedicated outbound region.
42 * @irq_pending: bitmask of asserted INTX IRQs.
43 */
44 struct rockchip_pcie_ep {
45 struct rockchip_pcie rockchip;
46 struct pci_epc *epc;
47 u32 max_regions;
48 unsigned long ob_region_map;
49 phys_addr_t *ob_addr;
50 phys_addr_t irq_phys_addr;
51 void __iomem *irq_cpu_addr;
52 u64 irq_pci_addr;
53 u8 irq_pci_fn;
54 u8 irq_pending;
55 int perst_irq;
56 bool perst_asserted;
57 bool link_up;
58 struct delayed_work link_training;
59 };
60
61 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
62 u32 region)
63 {
64 rockchip_pcie_write(rockchip, 0,
65 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
66 rockchip_pcie_write(rockchip, 0,
67 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
68 rockchip_pcie_write(rockchip, 0,
69 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
70 rockchip_pcie_write(rockchip, 0,
71 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
72 }
73
74 static int rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie *rockchip,
75 u64 pci_addr, size_t size)
76 {
77 int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1));
78
79 return clamp(num_pass_bits,
80 ROCKCHIP_PCIE_AT_MIN_NUM_BITS,
81 ROCKCHIP_PCIE_AT_MAX_NUM_BITS);
82 }
83
84 static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
85 u32 r, u64 cpu_addr, u64 pci_addr,
86 size_t size)
87 {
88 int num_pass_bits;
89 u32 addr0, addr1, desc0;
90
91 num_pass_bits = rockchip_pcie_ep_ob_atu_num_bits(rockchip,
92 pci_addr, size);
93
94 addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
95 (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
96 addr1 = upper_32_bits(pci_addr);
97 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | AXI_WRAPPER_MEM_WRITE;
98
99 /* PCI bus address region */
100 rockchip_pcie_write(rockchip, addr0,
101 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
102 rockchip_pcie_write(rockchip, addr1,
103 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
104 rockchip_pcie_write(rockchip, desc0,
105 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
106 rockchip_pcie_write(rockchip, 0,
107 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
108 }
109
110 static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
111 struct pci_epf_header *hdr)
112 {
113 u32 reg;
114 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
115 struct rockchip_pcie *rockchip = &ep->rockchip;
116
117 /* All functions share the same vendor ID with function 0 */
118 if (fn == 0) {
119 rockchip_pcie_write(rockchip,
120 hdr->vendorid | hdr->subsys_vendor_id << 16,
121 PCIE_CORE_CONFIG_VENDOR);
122 }
123
124 reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
125 reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
126 rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
127
128 rockchip_pcie_write(rockchip,
129 hdr->revid |
130 hdr->progif_code << 8 |
131 hdr->subclass_code << 16 |
132 hdr->baseclass_code << 24,
133 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
134 rockchip_pcie_write(rockchip, hdr->cache_line_size,
135 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
136 PCI_CACHE_LINE_SIZE);
137 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
138 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
139 PCI_SUBSYSTEM_VENDOR_ID);
140 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
141 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
142 PCI_INTERRUPT_LINE);
143
144 return 0;
145 }
146
147 static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
148 struct pci_epf_bar *epf_bar)
149 {
150 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
151 struct rockchip_pcie *rockchip = &ep->rockchip;
152 dma_addr_t bar_phys = epf_bar->phys_addr;
153 enum pci_barno bar = epf_bar->barno;
154 int flags = epf_bar->flags;
155 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
156 u64 sz;
157
158 /* BAR size is 2^(aperture + 7) */
159 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
160
161 /*
162 * roundup_pow_of_two() returns an unsigned long, which is not suited
163 * for 64bit values.
164 */
165 sz = 1ULL << fls64(sz - 1);
166 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
167
168 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
169 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
170 } else {
171 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
172 bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
173
174 if (is_64bits && (bar & 1))
175 return -EINVAL;
176
177 if (is_64bits && is_prefetch)
178 ctrl =
179 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
180 else if (is_prefetch)
181 ctrl =
182 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
183 else if (is_64bits)
184 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
185 else
186 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
187 }
188
189 if (bar < BAR_4) {
190 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
191 b = bar;
192 } else {
193 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
194 b = bar - BAR_4;
195 }
196
197 addr0 = lower_32_bits(bar_phys);
198 addr1 = upper_32_bits(bar_phys);
199
200 cfg = rockchip_pcie_read(rockchip, reg);
201 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
202 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
203 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
204 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
205
206 rockchip_pcie_write(rockchip, cfg, reg);
207 rockchip_pcie_write(rockchip, addr0,
208 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
209 rockchip_pcie_write(rockchip, addr1,
210 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
211
212 return 0;
213 }
214
215 static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
216 struct pci_epf_bar *epf_bar)
217 {
218 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
219 struct rockchip_pcie *rockchip = &ep->rockchip;
220 u32 reg, cfg, b, ctrl;
221 enum pci_barno bar = epf_bar->barno;
222
223 if (bar < BAR_4) {
224 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
225 b = bar;
226 } else {
227 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
228 b = bar - BAR_4;
229 }
230
231 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
232 cfg = rockchip_pcie_read(rockchip, reg);
233 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
234 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
235 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
236
237 rockchip_pcie_write(rockchip, cfg, reg);
238 rockchip_pcie_write(rockchip, 0x0,
239 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
240 rockchip_pcie_write(rockchip, 0x0,
241 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
242 }
243
244 static inline u32 rockchip_ob_region(phys_addr_t addr)
245 {
246 return (addr >> ilog2(SZ_1M)) & 0x1f;
247 }
248
249 static u64 rockchip_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr,
250 size_t *pci_size, size_t *addr_offset)
251 {
252 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
253 size_t size = *pci_size;
254 u64 offset, mask;
255 int num_bits;
256
257 num_bits = rockchip_pcie_ep_ob_atu_num_bits(&ep->rockchip,
258 pci_addr, size);
259 mask = (1ULL << num_bits) - 1;
260
261 offset = pci_addr & mask;
262 if (size + offset > SZ_1M)
263 size = SZ_1M - offset;
264
265 *pci_size = ALIGN(offset + size, ROCKCHIP_PCIE_AT_SIZE_ALIGN);
266 *addr_offset = offset;
267
268 return pci_addr & ~mask;
269 }
270
271 static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
272 phys_addr_t addr, u64 pci_addr,
273 size_t size)
274 {
275 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
276 struct rockchip_pcie *pcie = &ep->rockchip;
277 u32 r = rockchip_ob_region(addr);
278
279 if (test_bit(r, &ep->ob_region_map))
280 return -EBUSY;
281
282 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size);
283
284 set_bit(r, &ep->ob_region_map);
285 ep->ob_addr[r] = addr;
286
287 return 0;
288 }
289
290 static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
291 phys_addr_t addr)
292 {
293 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
294 struct rockchip_pcie *rockchip = &ep->rockchip;
295 u32 r = rockchip_ob_region(addr);
296
297 if (addr != ep->ob_addr[r] || !test_bit(r, &ep->ob_region_map))
298 return;
299
300 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
301
302 ep->ob_addr[r] = 0;
303 clear_bit(r, &ep->ob_region_map);
304 }
305
306 static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
307 u8 multi_msg_cap)
308 {
309 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
310 struct rockchip_pcie *rockchip = &ep->rockchip;
311 u32 flags;
312
313 flags = rockchip_pcie_read(rockchip,
314 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
315 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
316 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
317 flags |=
318 (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
319 (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
320 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
321 rockchip_pcie_write(rockchip, flags,
322 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
323 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
324 return 0;
325 }
326
327 static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
328 {
329 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
330 struct rockchip_pcie *rockchip = &ep->rockchip;
331 u32 flags;
332
333 flags = rockchip_pcie_read(rockchip,
334 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
335 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
336 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
337 return -EINVAL;
338
339 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
340 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
341 }
342
343 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
344 u8 intx, bool do_assert)
345 {
346 struct rockchip_pcie *rockchip = &ep->rockchip;
347
348 intx &= 3;
349
350 if (do_assert) {
351 ep->irq_pending |= BIT(intx);
352 rockchip_pcie_write(rockchip,
353 PCIE_CLIENT_INT_IN_ASSERT |
354 PCIE_CLIENT_INT_PEND_ST_PEND,
355 PCIE_CLIENT_LEGACY_INT_CTRL);
356 } else {
357 ep->irq_pending &= ~BIT(intx);
358 rockchip_pcie_write(rockchip,
359 PCIE_CLIENT_INT_IN_DEASSERT |
360 PCIE_CLIENT_INT_PEND_ST_NORMAL,
361 PCIE_CLIENT_LEGACY_INT_CTRL);
362 }
363 }
364
365 static int rockchip_pcie_ep_send_intx_irq(struct rockchip_pcie_ep *ep, u8 fn,
366 u8 intx)
367 {
368 u16 cmd;
369
370 cmd = rockchip_pcie_read(&ep->rockchip,
371 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
372 ROCKCHIP_PCIE_EP_CMD_STATUS);
373
374 if (cmd & PCI_COMMAND_INTX_DISABLE)
375 return -EINVAL;
376
377 /*
378 * Should add some delay between toggling INTx per TRM vaguely saying
379 * it depends on some cycles of the AHB bus clock to function it. So
380 * add sufficient 1ms here.
381 */
382 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
383 mdelay(1);
384 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
385 return 0;
386 }
387
388 static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
389 u8 interrupt_num)
390 {
391 struct rockchip_pcie *rockchip = &ep->rockchip;
392 u32 flags, mme, data, data_mask;
393 size_t irq_pci_size, offset;
394 u64 irq_pci_addr;
395 u8 msi_count;
396 u64 pci_addr;
397
398 /* Check MSI enable bit */
399 flags = rockchip_pcie_read(&ep->rockchip,
400 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
401 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
402 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
403 return -EINVAL;
404
405 /* Get MSI numbers from MME */
406 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
407 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
408 msi_count = 1 << mme;
409 if (!interrupt_num || interrupt_num > msi_count)
410 return -EINVAL;
411
412 /* Set MSI private data */
413 data_mask = msi_count - 1;
414 data = rockchip_pcie_read(rockchip,
415 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
416 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
417 PCI_MSI_DATA_64);
418 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
419
420 /* Get MSI PCI address */
421 pci_addr = rockchip_pcie_read(rockchip,
422 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
423 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
424 PCI_MSI_ADDRESS_HI);
425 pci_addr <<= 32;
426 pci_addr |= rockchip_pcie_read(rockchip,
427 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
428 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
429 PCI_MSI_ADDRESS_LO);
430
431 /* Set the outbound region if needed. */
432 irq_pci_size = ~PCIE_ADDR_MASK + 1;
433 irq_pci_addr = rockchip_pcie_ep_align_addr(ep->epc,
434 pci_addr & PCIE_ADDR_MASK,
435 &irq_pci_size, &offset);
436 if (unlikely(ep->irq_pci_addr != irq_pci_addr ||
437 ep->irq_pci_fn != fn)) {
438 rockchip_pcie_prog_ep_ob_atu(rockchip, fn,
439 rockchip_ob_region(ep->irq_phys_addr),
440 ep->irq_phys_addr,
441 irq_pci_addr, irq_pci_size);
442 ep->irq_pci_addr = irq_pci_addr;
443 ep->irq_pci_fn = fn;
444 }
445
446 writew(data, ep->irq_cpu_addr + offset + (pci_addr & ~PCIE_ADDR_MASK));
447 return 0;
448 }
449
450 static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
451 unsigned int type, u16 interrupt_num)
452 {
453 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
454
455 switch (type) {
456 case PCI_IRQ_INTX:
457 return rockchip_pcie_ep_send_intx_irq(ep, fn, 0);
458 case PCI_IRQ_MSI:
459 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
460 default:
461 return -EINVAL;
462 }
463 }
464
465 static int rockchip_pcie_ep_start(struct pci_epc *epc)
466 {
467 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
468 struct rockchip_pcie *rockchip = &ep->rockchip;
469 struct pci_epf *epf;
470 u32 cfg;
471
472 cfg = BIT(0);
473 list_for_each_entry(epf, &epc->pci_epf, list)
474 cfg |= BIT(epf->func_no);
475
476 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
477
478 if (rockchip->perst_gpio)
479 enable_irq(ep->perst_irq);
480
481 /* Enable configuration and start link training */
482 rockchip_pcie_write(rockchip,
483 PCIE_CLIENT_LINK_TRAIN_ENABLE |
484 PCIE_CLIENT_CONF_ENABLE,
485 PCIE_CLIENT_CONFIG);
486
487 if (!rockchip->perst_gpio)
488 schedule_delayed_work(&ep->link_training, 0);
489
490 return 0;
491 }
492
493 static void rockchip_pcie_ep_stop(struct pci_epc *epc)
494 {
495 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
496 struct rockchip_pcie *rockchip = &ep->rockchip;
497
498 if (rockchip->perst_gpio) {
499 ep->perst_asserted = true;
500 disable_irq(ep->perst_irq);
501 }
502
503 cancel_delayed_work_sync(&ep->link_training);
504
505 /* Stop link training and disable configuration */
506 rockchip_pcie_write(rockchip,
507 PCIE_CLIENT_CONF_DISABLE |
508 PCIE_CLIENT_LINK_TRAIN_DISABLE,
509 PCIE_CLIENT_CONFIG);
510 }
511
512 static void rockchip_pcie_ep_retrain_link(struct rockchip_pcie *rockchip)
513 {
514 u32 status;
515
516 status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS);
517 status |= PCI_EXP_LNKCTL_RL;
518 rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS);
519 }
520
521 static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip)
522 {
523 u32 val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
524
525 return PCIE_LINK_UP(val);
526 }
527
528 static void rockchip_pcie_ep_link_training(struct work_struct *work)
529 {
530 struct rockchip_pcie_ep *ep =
531 container_of(work, struct rockchip_pcie_ep, link_training.work);
532 struct rockchip_pcie *rockchip = &ep->rockchip;
533 struct device *dev = rockchip->dev;
534 u32 val;
535 int ret;
536
537 /* Enable Gen1 training and wait for its completion */
538 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
539 val, PCIE_LINK_TRAINING_DONE(val), 50,
540 LINK_TRAIN_TIMEOUT);
541 if (ret)
542 goto again;
543
544 /* Make sure that the link is up */
545 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
546 val, PCIE_LINK_UP(val), 50,
547 LINK_TRAIN_TIMEOUT);
548 if (ret)
549 goto again;
550
551 /*
552 * Check the current speed: if gen2 speed was requested and we are not
553 * at gen2 speed yet, retrain again for gen2.
554 */
555 val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
556 if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) {
557 /* Enable retrain for gen2 */
558 rockchip_pcie_ep_retrain_link(rockchip);
559 readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
560 val, PCIE_LINK_IS_GEN2(val), 50,
561 LINK_TRAIN_TIMEOUT);
562 }
563
564 /* Check again that the link is up */
565 if (!rockchip_pcie_ep_link_up(rockchip))
566 goto again;
567
568 /*
569 * If PERST# was asserted while polling the link, do not notify
570 * the function.
571 */
572 if (ep->perst_asserted)
573 return;
574
575 val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS0);
576 dev_info(dev,
577 "link up (negotiated speed: %sGT/s, width: x%lu)\n",
578 (val & PCIE_CLIENT_NEG_LINK_SPEED) ? "5" : "2.5",
579 ((val & PCIE_CLIENT_NEG_LINK_WIDTH_MASK) >>
580 PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT) << 1);
581
582 /* Notify the function */
583 pci_epc_linkup(ep->epc);
584 ep->link_up = true;
585
586 return;
587
588 again:
589 schedule_delayed_work(&ep->link_training, msecs_to_jiffies(5));
590 }
591
592 static void rockchip_pcie_ep_perst_assert(struct rockchip_pcie_ep *ep)
593 {
594 struct rockchip_pcie *rockchip = &ep->rockchip;
595
596 dev_dbg(rockchip->dev, "PERST# asserted, link down\n");
597
598 if (ep->perst_asserted)
599 return;
600
601 ep->perst_asserted = true;
602
603 cancel_delayed_work_sync(&ep->link_training);
604
605 if (ep->link_up) {
606 pci_epc_linkdown(ep->epc);
607 ep->link_up = false;
608 }
609 }
610
611 static void rockchip_pcie_ep_perst_deassert(struct rockchip_pcie_ep *ep)
612 {
613 struct rockchip_pcie *rockchip = &ep->rockchip;
614
615 dev_dbg(rockchip->dev, "PERST# de-asserted, starting link training\n");
616
617 if (!ep->perst_asserted)
618 return;
619
620 ep->perst_asserted = false;
621
622 /* Enable link re-training */
623 rockchip_pcie_ep_retrain_link(rockchip);
624
625 /* Start link training */
626 schedule_delayed_work(&ep->link_training, 0);
627 }
628
629 static irqreturn_t rockchip_pcie_ep_perst_irq_thread(int irq, void *data)
630 {
631 struct pci_epc *epc = data;
632 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
633 struct rockchip_pcie *rockchip = &ep->rockchip;
634 u32 perst = gpiod_get_value(rockchip->perst_gpio);
635
636 if (perst)
637 rockchip_pcie_ep_perst_assert(ep);
638 else
639 rockchip_pcie_ep_perst_deassert(ep);
640
641 irq_set_irq_type(ep->perst_irq,
642 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
643
644 return IRQ_HANDLED;
645 }
646
647 static int rockchip_pcie_ep_setup_irq(struct pci_epc *epc)
648 {
649 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
650 struct rockchip_pcie *rockchip = &ep->rockchip;
651 struct device *dev = rockchip->dev;
652 int ret;
653
654 if (!rockchip->perst_gpio)
655 return 0;
656
657 /* PCIe reset interrupt */
658 ep->perst_irq = gpiod_to_irq(rockchip->perst_gpio);
659 if (ep->perst_irq < 0) {
660 dev_err(dev,
661 "failed to get IRQ for PERST# GPIO: %d\n",
662 ep->perst_irq);
663
664 return ep->perst_irq;
665 }
666
667 /*
668 * The perst_gpio is active low, so when it is inactive on start, it
669 * is high and will trigger the perst_irq handler. So treat this initial
670 * IRQ as a dummy one by faking the host asserting PERST#.
671 */
672 ep->perst_asserted = true;
673 irq_set_status_flags(ep->perst_irq, IRQ_NOAUTOEN);
674 ret = devm_request_threaded_irq(dev, ep->perst_irq, NULL,
675 rockchip_pcie_ep_perst_irq_thread,
676 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
677 "pcie-ep-perst", epc);
678 if (ret) {
679 dev_err(dev,
680 "failed to request IRQ for PERST# GPIO: %d\n",
681 ret);
682
683 return ret;
684 }
685
686 return 0;
687 }
688
689 static const struct pci_epc_features rockchip_pcie_epc_features = {
690 .linkup_notifier = true,
691 .msi_capable = true,
692 .msix_capable = false,
693 .align = ROCKCHIP_PCIE_AT_SIZE_ALIGN,
694 };
695
696 static const struct pci_epc_features*
697 rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
698 {
699 return &rockchip_pcie_epc_features;
700 }
701
702 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
703 .write_header = rockchip_pcie_ep_write_header,
704 .set_bar = rockchip_pcie_ep_set_bar,
705 .clear_bar = rockchip_pcie_ep_clear_bar,
706 .align_addr = rockchip_pcie_ep_align_addr,
707 .map_addr = rockchip_pcie_ep_map_addr,
708 .unmap_addr = rockchip_pcie_ep_unmap_addr,
709 .set_msi = rockchip_pcie_ep_set_msi,
710 .get_msi = rockchip_pcie_ep_get_msi,
711 .raise_irq = rockchip_pcie_ep_raise_irq,
712 .start = rockchip_pcie_ep_start,
713 .stop = rockchip_pcie_ep_stop,
714 .get_features = rockchip_pcie_ep_get_features,
715 };
716
717 static int rockchip_pcie_ep_get_resources(struct rockchip_pcie *rockchip,
718 struct rockchip_pcie_ep *ep)
719 {
720 struct device *dev = rockchip->dev;
721 int err;
722
723 err = rockchip_pcie_parse_dt(rockchip);
724 if (err)
725 return err;
726
727 err = rockchip_pcie_get_phys(rockchip);
728 if (err)
729 return err;
730
731 err = of_property_read_u32(dev->of_node,
732 "rockchip,max-outbound-regions",
733 &ep->max_regions);
734 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
735 ep->max_regions = MAX_REGION_LIMIT;
736
737 ep->ob_region_map = 0;
738
739 err = of_property_read_u8(dev->of_node, "max-functions",
740 &ep->epc->max_functions);
741 if (err < 0)
742 ep->epc->max_functions = 1;
743
744 return 0;
745 }
746
747 static const struct of_device_id rockchip_pcie_ep_of_match[] = {
748 { .compatible = "rockchip,rk3399-pcie-ep"},
749 {},
750 };
751
752 static int rockchip_pcie_ep_init_ob_mem(struct rockchip_pcie_ep *ep)
753 {
754 struct rockchip_pcie *rockchip = &ep->rockchip;
755 struct device *dev = rockchip->dev;
756 struct pci_epc_mem_window *windows = NULL;
757 int err, i;
758
759 ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr),
760 GFP_KERNEL);
761
762 if (!ep->ob_addr)
763 return -ENOMEM;
764
765 windows = devm_kcalloc(dev, ep->max_regions,
766 sizeof(struct pci_epc_mem_window), GFP_KERNEL);
767 if (!windows)
768 return -ENOMEM;
769
770 for (i = 0; i < ep->max_regions; i++) {
771 windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i);
772 windows[i].size = SZ_1M;
773 windows[i].page_size = SZ_1M;
774 }
775 err = pci_epc_multi_mem_init(ep->epc, windows, ep->max_regions);
776 devm_kfree(dev, windows);
777
778 if (err < 0) {
779 dev_err(dev, "failed to initialize the memory space\n");
780 return err;
781 }
782
783 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(ep->epc, &ep->irq_phys_addr,
784 SZ_1M);
785 if (!ep->irq_cpu_addr) {
786 dev_err(dev, "failed to reserve memory space for MSI\n");
787 goto err_epc_mem_exit;
788 }
789
790 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
791
792 return 0;
793
794 err_epc_mem_exit:
795 pci_epc_mem_exit(ep->epc);
796
797 return err;
798 }
799
800 static void rockchip_pcie_ep_exit_ob_mem(struct rockchip_pcie_ep *ep)
801 {
802 pci_epc_mem_exit(ep->epc);
803 }
804
805 static void rockchip_pcie_ep_hide_broken_msix_cap(struct rockchip_pcie *rockchip)
806 {
807 u32 cfg_msi, cfg_msix_cp;
808
809 /*
810 * MSI-X is not supported but the controller still advertises the MSI-X
811 * capability by default, which can lead to the Root Complex side
812 * allocating MSI-X vectors which cannot be used. Avoid this by skipping
813 * the MSI-X capability entry in the PCIe capabilities linked-list: get
814 * the next pointer from the MSI-X entry and set that in the MSI
815 * capability entry (which is the previous entry). This way the MSI-X
816 * entry is skipped (left out of the linked-list) and not advertised.
817 */
818 cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
819 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
820
821 cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;
822
823 cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
824 ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &
825 ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;
826
827 cfg_msi |= cfg_msix_cp;
828
829 rockchip_pcie_write(rockchip, cfg_msi,
830 PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
831 }
832
833 static int rockchip_pcie_ep_probe(struct platform_device *pdev)
834 {
835 struct device *dev = &pdev->dev;
836 struct rockchip_pcie_ep *ep;
837 struct rockchip_pcie *rockchip;
838 struct pci_epc *epc;
839 int err;
840
841 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
842 if (!ep)
843 return -ENOMEM;
844
845 rockchip = &ep->rockchip;
846 rockchip->is_rc = false;
847 rockchip->dev = dev;
848 INIT_DELAYED_WORK(&ep->link_training, rockchip_pcie_ep_link_training);
849
850 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
851 if (IS_ERR(epc)) {
852 dev_err(dev, "failed to create EPC device\n");
853 return PTR_ERR(epc);
854 }
855
856 ep->epc = epc;
857 epc_set_drvdata(epc, ep);
858
859 err = rockchip_pcie_ep_get_resources(rockchip, ep);
860 if (err)
861 return err;
862
863 err = rockchip_pcie_ep_init_ob_mem(ep);
864 if (err)
865 return err;
866
867 err = rockchip_pcie_enable_clocks(rockchip);
868 if (err)
869 goto err_exit_ob_mem;
870
871 err = rockchip_pcie_init_port(rockchip);
872 if (err)
873 goto err_disable_clocks;
874
875 rockchip_pcie_ep_hide_broken_msix_cap(rockchip);
876
877 /* Only enable function 0 by default */
878 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
879
880 pci_epc_init_notify(epc);
881
882 err = rockchip_pcie_ep_setup_irq(epc);
883 if (err < 0)
884 goto err_uninit_port;
885
886 return 0;
887 err_uninit_port:
888 rockchip_pcie_deinit_phys(rockchip);
889 err_disable_clocks:
890 rockchip_pcie_disable_clocks(rockchip);
891 err_exit_ob_mem:
892 rockchip_pcie_ep_exit_ob_mem(ep);
893 return err;
894 }
895
896 static struct platform_driver rockchip_pcie_ep_driver = {
897 .driver = {
898 .name = "rockchip-pcie-ep",
899 .of_match_table = rockchip_pcie_ep_of_match,
900 },
901 .probe = rockchip_pcie_ep_probe,
902 };
903
904 builtin_platform_driver(rockchip_pcie_ep_driver);
Kernel DRM miscellaneous fixes and cross-tree changes