drivers/pinctrl/freescale/pinctrl-imx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * IMX pinmux core definitions
   4  *
   5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2012 Linaro Ltd.
   7  *
   8  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   9  */
  10
  11 #ifndef __DRIVERS_PINCTRL_IMX_H
  12 #define __DRIVERS_PINCTRL_IMX_H
  13
  14 #include <linux/pinctrl/pinmux.h>
  15
  16 struct platform_device;
  17
  18 extern struct pinmux_ops imx_pmx_ops;
  19 extern const struct dev_pm_ops imx_pinctrl_pm_ops;
  20
  21 /**
  22  * struct imx_pin_mmio - MMIO pin configurations
  23  * @mux_mode: the mux mode for this pin.
  24  * @input_reg: the select input register offset for this pin if any
  25  *      0 if no select input setting needed.
  26  * @input_val: the select input value for this pin.
  27  * @configs: the config for this pin.
  28  */
  29 struct imx_pin_mmio {
  30         unsigned int mux_mode;
  31         u16 input_reg;
  32         unsigned int input_val;
  33         unsigned long config;
  34 };
  35
  36 /**
  37  * struct imx_pin_scu - SCU pin configurations
  38  * @mux: the mux mode for this pin.
  39  * @configs: the config for this pin.
  40  */
  41 struct imx_pin_scu {
  42         unsigned int mux_mode;
  43         unsigned long config;
  44 };
  45
  46 /**
  47  * struct imx_pin - describes a single i.MX pin
  48  * @pin: the pin_id of this pin
  49  * @conf: config type of this pin, either mmio or scu
  50  */
  51 struct imx_pin {
  52         unsigned int pin;
  53         union {
  54                 struct imx_pin_mmio mmio;
  55                 struct imx_pin_scu scu;
  56         } conf;
  57 };
  58
  59 /**
  60  * struct imx_pin_reg - describe a pin reg map
  61  * @mux_reg: mux register offset
  62  * @conf_reg: config register offset
  63  */
  64 struct imx_pin_reg {
  65         s16 mux_reg;
  66         s16 conf_reg;
  67 };
  68
  69 /**
  70  * @dev: a pointer back to containing device
  71  * @base: the offset to the controller in virtual memory
  72  */
  73 struct imx_pinctrl {
  74         struct device *dev;
  75         struct pinctrl_dev *pctl;
  76         void __iomem *base;
  77         void __iomem *input_sel_base;
  78         const struct imx_pinctrl_soc_info *info;
  79         struct imx_pin_reg *pin_regs;
  80         unsigned int group_index;
  81         struct mutex mutex;
  82 };
  83
  84 struct imx_pinctrl_soc_info {
  85         const struct pinctrl_pin_desc *pins;
  86         unsigned int npins;
  87         unsigned int flags;
  88         const char *gpr_compatible;
  89
  90         /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
  91         unsigned int mux_mask;
  92         u8 mux_shift;
  93
  94         int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
  95                                   struct pinctrl_gpio_range *range,
  96                                   unsigned offset,
  97                                   bool input);
  98         int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
  99                                unsigned long *config);
 100         int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id,
 101                                unsigned long *configs, unsigned int num_configs);
 102         void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl,
 103                                       unsigned int *pin_id, struct imx_pin *pin,
 104                                       const __be32 **list_p);
 105 };
 106
 107 #define SHARE_MUX_CONF_REG      BIT(0)
 108 #define ZERO_OFFSET_VALID       BIT(1)
 109 #define IMX_USE_SCU             BIT(2)
 110
 111 #define NO_MUX          0x0
 112 #define NO_PAD          0x0
 113
 114 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
 115
 116 #define PAD_CTL_MASK(len)       ((1 << len) - 1)
 117 #define IMX_MUX_MASK    0x7
 118 #define IOMUXC_CONFIG_SION      (0x1 << 4)
 119
 120 int imx_pinctrl_probe(struct platform_device *pdev,
 121                         const struct imx_pinctrl_soc_info *info);
 122
 123 #define BM_PAD_CTL_GP_ENABLE            BIT(30)
 124 #define BM_PAD_CTL_IFMUX_ENABLE         BIT(31)
 125 #define BP_PAD_CTL_IFMUX                27
 126
 127 int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
 128 int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
 129                         unsigned long *config);
 130 int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
 131                         unsigned long *configs, unsigned num_configs);
 132 void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
 133                                unsigned int *pin_id, struct imx_pin *pin,
 134                                const __be32 **list_p);
 135 #endif /* __DRIVERS_PINCTRL_IMX_H */