drivers/pmdomain/mediatek/mt6735-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mediatek,mt6735-power-controller.h>
   8
   9 /*
  10  * MT6735 power domain support
  11  */
  12
  13 static const struct scpsys_domain_data scpsys_domain_data_mt6735[] = {
  14         [MT6735_POWER_DOMAIN_MD1] = {
  15                 .name = "md1",
  16                 .sta_mask = PWR_STATUS_MD1,
  17                 .ctl_offs = SPM_MD1_PWR_CON,
  18                 .pwr_sta_offs = SPM_PWR_STATUS,
  19                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  20                 .sram_pdn_bits = GENMASK(8, 8),
  21                 .sram_pdn_ack_bits = 0,
  22                 .bp_cfg = {
  23                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_MD1),
  24                 },
  25         },
  26         [MT6735_POWER_DOMAIN_CONN] = {
  27                 .name = "conn",
  28                 .sta_mask = PWR_STATUS_CONN,
  29                 .ctl_offs = SPM_CONN_PWR_CON,
  30                 .pwr_sta_offs = SPM_PWR_STATUS,
  31                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  32                 .sram_pdn_bits = GENMASK(8, 8),
  33                 .sram_pdn_ack_bits = 0,
  34                 .bp_cfg = {
  35                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_CONN),
  36                 },
  37         },
  38         [MT6735_POWER_DOMAIN_DIS] = {
  39                 .name = "dis",
  40                 .sta_mask = PWR_STATUS_DISP,
  41                 .ctl_offs = SPM_DIS_PWR_CON,
  42                 .pwr_sta_offs = SPM_PWR_STATUS,
  43                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  44                 .sram_pdn_bits = GENMASK(11, 8),
  45                 .sram_pdn_ack_bits = GENMASK(12, 12),
  46                 .bp_cfg = {
  47                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0),
  48                 },
  49         },
  50         [MT6735_POWER_DOMAIN_MFG] = {
  51                 .name = "mfg",
  52                 .sta_mask = PWR_STATUS_MFG,
  53                 .ctl_offs = SPM_MFG_PWR_CON,
  54                 .pwr_sta_offs = SPM_PWR_STATUS,
  55                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  56                 .sram_pdn_bits = GENMASK(11, 8),
  57                 .sram_pdn_ack_bits = GENMASK(12, 12),
  58                 .bp_cfg = {
  59                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S),
  60                 },
  61         },
  62         [MT6735_POWER_DOMAIN_ISP] = {
  63                 .name = "isp",
  64                 .sta_mask = PWR_STATUS_ISP,
  65                 .ctl_offs = SPM_ISP_PWR_CON,
  66                 .pwr_sta_offs = SPM_PWR_STATUS,
  67                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  68                 .sram_pdn_bits = GENMASK(11, 8),
  69                 .sram_pdn_ack_bits = GENMASK(13, 12),
  70         },
  71         [MT6735_POWER_DOMAIN_VDE] = {
  72                 .name = "vde",
  73                 .sta_mask = PWR_STATUS_VDEC,
  74                 .ctl_offs = SPM_VDE_PWR_CON,
  75                 .pwr_sta_offs = SPM_PWR_STATUS,
  76                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  77                 .sram_pdn_bits = GENMASK(11, 8),
  78                 .sram_pdn_ack_bits = GENMASK(12, 12),
  79         },
  80         [MT6735_POWER_DOMAIN_VEN] = {
  81                 .name = "ven",
  82                 .sta_mask = BIT(8),
  83                 .ctl_offs = SPM_VEN_PWR_CON,
  84                 .pwr_sta_offs = SPM_PWR_STATUS,
  85                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  86                 .sram_pdn_bits = GENMASK(11, 8),
  87                 .sram_pdn_ack_bits = GENMASK(15, 12),
  88         },
  89 };
  90
  91 static const struct scpsys_soc_data mt6735_scpsys_data = {
  92         .domains_data = scpsys_domain_data_mt6735,
  93         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6735),
  94 };
  95
  96 #endif /* __SOC_MEDIATEK_MT6735_PM_DOMAINS_H */