include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *  Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
   7  *
   8  *  Michal Simek <michal.simek@amd.com>
   9  *  Davorin Mista <davorin.mista@aggios.com>
  10  *  Jolly Shah <jollys@xilinx.com>
  11  *  Rajan Vaja <rajanv@xilinx.com>
  12  */
  13
  14 #ifndef __FIRMWARE_ZYNQMP_H__
  15 #define __FIRMWARE_ZYNQMP_H__
  16 #include <linux/types.h>
  17
  18 #include <linux/err.h>
  19
  20 #define ZYNQMP_PM_VERSION_MAJOR 1
  21 #define ZYNQMP_PM_VERSION_MINOR 0
  22
  23 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  24                                         ZYNQMP_PM_VERSION_MINOR)
  25
  26 #define ZYNQMP_TZ_VERSION_MAJOR 1
  27 #define ZYNQMP_TZ_VERSION_MINOR 0
  28
  29 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  30                                         ZYNQMP_TZ_VERSION_MINOR)
  31
  32 /* SMC SIP service Call Function Identifier Prefix */
  33 #define PM_SIP_SVC                      0xC2000000
  34
  35 /* SMC function ID to get SiP SVC version */
  36 #define GET_SIP_SVC_VERSION     (0x8200ff03U)
  37
  38 /* SiP Service Calls version numbers */
  39 #define SIP_SVC_VERSION_MAJOR           (0U)
  40 #define SIP_SVC_VERSION_MINOR           (2U)
  41
  42 #define SIP_SVC_PASSTHROUGH_VERSION     ((SIP_SVC_VERSION_MAJOR << 16) | \
  43                                          SIP_SVC_VERSION_MINOR)
  44
  45 /* Fixed ID for FW specific APIs */
  46 #define PASS_THROUGH_FW_CMD_ID  GENMASK(11, 0)
  47
  48 /* PM API versions */
  49 #define PM_API_VERSION_1        1
  50 #define PM_API_VERSION_2        2
  51
  52 #define PM_PINCTRL_PARAM_SET_VERSION    2
  53
  54 #define ZYNQMP_FAMILY_CODE 0x23
  55 #define VERSAL_FAMILY_CODE 0x26
  56
  57 /* When all subfamily of platform need to support */
  58 #define ALL_SUB_FAMILY_CODE             0x00
  59 #define VERSAL_SUB_FAMILY_CODE          0x01
  60 #define VERSALNET_SUB_FAMILY_CODE       0x03
  61
  62 #define FAMILY_CODE_MASK        GENMASK(27, 21)
  63 #define SUB_FAMILY_CODE_MASK    GENMASK(20, 19)
  64
  65 #define API_ID_MASK             GENMASK(7, 0)
  66 #define MODULE_ID_MASK          GENMASK(11, 8)
  67 #define PLM_MODULE_ID_MASK      GENMASK(15, 8)
  68
  69 /* Firmware feature check version mask */
  70 #define FIRMWARE_VERSION_MASK           0xFFFFU
  71
  72 /* ATF only commands */
  73 #define TF_A_PM_REGISTER_SGI            0xa04
  74 #define PM_GET_TRUSTZONE_VERSION        0xa03
  75 #define PM_SET_SUSPEND_MODE             0xa02
  76 #define GET_CALLBACK_DATA               0xa01
  77
  78 /* Number of 32bits values in payload */
  79 #define PAYLOAD_ARG_CNT 7U
  80
  81 /* Number of 64bits arguments for SMC call */
  82 #define SMC_ARG_CNT_64  8U
  83
  84 /* Number of 32bits arguments for SMC call */
  85 #define SMC_ARG_CNT_32  13U
  86
  87 /* Number of arguments for a callback */
  88 #define CB_ARG_CNT     4
  89
  90 /* Payload size (consists of callback API ID + arguments) */
  91 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  92
  93 #define ZYNQMP_PM_MAX_QOS               100U
  94
  95 #define GSS_NUM_REGS    (4)
  96
  97 /* Node capabilities */
  98 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  99 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
 100 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
 101 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
 102
 103 /* Loader commands */
 104 #define PM_LOAD_PDI     0x701
 105 #define PDI_SRC_DDR     0xF
 106
 107 /*
 108  * Firmware FPGA Manager flags
 109  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
 110  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
 111  */
 112 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
 113 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
 114
 115 /* FPGA Status Reg */
 116 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET        7U
 117 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG           0U
 118
 119 /*
 120  * Node IDs for the Error Events.
 121  */
 122 #define VERSAL_EVENT_ERROR_PMC_ERR1     (0x28100000U)
 123 #define VERSAL_EVENT_ERROR_PMC_ERR2     (0x28104000U)
 124 #define VERSAL_EVENT_ERROR_PSM_ERR1     (0x28108000U)
 125 #define VERSAL_EVENT_ERROR_PSM_ERR2     (0x2810C000U)
 126
 127 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U)
 128 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U)
 129 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U)
 130 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U)
 131 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U)
 132 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U)
 133 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U)
 134
 135 /* ZynqMP SD tap delay tuning */
 136 #define SD_ITAPDLY      0xFF180314
 137 #define SD_OTAPDLYSEL   0xFF180318
 138
 139 /**
 140  * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error.
 141  */
 142 #define XPM_EVENT_ERROR_MASK_DDRMC_CR           BIT(18)
 143
 144 /**
 145  * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
 146  */
 147 #define XPM_EVENT_ERROR_MASK_DDRMC_NCR          BIT(19)
 148 #define XPM_EVENT_ERROR_MASK_NOC_NCR            BIT(13)
 149 #define XPM_EVENT_ERROR_MASK_NOC_CR             BIT(12)
 150
 151 enum pm_module_id {
 152         PM_MODULE_ID = 0x0,
 153         XPM_MODULE_ID = 0x2,
 154         XSEM_MODULE_ID = 0x3,
 155         TF_A_MODULE_ID = 0xa,
 156 };
 157
 158 enum pm_api_cb_id {
 159         PM_INIT_SUSPEND_CB = 30,
 160         PM_ACKNOWLEDGE_CB = 31,
 161         PM_NOTIFY_CB = 32,
 162 };
 163
 164 enum pm_api_id {
 165         PM_API_FEATURES = 0,
 166         PM_GET_API_VERSION = 1,
 167         PM_REGISTER_NOTIFIER = 5,
 168         PM_FORCE_POWERDOWN = 8,
 169         PM_REQUEST_WAKEUP = 10,
 170         PM_SYSTEM_SHUTDOWN = 12,
 171         PM_REQUEST_NODE = 13,
 172         PM_RELEASE_NODE = 14,
 173         PM_SET_REQUIREMENT = 15,
 174         PM_RESET_ASSERT = 17,
 175         PM_RESET_GET_STATUS = 18,
 176         PM_MMIO_WRITE = 19,
 177         PM_MMIO_READ = 20,
 178         PM_PM_INIT_FINALIZE = 21,
 179         PM_FPGA_LOAD = 22,
 180         PM_FPGA_GET_STATUS = 23,
 181         PM_GET_CHIPID = 24,
 182         PM_SECURE_SHA = 26,
 183         PM_PINCTRL_REQUEST = 28,
 184         PM_PINCTRL_RELEASE = 29,
 185         PM_PINCTRL_SET_FUNCTION = 31,
 186         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 187         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 188         PM_IOCTL = 34,
 189         PM_QUERY_DATA = 35,
 190         PM_CLOCK_ENABLE = 36,
 191         PM_CLOCK_DISABLE = 37,
 192         PM_CLOCK_GETSTATE = 38,
 193         PM_CLOCK_SETDIVIDER = 39,
 194         PM_CLOCK_GETDIVIDER = 40,
 195         PM_CLOCK_SETPARENT = 43,
 196         PM_CLOCK_GETPARENT = 44,
 197         PM_FPGA_READ = 46,
 198         PM_SECURE_AES = 47,
 199         PM_EFUSE_ACCESS = 53,
 200         PM_FEATURE_CHECK = 63,
 201 };
 202
 203 /* PMU-FW return status codes */
 204 enum pm_ret_status {
 205         XST_PM_SUCCESS = 0,
 206         XST_PM_INVALID_VERSION = 4,
 207         XST_PM_NO_FEATURE = 19,
 208         XST_PM_INVALID_CRC = 301,
 209         XST_PM_INTERNAL = 2000,
 210         XST_PM_CONFLICT = 2001,
 211         XST_PM_NO_ACCESS = 2002,
 212         XST_PM_INVALID_NODE = 2003,
 213         XST_PM_DOUBLE_REQ = 2004,
 214         XST_PM_ABORT_SUSPEND = 2005,
 215         XST_PM_MULT_USER = 2008,
 216 };
 217
 218 enum pm_ioctl_id {
 219         IOCTL_GET_RPU_OPER_MODE = 0,
 220         IOCTL_SET_RPU_OPER_MODE = 1,
 221         IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
 222         IOCTL_TCM_COMB_CONFIG = 3,
 223         IOCTL_SET_TAPDELAY_BYPASS = 4,
 224         IOCTL_SD_DLL_RESET = 6,
 225         IOCTL_SET_SD_TAPDELAY = 7,
 226         IOCTL_SET_PLL_FRAC_MODE = 8,
 227         IOCTL_GET_PLL_FRAC_MODE = 9,
 228         IOCTL_SET_PLL_FRAC_DATA = 10,
 229         IOCTL_GET_PLL_FRAC_DATA = 11,
 230         IOCTL_WRITE_GGS = 12,
 231         IOCTL_READ_GGS = 13,
 232         IOCTL_WRITE_PGGS = 14,
 233         IOCTL_READ_PGGS = 15,
 234         /* Set healthy bit value */
 235         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 236         IOCTL_OSPI_MUX_SELECT = 21,
 237         /* Register SGI to ATF */
 238         IOCTL_REGISTER_SGI = 25,
 239         /* Runtime feature configuration */
 240         IOCTL_SET_FEATURE_CONFIG = 26,
 241         IOCTL_GET_FEATURE_CONFIG = 27,
 242         /* IOCTL for Secure Read/Write Interface */
 243         IOCTL_READ_REG = 28,
 244         /* Dynamic SD/GEM configuration */
 245         IOCTL_SET_SD_CONFIG = 30,
 246         IOCTL_SET_GEM_CONFIG = 31,
 247         /* IOCTL to get default/current QoS */
 248         IOCTL_GET_QOS = 34,
 249 };
 250
 251 enum pm_query_id {
 252         PM_QID_INVALID = 0,
 253         PM_QID_CLOCK_GET_NAME = 1,
 254         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 255         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 256         PM_QID_CLOCK_GET_PARENTS = 4,
 257         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 258         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 259         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 260         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 261         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 262         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 263         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 264         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 265         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 266         PM_QID_PINCTRL_GET_ATTRIBUTES = 15,
 267 };
 268
 269 enum rpu_oper_mode {
 270         PM_RPU_MODE_LOCKSTEP = 0,
 271         PM_RPU_MODE_SPLIT = 1,
 272 };
 273
 274 enum rpu_boot_mem {
 275         PM_RPU_BOOTMEM_LOVEC = 0,
 276         PM_RPU_BOOTMEM_HIVEC = 1,
 277 };
 278
 279 enum rpu_tcm_comb {
 280         PM_RPU_TCM_SPLIT = 0,
 281         PM_RPU_TCM_COMB = 1,
 282 };
 283
 284 enum zynqmp_pm_reset_action {
 285         PM_RESET_ACTION_RELEASE = 0,
 286         PM_RESET_ACTION_ASSERT = 1,
 287         PM_RESET_ACTION_PULSE = 2,
 288 };
 289
 290 enum zynqmp_pm_reset {
 291         ZYNQMP_PM_RESET_START = 1000,
 292         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 293         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 294         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 295         ZYNQMP_PM_RESET_DP = 1003,
 296         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 297         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 298         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 299         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 300         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 301         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 302         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 303         ZYNQMP_PM_RESET_GDMA = 1011,
 304         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 305         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 306         ZYNQMP_PM_RESET_GPU = 1014,
 307         ZYNQMP_PM_RESET_GT = 1015,
 308         ZYNQMP_PM_RESET_SATA = 1016,
 309         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 310         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 311         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 312         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 313         ZYNQMP_PM_RESET_APU_L2 = 1021,
 314         ZYNQMP_PM_RESET_ACPU3 = 1022,
 315         ZYNQMP_PM_RESET_ACPU2 = 1023,
 316         ZYNQMP_PM_RESET_ACPU1 = 1024,
 317         ZYNQMP_PM_RESET_ACPU0 = 1025,
 318         ZYNQMP_PM_RESET_DDR = 1026,
 319         ZYNQMP_PM_RESET_APM_FPD = 1027,
 320         ZYNQMP_PM_RESET_SOFT = 1028,
 321         ZYNQMP_PM_RESET_GEM0 = 1029,
 322         ZYNQMP_PM_RESET_GEM1 = 1030,
 323         ZYNQMP_PM_RESET_GEM2 = 1031,
 324         ZYNQMP_PM_RESET_GEM3 = 1032,
 325         ZYNQMP_PM_RESET_QSPI = 1033,
 326         ZYNQMP_PM_RESET_UART0 = 1034,
 327         ZYNQMP_PM_RESET_UART1 = 1035,
 328         ZYNQMP_PM_RESET_SPI0 = 1036,
 329         ZYNQMP_PM_RESET_SPI1 = 1037,
 330         ZYNQMP_PM_RESET_SDIO0 = 1038,
 331         ZYNQMP_PM_RESET_SDIO1 = 1039,
 332         ZYNQMP_PM_RESET_CAN0 = 1040,
 333         ZYNQMP_PM_RESET_CAN1 = 1041,
 334         ZYNQMP_PM_RESET_I2C0 = 1042,
 335         ZYNQMP_PM_RESET_I2C1 = 1043,
 336         ZYNQMP_PM_RESET_TTC0 = 1044,
 337         ZYNQMP_PM_RESET_TTC1 = 1045,
 338         ZYNQMP_PM_RESET_TTC2 = 1046,
 339         ZYNQMP_PM_RESET_TTC3 = 1047,
 340         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 341         ZYNQMP_PM_RESET_NAND = 1049,
 342         ZYNQMP_PM_RESET_ADMA = 1050,
 343         ZYNQMP_PM_RESET_GPIO = 1051,
 344         ZYNQMP_PM_RESET_IOU_CC = 1052,
 345         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 346         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 347         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 348         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 349         ZYNQMP_PM_RESET_OCM = 1057,
 350         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 351         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 352         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 353         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 354         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 355         ZYNQMP_PM_RESET_USB0_APB = 1063,
 356         ZYNQMP_PM_RESET_USB1_APB = 1064,
 357         ZYNQMP_PM_RESET_IPI = 1065,
 358         ZYNQMP_PM_RESET_APM_LPD = 1066,
 359         ZYNQMP_PM_RESET_RTC = 1067,
 360         ZYNQMP_PM_RESET_SYSMON = 1068,
 361         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 362         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 363         ZYNQMP_PM_RESET_FPD = 1071,
 364         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 365         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 366         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 367         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 368         ZYNQMP_PM_RESET_APLL = 1076,
 369         ZYNQMP_PM_RESET_DPLL = 1077,
 370         ZYNQMP_PM_RESET_VPLL = 1078,
 371         ZYNQMP_PM_RESET_IOPLL = 1079,
 372         ZYNQMP_PM_RESET_RPLL = 1080,
 373         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 374         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 375         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 376         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 377         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 378         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 379         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 380         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 381         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 382         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 383         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 384         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 385         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 386         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 387         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 388         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 389         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 390         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 391         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 392         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 393         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 394         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 395         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 396         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 397         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 398         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 399         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 400         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 401         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 402         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 403         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 404         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 405         ZYNQMP_PM_RESET_RPU_LS = 1113,
 406         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 407         ZYNQMP_PM_RESET_PL = 1115,
 408         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 409         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 410         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 411         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 412         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 413 };
 414
 415 enum zynqmp_pm_suspend_reason {
 416         SUSPEND_POWER_REQUEST = 201,
 417         SUSPEND_ALERT = 202,
 418         SUSPEND_SYSTEM_SHUTDOWN = 203,
 419 };
 420
 421 enum zynqmp_pm_request_ack {
 422         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 423         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 424         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 425 };
 426
 427 enum pm_node_id {
 428         NODE_SD_0 = 39,
 429         NODE_SD_1 = 40,
 430 };
 431
 432 enum tap_delay_type {
 433         PM_TAPDELAY_INPUT = 0,
 434         PM_TAPDELAY_OUTPUT = 1,
 435 };
 436
 437 enum dll_reset_type {
 438         PM_DLL_RESET_ASSERT = 0,
 439         PM_DLL_RESET_RELEASE = 1,
 440         PM_DLL_RESET_PULSE = 2,
 441 };
 442
 443 enum pm_pinctrl_config_param {
 444         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 445         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 446         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 447         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 448         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 449         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 450         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 451         PM_PINCTRL_CONFIG_MAX = 7,
 452 };
 453
 454 enum pm_pinctrl_slew_rate {
 455         PM_PINCTRL_SLEW_RATE_FAST = 0,
 456         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 457 };
 458
 459 enum pm_pinctrl_bias_status {
 460         PM_PINCTRL_BIAS_DISABLE = 0,
 461         PM_PINCTRL_BIAS_ENABLE = 1,
 462 };
 463
 464 enum pm_pinctrl_pull_ctrl {
 465         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 466         PM_PINCTRL_BIAS_PULL_UP = 1,
 467 };
 468
 469 enum pm_pinctrl_schmitt_cmos {
 470         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 471         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 472 };
 473
 474 enum pm_pinctrl_drive_strength {
 475         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 476         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 477         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 478         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 479 };
 480
 481 enum pm_pinctrl_tri_state {
 482         PM_PINCTRL_TRI_STATE_DISABLE = 0,
 483         PM_PINCTRL_TRI_STATE_ENABLE = 1,
 484 };
 485
 486 enum zynqmp_pm_shutdown_type {
 487         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 488         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 489         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 490 };
 491
 492 enum zynqmp_pm_shutdown_subtype {
 493         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 494         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 495         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 496 };
 497
 498 enum tap_delay_signal_type {
 499         PM_TAPDELAY_NAND_DQS_IN = 0,
 500         PM_TAPDELAY_NAND_DQS_OUT = 1,
 501         PM_TAPDELAY_QSPI = 2,
 502         PM_TAPDELAY_MAX = 3,
 503 };
 504
 505 enum tap_delay_bypass_ctrl {
 506         PM_TAPDELAY_BYPASS_DISABLE = 0,
 507         PM_TAPDELAY_BYPASS_ENABLE = 1,
 508 };
 509
 510 enum ospi_mux_select_type {
 511         PM_OSPI_MUX_SEL_DMA = 0,
 512         PM_OSPI_MUX_SEL_LINEAR = 1,
 513 };
 514
 515 enum pm_feature_config_id {
 516         PM_FEATURE_INVALID = 0,
 517         PM_FEATURE_OVERTEMP_STATUS = 1,
 518         PM_FEATURE_OVERTEMP_VALUE = 2,
 519         PM_FEATURE_EXTWDT_STATUS = 3,
 520         PM_FEATURE_EXTWDT_VALUE = 4,
 521 };
 522
 523 /**
 524  * enum pm_sd_config_type - PM SD configuration.
 525  * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
 526  * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
 527  * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
 528  * @SD_CONFIG_FIXED: To set fixed config registers
 529  */
 530 enum pm_sd_config_type {
 531         SD_CONFIG_EMMC_SEL = 1,
 532         SD_CONFIG_BASECLK = 2,
 533         SD_CONFIG_8BIT = 3,
 534         SD_CONFIG_FIXED = 4,
 535 };
 536
 537 /**
 538  * enum pm_gem_config_type - PM GEM configuration.
 539  * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
 540  * @GEM_CONFIG_FIXED: To set fixed config registers
 541  */
 542 enum pm_gem_config_type {
 543         GEM_CONFIG_SGMII_MODE = 1,
 544         GEM_CONFIG_FIXED = 2,
 545 };
 546
 547 /**
 548  * struct zynqmp_pm_query_data - PM query data
 549  * @qid:        query ID
 550  * @arg1:       Argument 1 of query data
 551  * @arg2:       Argument 2 of query data
 552  * @arg3:       Argument 3 of query data
 553  */
 554 struct zynqmp_pm_query_data {
 555         u32 qid;
 556         u32 arg1;
 557         u32 arg2;
 558         u32 arg3;
 559 };
 560
 561 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...);
 562 int zynqmp_pm_invoke_fw_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...);
 563
 564 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 565 int zynqmp_pm_get_api_version(u32 *version);
 566 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 567 int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily);
 568 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 569 int zynqmp_pm_clock_enable(u32 clock_id);
 570 int zynqmp_pm_clock_disable(u32 clock_id);
 571 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 572 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 573 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 574 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 575 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 576 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 577 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 578 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 579 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 580 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 581 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 582 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 583 int zynqmp_pm_reset_assert(const u32 reset,
 584                            const enum zynqmp_pm_reset_action assert_flag);
 585 int zynqmp_pm_reset_get_status(const u32 reset, u32 *status);
 586 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 587 int zynqmp_pm_bootmode_write(u32 ps_mode);
 588 int zynqmp_pm_init_finalize(void);
 589 int zynqmp_pm_set_suspend_mode(u32 mode);
 590 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 591                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 592 int zynqmp_pm_release_node(const u32 node);
 593 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 594                               const u32 qos,
 595                               const enum zynqmp_pm_request_ack ack);
 596 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 597 int zynqmp_pm_efuse_access(const u64 address, u32 *out);
 598 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 599 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 600 int zynqmp_pm_fpga_get_status(u32 *value);
 601 int zynqmp_pm_fpga_get_config_status(u32 *value);
 602 int zynqmp_pm_write_ggs(u32 index, u32 value);
 603 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 604 int zynqmp_pm_write_pggs(u32 index, u32 value);
 605 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 606 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 607 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 608 int zynqmp_pm_set_boot_health_status(u32 value);
 609 int zynqmp_pm_pinctrl_request(const u32 pin);
 610 int zynqmp_pm_pinctrl_release(const u32 pin);
 611 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 612 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 613                                  u32 *value);
 614 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 615                                  u32 value);
 616 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 617 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 618                                 const u32 wake, const u32 enable);
 619 int zynqmp_pm_feature(const u32 api_id);
 620 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 621 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 622 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 623 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
 624 int zynqmp_pm_force_pwrdwn(const u32 target,
 625                            const enum zynqmp_pm_request_ack ack);
 626 int zynqmp_pm_request_wake(const u32 node,
 627                            const bool set_addr,
 628                            const u64 address,
 629                            const enum zynqmp_pm_request_ack ack);
 630 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
 631 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
 632 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
 633 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 634 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 635                              u32 value);
 636 #else
 637 static inline int zynqmp_pm_get_api_version(u32 *version)
 638 {
 639         return -ENODEV;
 640 }
 641
 642 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 643 {
 644         return -ENODEV;
 645 }
 646
 647 static inline int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)
 648 {
 649         return -ENODEV;
 650 }
 651
 652 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 653                                        u32 *out)
 654 {
 655         return -ENODEV;
 656 }
 657
 658 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 659 {
 660         return -ENODEV;
 661 }
 662
 663 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 664 {
 665         return -ENODEV;
 666 }
 667
 668 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 669 {
 670         return -ENODEV;
 671 }
 672
 673 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 674 {
 675         return -ENODEV;
 676 }
 677
 678 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 679 {
 680         return -ENODEV;
 681 }
 682
 683 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 684 {
 685         return -ENODEV;
 686 }
 687
 688 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 689 {
 690         return -ENODEV;
 691 }
 692
 693 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 694 {
 695         return -ENODEV;
 696 }
 697
 698 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 699 {
 700         return -ENODEV;
 701 }
 702
 703 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 704 {
 705         return -ENODEV;
 706 }
 707
 708 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 709 {
 710         return -ENODEV;
 711 }
 712
 713 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 714 {
 715         return -ENODEV;
 716 }
 717
 718 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 719 {
 720         return -ENODEV;
 721 }
 722
 723 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 724 {
 725         return -ENODEV;
 726 }
 727
 728 static inline int zynqmp_pm_reset_assert(const u32 reset,
 729                                          const enum zynqmp_pm_reset_action assert_flag)
 730 {
 731         return -ENODEV;
 732 }
 733
 734 static inline int zynqmp_pm_reset_get_status(const u32 reset, u32 *status)
 735 {
 736         return -ENODEV;
 737 }
 738
 739 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 740 {
 741         return -ENODEV;
 742 }
 743
 744 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 745 {
 746         return -ENODEV;
 747 }
 748
 749 static inline int zynqmp_pm_init_finalize(void)
 750 {
 751         return -ENODEV;
 752 }
 753
 754 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 755 {
 756         return -ENODEV;
 757 }
 758
 759 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 760                                          const u32 qos,
 761                                          const enum zynqmp_pm_request_ack ack)
 762 {
 763         return -ENODEV;
 764 }
 765
 766 static inline int zynqmp_pm_release_node(const u32 node)
 767 {
 768         return -ENODEV;
 769 }
 770
 771 static inline int zynqmp_pm_set_requirement(const u32 node,
 772                                             const u32 capabilities,
 773                                             const u32 qos,
 774                                             const enum zynqmp_pm_request_ack ack)
 775 {
 776         return -ENODEV;
 777 }
 778
 779 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 780 {
 781         return -ENODEV;
 782 }
 783
 784 static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
 785 {
 786         return -ENODEV;
 787 }
 788
 789 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 790                                      const u32 flags)
 791 {
 792         return -ENODEV;
 793 }
 794
 795 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 796                                       const u32 flags)
 797 {
 798         return -ENODEV;
 799 }
 800
 801 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 802 {
 803         return -ENODEV;
 804 }
 805
 806 static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
 807 {
 808         return -ENODEV;
 809 }
 810
 811 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 812 {
 813         return -ENODEV;
 814 }
 815
 816 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 817 {
 818         return -ENODEV;
 819 }
 820
 821 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 822 {
 823         return -ENODEV;
 824 }
 825
 826 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 827 {
 828         return -ENODEV;
 829 }
 830
 831 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
 832 {
 833         return -ENODEV;
 834 }
 835
 836 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 837 {
 838         return -ENODEV;
 839 }
 840
 841 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 842 {
 843         return -ENODEV;
 844 }
 845
 846 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 847 {
 848         return -ENODEV;
 849 }
 850
 851 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 852 {
 853         return -ENODEV;
 854 }
 855
 856 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 857 {
 858         return -ENODEV;
 859 }
 860
 861 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 862 {
 863         return -ENODEV;
 864 }
 865
 866 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 867                                                u32 *value)
 868 {
 869         return -ENODEV;
 870 }
 871
 872 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 873                                                u32 value)
 874 {
 875         return -ENODEV;
 876 }
 877
 878 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 879 {
 880         return -ENODEV;
 881 }
 882
 883 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 884                                               const u32 wake, const u32 enable)
 885 {
 886         return -ENODEV;
 887 }
 888
 889 static inline int zynqmp_pm_feature(const u32 api_id)
 890 {
 891         return -ENODEV;
 892 }
 893
 894 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 895                                                u32 value)
 896 {
 897         return -ENODEV;
 898 }
 899
 900 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 901                                                u32 *payload)
 902 {
 903         return -ENODEV;
 904 }
 905
 906 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 907 {
 908         return -ENODEV;
 909 }
 910
 911 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
 912                                          const enum zynqmp_pm_request_ack ack)
 913 {
 914         return -ENODEV;
 915 }
 916
 917 static inline int zynqmp_pm_request_wake(const u32 node,
 918                                          const bool set_addr,
 919                                          const u64 address,
 920                                          const enum zynqmp_pm_request_ack ack)
 921 {
 922         return -ENODEV;
 923 }
 924
 925 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
 926 {
 927         return -ENODEV;
 928 }
 929
 930 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
 931 {
 932         return -ENODEV;
 933 }
 934
 935 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
 936 {
 937         return -ENODEV;
 938 }
 939
 940 static inline int zynqmp_pm_set_sd_config(u32 node,
 941                                           enum pm_sd_config_type config,
 942                                           u32 value)
 943 {
 944         return -ENODEV;
 945 }
 946
 947 static inline int zynqmp_pm_set_gem_config(u32 node,
 948                                            enum pm_gem_config_type config,
 949                                            u32 value)
 950 {
 951         return -ENODEV;
 952 }
 953
 954 #endif
 955
 956 #endif /* __FIRMWARE_ZYNQMP_H__ */