include/linux/fsl/guts.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Freecale 85xx and 86xx Global Utilties register set
   4  *
   5  * Authors: Jeff Brown
   6  *          Timur Tabi <timur@freescale.com>
   7  *
   8  * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
   9  */
  10
  11 #ifndef __FSL_GUTS_H__
  12 #define __FSL_GUTS_H__
  13
  14 #include <linux/types.h>
  15 #include <linux/io.h>
  16
  17 /*
  18  * Global Utility Registers.
  19  *
  20  * Not all registers defined in this structure are available on all chips, so
  21  * you are expected to know whether a given register actually exists on your
  22  * chip before you access it.
  23  *
  24  * Also, some registers are similar on different chips but have slightly
  25  * different names.  In these cases, one name is chosen to avoid extraneous
  26  * #ifdefs.
  27  */
  28 struct ccsr_guts {
  29         u32     porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
  30         u32     porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
  31         u32     porimpscr;      /* 0x.0008 - POR I/O Impedance Status and
  32                                  *           Control Register
  33                                  */
  34         u32     pordevsr;       /* 0x.000c - POR I/O Device Status Register */
  35         u32     pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
  36         u32     pordevsr2;      /* 0x.0014 - POR device status register 2 */
  37         u8      res018[0x20 - 0x18];
  38         u32     porcir;         /* 0x.0020 - POR Configuration Information
  39                                  *           Register
  40                                  */
  41         u8      res024[0x30 - 0x24];
  42         u32     gpiocr;         /* 0x.0030 - GPIO Control Register */
  43         u8      res034[0x40 - 0x34];
  44         u32     gpoutdr;        /* 0x.0040 - General-Purpose Output Data
  45                                  *           Register
  46                                  */
  47         u8      res044[0x50 - 0x44];
  48         u32     gpindr;         /* 0x.0050 - General-Purpose Input Data
  49                                  *           Register
  50                                  */
  51         u8      res054[0x60 - 0x54];
  52         u32     pmuxcr;         /* 0x.0060 - Alternate Function Signal
  53                                  *           Multiplex Control
  54                                  */
  55         u32     pmuxcr2;        /* 0x.0064 - Alternate function signal
  56                                  *           multiplex control 2
  57                                  */
  58         u32     dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
  59         u8      res06c[0x70 - 0x6c];
  60         u32     devdisr;        /* 0x.0070 - Device Disable Control */
  61 #define CCSR_GUTS_DEVDISR_TB1   0x00001000
  62 #define CCSR_GUTS_DEVDISR_TB0   0x00004000
  63         u32     devdisr2;       /* 0x.0074 - Device Disable Control 2 */
  64         u8      res078[0x7c - 0x78];
  65         u32     pmjcr;          /* 0x.007c - 4 Power Management Jog Control
  66                                  *           Register
  67                                  */
  68         u32     powmgtcsr;      /* 0x.0080 - Power Management Status and
  69                                  *           Control Register
  70                                  */
  71         u32     pmrccr;         /* 0x.0084 - Power Management Reset Counter
  72                                  *           Configuration Register
  73                                  */
  74         u32     pmpdccr;        /* 0x.0088 - Power Management Power Down Counter
  75                                  *           Configuration Register
  76                                  */
  77         u32     pmcdr;          /* 0x.008c - 4Power management clock disable
  78                                  *           register
  79                                  */
  80         u32     mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
  81         u32     rstrscr;        /* 0x.0094 - Reset Request Status and
  82                                  *           Control Register
  83                                  */
  84         u32     ectrstcr;       /* 0x.0098 - Exception reset control register */
  85         u32     autorstsr;      /* 0x.009c - Automatic reset status register */
  86         u32     pvr;            /* 0x.00a0 - Processor Version Register */
  87         u32     svr;            /* 0x.00a4 - System Version Register */
  88         u8      res0a8[0xb0 - 0xa8];
  89         u32     rstcr;          /* 0x.00b0 - Reset Control Register */
  90         u8      res0b4[0xc0 - 0xb4];
  91         u32     iovselsr;       /* 0x.00c0 - I/O voltage select status register
  92                                              Called 'elbcvselcr' on 86xx SOCs */
  93         u8      res0c4[0x100 - 0xc4];
  94         u32     rcwsr[16];      /* 0x.0100 - Reset Control Word Status registers
  95                                              There are 16 registers */
  96         u8      res140[0x224 - 0x140];
  97         u32     iodelay1;       /* 0x.0224 - IO delay control register 1 */
  98         u32     iodelay2;       /* 0x.0228 - IO delay control register 2 */
  99         u8      res22c[0x604 - 0x22c];
 100         u32     pamubypenr;     /* 0x.604 - PAMU bypass enable register */
 101         u8      res608[0x800 - 0x608];
 102         u32     clkdvdr;        /* 0x.0800 - Clock Divide Register */
 103         u8      res804[0x900 - 0x804];
 104         u32     ircr;           /* 0x.0900 - Infrared Control Register */
 105         u8      res904[0x908 - 0x904];
 106         u32     dmacr;          /* 0x.0908 - DMA Control Register */
 107         u8      res90c[0x914 - 0x90c];
 108         u32     elbccr;         /* 0x.0914 - eLBC Control Register */
 109         u8      res918[0xb20 - 0x918];
 110         u32     ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
 111         u32     ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
 112         u32     ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
 113         u8      resb2c[0xe00 - 0xb2c];
 114         u32     clkocr;         /* 0x.0e00 - Clock Out Select Register */
 115         u8      rese04[0xe10 - 0xe04];
 116         u32     ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
 117         u8      rese14[0xe20 - 0xe14];
 118         u32     lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
 119         u32     cpfor;          /* 0x.0e24 - L2 charge pump fuse override
 120                                  *           register
 121                                  */
 122         u8      rese28[0xf04 - 0xe28];
 123         u32     srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
 124         u32     srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
 125         u8      resf0c[0xf2c - 0xf0c];
 126         u32     itcr;           /* 0x.0f2c - Internal transaction control
 127                                  *           register
 128                                  */
 129         u8      resf30[0xf40 - 0xf30];
 130         u32     srds2cr0;       /* 0x.0f40 - SerDes2 Control Register 0 */
 131         u32     srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
 132 } __attribute__ ((packed));
 133
 134 /* Alternate function signal multiplex control */
 135 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
 136
 137 #ifdef CONFIG_PPC_86xx
 138
 139 #define CCSR_GUTS_DMACR_DEV_SSI 0       /* DMA controller/channel set to SSI */
 140 #define CCSR_GUTS_DMACR_DEV_IR  1       /* DMA controller/channel set to IR */
 141
 142 /*
 143  * Set the DMACR register in the GUTS
 144  *
 145  * The DMACR register determines the source of initiated transfers for each
 146  * channel on each DMA controller.  Rather than have a bunch of repetitive
 147  * macros for the bit patterns, we just have a function that calculates
 148  * them.
 149  *
 150  * guts: Pointer to GUTS structure
 151  * co: The DMA controller (0 or 1)
 152  * ch: The channel on the DMA controller (0, 1, 2, or 3)
 153  * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
 154  */
 155 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
 156         unsigned int co, unsigned int ch, unsigned int device)
 157 {
 158         unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
 159
 160         clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
 161 }
 162
 163 #define CCSR_GUTS_PMUXCR_LDPSEL         0x00010000
 164 #define CCSR_GUTS_PMUXCR_SSI1_MASK      0x0000C000      /* Bitmask for SSI1 */
 165 #define CCSR_GUTS_PMUXCR_SSI1_LA        0x00000000      /* Latched address */
 166 #define CCSR_GUTS_PMUXCR_SSI1_HI        0x00004000      /* High impedance */
 167 #define CCSR_GUTS_PMUXCR_SSI1_SSI       0x00008000      /* Used for SSI1 */
 168 #define CCSR_GUTS_PMUXCR_SSI2_MASK      0x00003000      /* Bitmask for SSI2 */
 169 #define CCSR_GUTS_PMUXCR_SSI2_LA        0x00000000      /* Latched address */
 170 #define CCSR_GUTS_PMUXCR_SSI2_HI        0x00001000      /* High impedance */
 171 #define CCSR_GUTS_PMUXCR_SSI2_SSI       0x00002000      /* Used for SSI2 */
 172 #define CCSR_GUTS_PMUXCR_LA_22_25_LA    0x00000000      /* Latched Address */
 173 #define CCSR_GUTS_PMUXCR_LA_22_25_HI    0x00000400      /* High impedance */
 174 #define CCSR_GUTS_PMUXCR_DBGDRV         0x00000200      /* Signals not driven */
 175 #define CCSR_GUTS_PMUXCR_DMA2_0         0x00000008
 176 #define CCSR_GUTS_PMUXCR_DMA2_3         0x00000004
 177 #define CCSR_GUTS_PMUXCR_DMA1_0         0x00000002
 178 #define CCSR_GUTS_PMUXCR_DMA1_3         0x00000001
 179
 180 /*
 181  * Set the DMA external control bits in the GUTS
 182  *
 183  * The DMA external control bits in the PMUXCR are only meaningful for
 184  * channels 0 and 3.  Any other channels are ignored.
 185  *
 186  * guts: Pointer to GUTS structure
 187  * co: The DMA controller (0 or 1)
 188  * ch: The channel on the DMA controller (0, 1, 2, or 3)
 189  * value: the new value for the bit (0 or 1)
 190  */
 191 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
 192         unsigned int co, unsigned int ch, unsigned int value)
 193 {
 194         if ((ch == 0) || (ch == 3)) {
 195                 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
 196
 197                 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
 198         }
 199 }
 200
 201 #define CCSR_GUTS_CLKDVDR_PXCKEN        0x80000000
 202 #define CCSR_GUTS_CLKDVDR_SSICKEN       0x20000000
 203 #define CCSR_GUTS_CLKDVDR_PXCKINV       0x10000000
 204 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
 205 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK  0x06000000
 206 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
 207         (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
 208 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT   16
 209 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK    0x001F0000
 210 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
 211 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK   0x000000FF
 212 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
 213
 214 #endif
 215
 216 struct ccsr_rcpm_v1 {
 217         u8      res0000[4];
 218         __be32  cdozsr;     /* 0x0004 Core Doze Status Register */
 219         u8      res0008[4];
 220         __be32  cdozcr;     /* 0x000c Core Doze Control Register */
 221         u8      res0010[4];
 222         __be32  cnapsr;     /* 0x0014 Core Nap Status Register */
 223         u8      res0018[4];
 224         __be32  cnapcr;     /* 0x001c Core Nap Control Register */
 225         u8      res0020[4];
 226         __be32  cdozpsr;    /* 0x0024 Core Doze Previous Status Register */
 227         u8      res0028[4];
 228         __be32  cnappsr;    /* 0x002c Core Nap Previous Status Register */
 229         u8      res0030[4];
 230         __be32  cwaitsr;    /* 0x0034 Core Wait Status Register */
 231         u8      res0038[4];
 232         __be32  cwdtdsr;    /* 0x003c Core Watchdog Detect Status Register */
 233         __be32  powmgtcsr;  /* 0x0040 PM Control&Status Register */
 234 #define RCPM_POWMGTCSR_SLP      0x00020000
 235         u8      res0044[12];
 236         __be32  ippdexpcr;  /* 0x0050 IP Powerdown Exception Control Register */
 237         u8      res0054[16];
 238         __be32  cpmimr;     /* 0x0064 Core PM IRQ Mask Register */
 239         u8      res0068[4];
 240         __be32  cpmcimr;    /* 0x006c Core PM Critical IRQ Mask Register */
 241         u8      res0070[4];
 242         __be32  cpmmcmr;    /* 0x0074 Core PM Machine Check Mask Register */
 243         u8      res0078[4];
 244         __be32  cpmnmimr;   /* 0x007c Core PM NMI Mask Register */
 245         u8      res0080[4];
 246         __be32  ctbenr;     /* 0x0084 Core Time Base Enable Register */
 247         u8      res0088[4];
 248         __be32  ctbckselr;  /* 0x008c Core Time Base Clock Select Register */
 249         u8      res0090[4];
 250         __be32  ctbhltcr;   /* 0x0094 Core Time Base Halt Control Register */
 251         u8      res0098[4];
 252         __be32  cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
 253 };
 254
 255 struct ccsr_rcpm_v2 {
 256         u8      res_00[12];
 257         __be32  tph10sr0;       /* Thread PH10 Status Register */
 258         u8      res_10[12];
 259         __be32  tph10setr0;     /* Thread PH10 Set Control Register */
 260         u8      res_20[12];
 261         __be32  tph10clrr0;     /* Thread PH10 Clear Control Register */
 262         u8      res_30[12];
 263         __be32  tph10psr0;      /* Thread PH10 Previous Status Register */
 264         u8      res_40[12];
 265         __be32  twaitsr0;       /* Thread Wait Status Register */
 266         u8      res_50[96];
 267         __be32  pcph15sr;       /* Physical Core PH15 Status Register */
 268         __be32  pcph15setr;     /* Physical Core PH15 Set Control Register */
 269         __be32  pcph15clrr;     /* Physical Core PH15 Clear Control Register */
 270         __be32  pcph15psr;      /* Physical Core PH15 Prev Status Register */
 271         u8      res_c0[16];
 272         __be32  pcph20sr;       /* Physical Core PH20 Status Register */
 273         __be32  pcph20setr;     /* Physical Core PH20 Set Control Register */
 274         __be32  pcph20clrr;     /* Physical Core PH20 Clear Control Register */
 275         __be32  pcph20psr;      /* Physical Core PH20 Prev Status Register */
 276         __be32  pcpw20sr;       /* Physical Core PW20 Status Register */
 277         u8      res_e0[12];
 278         __be32  pcph30sr;       /* Physical Core PH30 Status Register */
 279         __be32  pcph30setr;     /* Physical Core PH30 Set Control Register */
 280         __be32  pcph30clrr;     /* Physical Core PH30 Clear Control Register */
 281         __be32  pcph30psr;      /* Physical Core PH30 Prev Status Register */
 282         u8      res_100[32];
 283         __be32  ippwrgatecr;    /* IP Power Gating Control Register */
 284         u8      res_124[12];
 285         __be32  powmgtcsr;      /* Power Management Control & Status Reg */
 286 #define RCPM_POWMGTCSR_LPM20_RQ         0x00100000
 287 #define RCPM_POWMGTCSR_LPM20_ST         0x00000200
 288 #define RCPM_POWMGTCSR_P_LPM20_ST       0x00000100
 289         u8      res_134[12];
 290         __be32  ippdexpcr[4];   /* IP Powerdown Exception Control Reg */
 291         u8      res_150[12];
 292         __be32  tpmimr0;        /* Thread PM Interrupt Mask Reg */
 293         u8      res_160[12];
 294         __be32  tpmcimr0;       /* Thread PM Crit Interrupt Mask Reg */
 295         u8      res_170[12];
 296         __be32  tpmmcmr0;       /* Thread PM Machine Check Interrupt Mask Reg */
 297         u8      res_180[12];
 298         __be32  tpmnmimr0;      /* Thread PM NMI Mask Reg */
 299         u8      res_190[12];
 300         __be32  tmcpmaskcr0;    /* Thread Machine Check Mask Control Reg */
 301         __be32  pctbenr;        /* Physical Core Time Base Enable Reg */
 302         __be32  pctbclkselr;    /* Physical Core Time Base Clock Select */
 303         __be32  tbclkdivr;      /* Time Base Clock Divider Register */
 304         u8      res_1ac[4];
 305         __be32  ttbhltcr[4];    /* Thread Time Base Halt Control Register */
 306         __be32  clpcl10sr;      /* Cluster PCL10 Status Register */
 307         __be32  clpcl10setr;    /* Cluster PCL30 Set Control Register */
 308         __be32  clpcl10clrr;    /* Cluster PCL30 Clear Control Register */
 309         __be32  clpcl10psr;     /* Cluster PCL30 Prev Status Register */
 310         __be32  cddslpsetr;     /* Core Domain Deep Sleep Set Register */
 311         __be32  cddslpclrr;     /* Core Domain Deep Sleep Clear Register */
 312         __be32  cdpwroksetr;    /* Core Domain Power OK Set Register */
 313         __be32  cdpwrokclrr;    /* Core Domain Power OK Clear Register */
 314         __be32  cdpwrensr;      /* Core Domain Power Enable Status Register */
 315         __be32  cddslsr;        /* Core Domain Deep Sleep Status Register */
 316         u8      res_1e8[8];
 317         __be32  dslpcntcr[8];   /* Deep Sleep Counter Cfg Register */
 318         u8      res_300[3568];
 319 };
 320
 321 #endif