include/linux/mlx5/port.h

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef __MLX5_PORT_H__
  34 #define __MLX5_PORT_H__
  35
  36 #include <linux/mlx5/driver.h>
  37
  38 enum mlx5_beacon_duration {
  39         MLX5_BEACON_DURATION_OFF = 0x0,
  40         MLX5_BEACON_DURATION_INF = 0xffff,
  41 };
  42
  43 enum mlx5_module_id {
  44         MLX5_MODULE_ID_SFP              = 0x3,
  45         MLX5_MODULE_ID_QSFP             = 0xC,
  46         MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
  47         MLX5_MODULE_ID_QSFP28           = 0x11,
  48         MLX5_MODULE_ID_DSFP             = 0x1B,
  49 };
  50
  51 enum mlx5_an_status {
  52         MLX5_AN_UNAVAILABLE = 0,
  53         MLX5_AN_COMPLETE    = 1,
  54         MLX5_AN_FAILED      = 2,
  55         MLX5_AN_LINK_UP     = 3,
  56         MLX5_AN_LINK_DOWN   = 4,
  57 };
  58
  59 #define MLX5_I2C_ADDR_LOW               0x50
  60 #define MLX5_I2C_ADDR_HIGH              0x51
  61 #define MLX5_EEPROM_PAGE_LENGTH         256
  62 #define MLX5_EEPROM_HIGH_PAGE_LENGTH    128
  63
  64 struct mlx5_module_eeprom_query_params {
  65         u16 size;
  66         u16 offset;
  67         u16 i2c_address;
  68         u32 page;
  69         u32 bank;
  70         u32 module_number;
  71 };
  72
  73 enum mlx5e_link_mode {
  74         MLX5E_1000BASE_CX_SGMII  = 0,
  75         MLX5E_1000BASE_KX        = 1,
  76         MLX5E_10GBASE_CX4        = 2,
  77         MLX5E_10GBASE_KX4        = 3,
  78         MLX5E_10GBASE_KR         = 4,
  79         MLX5E_20GBASE_KR2        = 5,
  80         MLX5E_40GBASE_CR4        = 6,
  81         MLX5E_40GBASE_KR4        = 7,
  82         MLX5E_56GBASE_R4         = 8,
  83         MLX5E_10GBASE_CR         = 12,
  84         MLX5E_10GBASE_SR         = 13,
  85         MLX5E_10GBASE_ER         = 14,
  86         MLX5E_40GBASE_SR4        = 15,
  87         MLX5E_40GBASE_LR4        = 16,
  88         MLX5E_50GBASE_SR2        = 18,
  89         MLX5E_100GBASE_CR4       = 20,
  90         MLX5E_100GBASE_SR4       = 21,
  91         MLX5E_100GBASE_KR4       = 22,
  92         MLX5E_100GBASE_LR4       = 23,
  93         MLX5E_100BASE_TX         = 24,
  94         MLX5E_1000BASE_T         = 25,
  95         MLX5E_10GBASE_T          = 26,
  96         MLX5E_25GBASE_CR         = 27,
  97         MLX5E_25GBASE_KR         = 28,
  98         MLX5E_25GBASE_SR         = 29,
  99         MLX5E_50GBASE_CR2        = 30,
 100         MLX5E_50GBASE_KR2        = 31,
 101         MLX5E_LINK_MODES_NUMBER,
 102 };
 103
 104 enum mlx5e_ext_link_mode {
 105         MLX5E_SGMII_100M                        = 0,
 106         MLX5E_1000BASE_X_SGMII                  = 1,
 107         MLX5E_5GBASE_R                          = 3,
 108         MLX5E_10GBASE_XFI_XAUI_1                = 4,
 109         MLX5E_40GBASE_XLAUI_4_XLPPI_4           = 5,
 110         MLX5E_25GAUI_1_25GBASE_CR_KR            = 6,
 111         MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2   = 7,
 112         MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR     = 8,
 113         MLX5E_CAUI_4_100GBASE_CR4_KR4           = 9,
 114         MLX5E_100GAUI_2_100GBASE_CR2_KR2        = 10,
 115         MLX5E_100GAUI_1_100GBASE_CR_KR          = 11,
 116         MLX5E_200GAUI_4_200GBASE_CR4_KR4        = 12,
 117         MLX5E_200GAUI_2_200GBASE_CR2_KR2        = 13,
 118         MLX5E_400GAUI_8_400GBASE_CR8            = 15,
 119         MLX5E_400GAUI_4_400GBASE_CR4_KR4        = 16,
 120         MLX5E_800GAUI_8_800GBASE_CR8_KR8        = 19,
 121         MLX5E_EXT_LINK_MODES_NUMBER,
 122 };
 123
 124 enum mlx5e_connector_type {
 125         MLX5E_PORT_UNKNOWN      = 0,
 126         MLX5E_PORT_NONE                 = 1,
 127         MLX5E_PORT_TP                   = 2,
 128         MLX5E_PORT_AUI                  = 3,
 129         MLX5E_PORT_BNC                  = 4,
 130         MLX5E_PORT_MII                  = 5,
 131         MLX5E_PORT_FIBRE                = 6,
 132         MLX5E_PORT_DA                   = 7,
 133         MLX5E_PORT_OTHER                = 8,
 134         MLX5E_CONNECTOR_TYPE_NUMBER,
 135 };
 136
 137 enum mlx5_ptys_width {
 138         MLX5_PTYS_WIDTH_1X      = 1 << 0,
 139         MLX5_PTYS_WIDTH_2X      = 1 << 1,
 140         MLX5_PTYS_WIDTH_4X      = 1 << 2,
 141         MLX5_PTYS_WIDTH_8X      = 1 << 3,
 142         MLX5_PTYS_WIDTH_12X     = 1 << 4,
 143 };
 144
 145 struct mlx5_port_eth_proto {
 146         u32 cap;
 147         u32 admin;
 148         u32 oper;
 149 };
 150
 151 #define MLX5E_PROT_MASK(link_mode) (1U << link_mode)
 152 #define MLX5_GET_ETH_PROTO(reg, out, ext, field)        \
 153         (ext ? MLX5_GET(reg, out, ext_##field) :        \
 154         MLX5_GET(reg, out, field))
 155
 156 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
 157 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 158                          int ptys_size, int proto_mask,
 159                          u8 local_port, u8 plane_index);
 160
 161 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
 162                             u16 *proto_oper, u8 local_port, u8 plane_index);
 163 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
 164 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 165                                enum mlx5_port_status status);
 166 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 167                                  enum mlx5_port_status *status);
 168 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
 169
 170 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
 171 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
 172 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
 173                               u8 port);
 174
 175 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 176                               u8 *vl_hw_cap, u8 local_port);
 177
 178 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
 179 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 180                           u32 *rx_pause, u32 *tx_pause);
 181
 182 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
 183 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
 184                         u8 *pfc_en_rx);
 185
 186 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
 187                                   u16 stall_critical_watermark,
 188                                   u16 stall_minor_watermark);
 189 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
 190                                     u16 *stall_critical_watermark, u16 *stall_minor_watermark);
 191
 192 int mlx5_max_tc(struct mlx5_core_dev *mdev);
 193
 194 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
 195 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
 196                             u8 prio, u8 *tc);
 197 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
 198 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
 199                              u8 tc, u8 *tc_group);
 200 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
 201 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
 202                                 u8 tc, u8 *bw_pct);
 203 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 204                                     u8 *max_bw_value,
 205                                     u8 *max_bw_unit);
 206 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 207                                    u8 *max_bw_value,
 208                                    u8 *max_bw_unit);
 209 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
 210 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
 211
 212 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
 213 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
 214 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
 215 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
 216                          bool *enabled);
 217 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
 218                              u16 offset, u16 size, u8 *data);
 219 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
 220                                      struct mlx5_module_eeprom_query_params *params, u8 *data);
 221
 222 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
 223 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
 224
 225 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
 226 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
 227 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
 228 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
 229
 230 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
 231                               struct mlx5_port_eth_proto *eproto);
 232 bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev);
 233 u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper,
 234                          bool force_legacy);
 235 u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed,
 236                               bool force_legacy);
 237 int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 238
 239 #endif /* __MLX5_PORT_H__ */