include/linux/rtsx_usb.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Driver for Realtek RTS5139 USB card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Roger Tseng <rogerable@realtek.com>
   8  */
   9
  10 #ifndef __RTSX_USB_H
  11 #define __RTSX_USB_H
  12
  13 #include <linux/usb.h>
  14
  15 /* related module names */
  16 #define RTSX_USB_SD_CARD        0
  17 #define RTSX_USB_MS_CARD        1
  18
  19 /* endpoint numbers */
  20 #define EP_BULK_OUT             1
  21 #define EP_BULK_IN              2
  22 #define EP_INTR_IN              3
  23
  24 /* USB vendor requests */
  25 #define RTSX_USB_REQ_REG_OP     0x00
  26 #define RTSX_USB_REQ_POLL       0x02
  27
  28 /* miscellaneous parameters */
  29 #define MIN_DIV_N               60
  30 #define MAX_DIV_N               120
  31
  32 #define MAX_PHASE               15
  33 #define RX_TUNING_CNT           3
  34
  35 #define QFN24                   0
  36 #define LQFP48                  1
  37 #define CHECK_PKG(ucr, pkg)     ((ucr)->package == (pkg))
  38
  39 /* data structures */
  40 struct rtsx_ucr {
  41         u16                     vendor_id;
  42         u16                     product_id;
  43
  44         int                     package;
  45         u8                      ic_version;
  46         bool                    is_rts5179;
  47
  48         unsigned int            cur_clk;
  49
  50         u8                      *cmd_buf;
  51         unsigned int            cmd_idx;
  52         u8                      *rsp_buf;
  53
  54         struct usb_device       *pusb_dev;
  55         struct usb_interface    *pusb_intf;
  56         struct usb_sg_request   current_sg;
  57
  58         struct timer_list       sg_timer;
  59         struct mutex            dev_mutex;
  60 };
  61
  62 /* buffer size */
  63 #define IOBUF_SIZE              1024
  64
  65 /* prototypes of exported functions */
  66 extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
  67
  68 extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
  69 extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  70                 u8 data);
  71
  72 extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  73                 u8 data);
  74 extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
  75                 u8 *data);
  76
  77 extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
  78                 u16 reg_addr, u8 mask, u8 data);
  79 extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
  80 extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
  81 extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
  82                               void *buf, unsigned int len, int use_sg,
  83                               unsigned int *act_len, int timeout);
  84
  85 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  86 extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  87 extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
  88                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
  89 extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
  90
  91 /* card status */
  92 #define SD_CD           0x01
  93 #define MS_CD           0x02
  94 #define XD_CD           0x04
  95 #define CD_MASK         (SD_CD | MS_CD | XD_CD)
  96 #define SD_WP           0x08
  97
  98 /* reader command field offset & parameters */
  99 #define READ_REG_CMD            0
 100 #define WRITE_REG_CMD           1
 101 #define CHECK_REG_CMD           2
 102
 103 #define PACKET_TYPE             4
 104 #define CNT_H                   5
 105 #define CNT_L                   6
 106 #define STAGE_FLAG              7
 107 #define CMD_OFFSET              8
 108 #define SEQ_WRITE_DATA_OFFSET   12
 109
 110 #define BATCH_CMD               0
 111 #define SEQ_READ                1
 112 #define SEQ_WRITE               2
 113
 114 #define STAGE_R                 0x01
 115 #define STAGE_DI                0x02
 116 #define STAGE_DO                0x04
 117 #define STAGE_MS_STATUS         0x08
 118 #define STAGE_XD_STATUS         0x10
 119 #define MODE_C                  0x00
 120 #define MODE_CR                 (STAGE_R)
 121 #define MODE_CDIR               (STAGE_R | STAGE_DI)
 122 #define MODE_CDOR               (STAGE_R | STAGE_DO)
 123
 124 #define EP0_OP_SHIFT            14
 125 #define EP0_READ_REG_CMD        2
 126 #define EP0_WRITE_REG_CMD       3
 127
 128 #define rtsx_usb_cmd_hdr_tag(ucr)               \
 129         do {                                    \
 130                 ucr->cmd_buf[0] = 'R';          \
 131                 ucr->cmd_buf[1] = 'T';          \
 132                 ucr->cmd_buf[2] = 'C';          \
 133                 ucr->cmd_buf[3] = 'R';          \
 134         } while (0)
 135
 136 static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
 137 {
 138         rtsx_usb_cmd_hdr_tag(ucr);
 139         ucr->cmd_idx = 0;
 140         ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
 141 }
 142
 143 /* internal register address */
 144 #define FPDCTL                          0xFC00
 145 #define SSC_DIV_N_0                     0xFC07
 146 #define SSC_CTL1                        0xFC09
 147 #define SSC_CTL2                        0xFC0A
 148 #define CFG_MODE                        0xFC0E
 149 #define CFG_MODE_1                      0xFC0F
 150 #define RCCTL                           0xFC14
 151 #define SOF_WDOG                        0xFC28
 152 #define SYS_DUMMY0                      0xFC30
 153
 154 #define MS_BLKEND                       0xFD30
 155 #define MS_READ_START                   0xFD31
 156 #define MS_READ_COUNT                   0xFD32
 157 #define MS_WRITE_START                  0xFD33
 158 #define MS_WRITE_COUNT                  0xFD34
 159 #define MS_COMMAND                      0xFD35
 160 #define MS_OLD_BLOCK_0                  0xFD36
 161 #define MS_OLD_BLOCK_1                  0xFD37
 162 #define MS_NEW_BLOCK_0                  0xFD38
 163 #define MS_NEW_BLOCK_1                  0xFD39
 164 #define MS_LOG_BLOCK_0                  0xFD3A
 165 #define MS_LOG_BLOCK_1                  0xFD3B
 166 #define MS_BUS_WIDTH                    0xFD3C
 167 #define MS_PAGE_START                   0xFD3D
 168 #define MS_PAGE_LENGTH                  0xFD3E
 169 #define MS_CFG                          0xFD40
 170 #define MS_TPC                          0xFD41
 171 #define MS_TRANS_CFG                    0xFD42
 172 #define MS_TRANSFER                     0xFD43
 173 #define MS_INT_REG                      0xFD44
 174 #define MS_BYTE_CNT                     0xFD45
 175 #define MS_SECTOR_CNT_L                 0xFD46
 176 #define MS_SECTOR_CNT_H                 0xFD47
 177 #define MS_DBUS_H                       0xFD48
 178
 179 #define CARD_DMA1_CTL                   0xFD5C
 180 #define CARD_PULL_CTL1                  0xFD60
 181 #define CARD_PULL_CTL2                  0xFD61
 182 #define CARD_PULL_CTL3                  0xFD62
 183 #define CARD_PULL_CTL4                  0xFD63
 184 #define CARD_PULL_CTL5                  0xFD64
 185 #define CARD_PULL_CTL6                  0xFD65
 186 #define CARD_EXIST                      0xFD6F
 187 #define CARD_INT_PEND                   0xFD71
 188
 189 #define LDO_POWER_CFG                   0xFD7B
 190
 191 #define SD_CFG1                         0xFDA0
 192 #define SD_CFG2                         0xFDA1
 193 #define SD_CFG3                         0xFDA2
 194 #define SD_STAT1                        0xFDA3
 195 #define SD_STAT2                        0xFDA4
 196 #define SD_BUS_STAT                     0xFDA5
 197 #define SD_PAD_CTL                      0xFDA6
 198 #define SD_SAMPLE_POINT_CTL             0xFDA7
 199 #define SD_PUSH_POINT_CTL               0xFDA8
 200 #define SD_CMD0                         0xFDA9
 201 #define SD_CMD1                         0xFDAA
 202 #define SD_CMD2                         0xFDAB
 203 #define SD_CMD3                         0xFDAC
 204 #define SD_CMD4                         0xFDAD
 205 #define SD_CMD5                         0xFDAE
 206 #define SD_BYTE_CNT_L                   0xFDAF
 207 #define SD_BYTE_CNT_H                   0xFDB0
 208 #define SD_BLOCK_CNT_L                  0xFDB1
 209 #define SD_BLOCK_CNT_H                  0xFDB2
 210 #define SD_TRANSFER                     0xFDB3
 211 #define SD_CMD_STATE                    0xFDB5
 212 #define SD_DATA_STATE                   0xFDB6
 213 #define SD_VPCLK0_CTL                   0xFC2A
 214 #define SD_VPCLK1_CTL                   0xFC2B
 215 #define SD_DCMPS0_CTL                   0xFC2C
 216 #define SD_DCMPS1_CTL                   0xFC2D
 217
 218 #define CARD_DMA1_CTL                   0xFD5C
 219
 220 #define HW_VERSION                      0xFC01
 221
 222 #define SSC_CLK_FPGA_SEL                0xFC02
 223 #define CLK_DIV                         0xFC03
 224 #define SFSM_ED                         0xFC04
 225
 226 #define CD_DEGLITCH_WIDTH               0xFC20
 227 #define CD_DEGLITCH_EN                  0xFC21
 228 #define AUTO_DELINK_EN                  0xFC23
 229
 230 #define FPGA_PULL_CTL                   0xFC1D
 231 #define CARD_CLK_SOURCE                 0xFC2E
 232
 233 #define CARD_SHARE_MODE                 0xFD51
 234 #define CARD_DRIVE_SEL                  0xFD52
 235 #define CARD_STOP                       0xFD53
 236 #define CARD_OE                         0xFD54
 237 #define CARD_AUTO_BLINK                 0xFD55
 238 #define CARD_GPIO                       0xFD56
 239 #define SD30_DRIVE_SEL                  0xFD57
 240
 241 #define CARD_DATA_SOURCE                0xFD5D
 242 #define CARD_SELECT                     0xFD5E
 243
 244 #define CARD_CLK_EN                     0xFD79
 245 #define CARD_PWR_CTL                    0xFD7A
 246
 247 #define OCPCTL                          0xFD80
 248 #define OCPPARA1                        0xFD81
 249 #define OCPPARA2                        0xFD82
 250 #define OCPSTAT                         0xFD83
 251
 252 #define HS_USB_STAT                     0xFE01
 253 #define HS_VCONTROL                     0xFE26
 254 #define HS_VSTAIN                       0xFE27
 255 #define HS_VLOADM                       0xFE28
 256 #define HS_VSTAOUT                      0xFE29
 257
 258 #define MC_IRQ                          0xFF00
 259 #define MC_IRQEN                        0xFF01
 260 #define MC_FIFO_CTL                     0xFF02
 261 #define MC_FIFO_BC0                     0xFF03
 262 #define MC_FIFO_BC1                     0xFF04
 263 #define MC_FIFO_STAT                    0xFF05
 264 #define MC_FIFO_MODE                    0xFF06
 265 #define MC_FIFO_RD_PTR0                 0xFF07
 266 #define MC_FIFO_RD_PTR1                 0xFF08
 267 #define MC_DMA_CTL                      0xFF10
 268 #define MC_DMA_TC0                      0xFF11
 269 #define MC_DMA_TC1                      0xFF12
 270 #define MC_DMA_TC2                      0xFF13
 271 #define MC_DMA_TC3                      0xFF14
 272 #define MC_DMA_RST                      0xFF15
 273
 274 #define RBUF_SIZE_MASK                  0xFBFF
 275 #define RBUF_BASE                       0xF000
 276 #define PPBUF_BASE1                     0xF800
 277 #define PPBUF_BASE2                     0xFA00
 278
 279 /* internal register value macros */
 280 #define POWER_OFF                       0x03
 281 #define PARTIAL_POWER_ON                0x02
 282 #define POWER_ON                        0x00
 283 #define POWER_MASK                      0x03
 284 #define LDO3318_PWR_MASK                0x0C
 285 #define LDO_ON                          0x00
 286 #define LDO_SUSPEND                     0x08
 287 #define LDO_OFF                         0x0C
 288 #define DV3318_AUTO_PWR_OFF             0x10
 289 #define FORCE_LDO_POWERB                0x60
 290
 291 /* LDO_POWER_CFG */
 292 #define TUNE_SD18_MASK                  0x1C
 293 #define TUNE_SD18_1V7                   0x00
 294 #define TUNE_SD18_1V8                   (0x01 << 2)
 295 #define TUNE_SD18_1V9                   (0x02 << 2)
 296 #define TUNE_SD18_2V0                   (0x03 << 2)
 297 #define TUNE_SD18_2V7                   (0x04 << 2)
 298 #define TUNE_SD18_2V8                   (0x05 << 2)
 299 #define TUNE_SD18_2V9                   (0x06 << 2)
 300 #define TUNE_SD18_3V3                   (0x07 << 2)
 301
 302 /* CLK_DIV */
 303 #define CLK_CHANGE                      0x80
 304 #define CLK_DIV_1                       0x00
 305 #define CLK_DIV_2                       0x01
 306 #define CLK_DIV_4                       0x02
 307 #define CLK_DIV_8                       0x03
 308
 309 #define SSC_POWER_MASK                  0x01
 310 #define SSC_POWER_DOWN                  0x01
 311 #define SSC_POWER_ON                    0x00
 312
 313 #define FPGA_VER                        0x80
 314 #define HW_VER_MASK                     0x0F
 315
 316 #define EXTEND_DMA1_ASYNC_SIGNAL        0x02
 317
 318 /* CFG_MODE*/
 319 #define XTAL_FREE                       0x80
 320 #define CLK_MODE_MASK                   0x03
 321 #define CLK_MODE_12M_XTAL               0x00
 322 #define CLK_MODE_NON_XTAL               0x01
 323 #define CLK_MODE_24M_OSC                0x02
 324 #define CLK_MODE_48M_OSC                0x03
 325
 326 /* CFG_MODE_1*/
 327 #define RTS5179                         0x02
 328
 329 #define NYET_EN                         0x01
 330 #define NYET_MSAK                       0x01
 331
 332 #define SD30_DRIVE_MASK                 0x07
 333 #define SD20_DRIVE_MASK                 0x03
 334
 335 #define DISABLE_SD_CD                   0x08
 336 #define DISABLE_MS_CD                   0x10
 337 #define DISABLE_XD_CD                   0x20
 338 #define SD_CD_DEGLITCH_EN               0x01
 339 #define MS_CD_DEGLITCH_EN               0x02
 340 #define XD_CD_DEGLITCH_EN               0x04
 341
 342 #define CARD_SHARE_LQFP48               0x04
 343 #define CARD_SHARE_QFN24                0x00
 344 #define CARD_SHARE_LQFP_SEL             0x04
 345 #define CARD_SHARE_XD                   0x00
 346 #define CARD_SHARE_SD                   0x01
 347 #define CARD_SHARE_MS                   0x02
 348 #define CARD_SHARE_MASK                 0x03
 349
 350
 351 /* SD30_DRIVE_SEL */
 352 #define DRIVER_TYPE_A                   0x05
 353 #define DRIVER_TYPE_B                   0x03
 354 #define DRIVER_TYPE_C                   0x02
 355 #define DRIVER_TYPE_D                   0x01
 356
 357 /* SD_BUS_STAT */
 358 #define SD_CLK_TOGGLE_EN                0x80
 359 #define SD_CLK_FORCE_STOP               0x40
 360 #define SD_DAT3_STATUS                  0x10
 361 #define SD_DAT2_STATUS                  0x08
 362 #define SD_DAT1_STATUS                  0x04
 363 #define SD_DAT0_STATUS                  0x02
 364 #define SD_CMD_STATUS                   0x01
 365
 366 /* SD_PAD_CTL */
 367 #define SD_IO_USING_1V8                 0x80
 368 #define SD_IO_USING_3V3                 0x7F
 369 #define TYPE_A_DRIVING                  0x00
 370 #define TYPE_B_DRIVING                  0x01
 371 #define TYPE_C_DRIVING                  0x02
 372 #define TYPE_D_DRIVING                  0x03
 373
 374 /* CARD_CLK_EN */
 375 #define SD_CLK_EN                       0x04
 376 #define MS_CLK_EN                       0x08
 377
 378 /* CARD_SELECT */
 379 #define SD_MOD_SEL                      2
 380 #define MS_MOD_SEL                      3
 381
 382 /* CARD_SHARE_MODE */
 383 #define CARD_SHARE_LQFP48               0x04
 384 #define CARD_SHARE_QFN24                0x00
 385 #define CARD_SHARE_LQFP_SEL             0x04
 386 #define CARD_SHARE_XD                   0x00
 387 #define CARD_SHARE_SD                   0x01
 388 #define CARD_SHARE_MS                   0x02
 389 #define CARD_SHARE_MASK                 0x03
 390
 391 /* SSC_CTL1 */
 392 #define SSC_RSTB                        0x80
 393 #define SSC_8X_EN                       0x40
 394 #define SSC_FIX_FRAC                    0x20
 395 #define SSC_SEL_1M                      0x00
 396 #define SSC_SEL_2M                      0x08
 397 #define SSC_SEL_4M                      0x10
 398 #define SSC_SEL_8M                      0x18
 399
 400 /* SSC_CTL2 */
 401 #define SSC_DEPTH_MASK                  0x03
 402 #define SSC_DEPTH_DISALBE               0x00
 403 #define SSC_DEPTH_2M                    0x01
 404 #define SSC_DEPTH_1M                    0x02
 405 #define SSC_DEPTH_512K                  0x03
 406
 407 /* SD_VPCLK0_CTL */
 408 #define PHASE_CHANGE                    0x80
 409 #define PHASE_NOT_RESET                 0x40
 410
 411 /* SD_TRANSFER */
 412 #define SD_TRANSFER_START               0x80
 413 #define SD_TRANSFER_END                 0x40
 414 #define SD_STAT_IDLE                    0x20
 415 #define SD_TRANSFER_ERR                 0x10
 416 #define SD_TM_NORMAL_WRITE              0x00
 417 #define SD_TM_AUTO_WRITE_3              0x01
 418 #define SD_TM_AUTO_WRITE_4              0x02
 419 #define SD_TM_AUTO_READ_3               0x05
 420 #define SD_TM_AUTO_READ_4               0x06
 421 #define SD_TM_CMD_RSP                   0x08
 422 #define SD_TM_AUTO_WRITE_1              0x09
 423 #define SD_TM_AUTO_WRITE_2              0x0A
 424 #define SD_TM_NORMAL_READ               0x0C
 425 #define SD_TM_AUTO_READ_1               0x0D
 426 #define SD_TM_AUTO_READ_2               0x0E
 427 #define SD_TM_AUTO_TUNING               0x0F
 428
 429 /* SD_CFG1 */
 430 #define SD_CLK_DIVIDE_0                 0x00
 431 #define SD_CLK_DIVIDE_256               0xC0
 432 #define SD_CLK_DIVIDE_128               0x80
 433 #define SD_CLK_DIVIDE_MASK              0xC0
 434 #define SD_BUS_WIDTH_1BIT               0x00
 435 #define SD_BUS_WIDTH_4BIT               0x01
 436 #define SD_BUS_WIDTH_8BIT               0x02
 437 #define SD_ASYNC_FIFO_RST               0x10
 438 #define SD_20_MODE                      0x00
 439 #define SD_DDR_MODE                     0x04
 440 #define SD_30_MODE                      0x08
 441
 442 /* SD_CFG2 */
 443 #define SD_CALCULATE_CRC7               0x00
 444 #define SD_NO_CALCULATE_CRC7            0x80
 445 #define SD_CHECK_CRC16                  0x00
 446 #define SD_NO_CHECK_CRC16               0x40
 447 #define SD_WAIT_CRC_TO_EN               0x20
 448 #define SD_WAIT_BUSY_END                0x08
 449 #define SD_NO_WAIT_BUSY_END             0x00
 450 #define SD_CHECK_CRC7                   0x00
 451 #define SD_NO_CHECK_CRC7                0x04
 452 #define SD_RSP_LEN_0                    0x00
 453 #define SD_RSP_LEN_6                    0x01
 454 #define SD_RSP_LEN_17                   0x02
 455 #define SD_RSP_TYPE_R0                  0x04
 456 #define SD_RSP_TYPE_R1                  0x01
 457 #define SD_RSP_TYPE_R1b                 0x09
 458 #define SD_RSP_TYPE_R2                  0x02
 459 #define SD_RSP_TYPE_R3                  0x05
 460 #define SD_RSP_TYPE_R4                  0x05
 461 #define SD_RSP_TYPE_R5                  0x01
 462 #define SD_RSP_TYPE_R6                  0x01
 463 #define SD_RSP_TYPE_R7                  0x01
 464
 465 /* SD_STAT1 */
 466 #define SD_CRC7_ERR                     0x80
 467 #define SD_CRC16_ERR                    0x40
 468 #define SD_CRC_WRITE_ERR                0x20
 469 #define SD_CRC_WRITE_ERR_MASK           0x1C
 470 #define GET_CRC_TIME_OUT                0x02
 471 #define SD_TUNING_COMPARE_ERR           0x01
 472
 473 /* SD_DATA_STATE */
 474 #define SD_DATA_IDLE                    0x80
 475
 476 /* CARD_DATA_SOURCE */
 477 #define PINGPONG_BUFFER                 0x01
 478 #define RING_BUFFER                     0x00
 479
 480 /* CARD_OE */
 481 #define SD_OUTPUT_EN                    0x04
 482 #define MS_OUTPUT_EN                    0x08
 483
 484 /* CARD_STOP */
 485 #define SD_STOP                         0x04
 486 #define MS_STOP                         0x08
 487 #define SD_CLR_ERR                      0x40
 488 #define MS_CLR_ERR                      0x80
 489
 490 /* CARD_CLK_SOURCE */
 491 #define CRC_FIX_CLK                     (0x00 << 0)
 492 #define CRC_VAR_CLK0                    (0x01 << 0)
 493 #define CRC_VAR_CLK1                    (0x02 << 0)
 494 #define SD30_FIX_CLK                    (0x00 << 2)
 495 #define SD30_VAR_CLK0                   (0x01 << 2)
 496 #define SD30_VAR_CLK1                   (0x02 << 2)
 497 #define SAMPLE_FIX_CLK                  (0x00 << 4)
 498 #define SAMPLE_VAR_CLK0                 (0x01 << 4)
 499 #define SAMPLE_VAR_CLK1                 (0x02 << 4)
 500
 501 /* SD_SAMPLE_POINT_CTL */
 502 #define DDR_FIX_RX_DAT                  0x00
 503 #define DDR_VAR_RX_DAT                  0x80
 504 #define DDR_FIX_RX_DAT_EDGE             0x00
 505 #define DDR_FIX_RX_DAT_14_DELAY         0x40
 506 #define DDR_FIX_RX_CMD                  0x00
 507 #define DDR_VAR_RX_CMD                  0x20
 508 #define DDR_FIX_RX_CMD_POS_EDGE         0x00
 509 #define DDR_FIX_RX_CMD_14_DELAY         0x10
 510 #define SD20_RX_POS_EDGE                0x00
 511 #define SD20_RX_14_DELAY                0x08
 512 #define SD20_RX_SEL_MASK                0x08
 513
 514 /* SD_PUSH_POINT_CTL */
 515 #define DDR_FIX_TX_CMD_DAT              0x00
 516 #define DDR_VAR_TX_CMD_DAT              0x80
 517 #define DDR_FIX_TX_DAT_14_TSU           0x00
 518 #define DDR_FIX_TX_DAT_12_TSU           0x40
 519 #define DDR_FIX_TX_CMD_NEG_EDGE         0x00
 520 #define DDR_FIX_TX_CMD_14_AHEAD         0x20
 521 #define SD20_TX_NEG_EDGE                0x00
 522 #define SD20_TX_14_AHEAD                0x10
 523 #define SD20_TX_SEL_MASK                0x10
 524 #define DDR_VAR_SDCLK_POL_SWAP          0x01
 525
 526 /* MS_CFG */
 527 #define SAMPLE_TIME_RISING              0x00
 528 #define SAMPLE_TIME_FALLING             0x80
 529 #define PUSH_TIME_DEFAULT               0x00
 530 #define PUSH_TIME_ODD                   0x40
 531 #define NO_EXTEND_TOGGLE                0x00
 532 #define EXTEND_TOGGLE_CHK               0x20
 533 #define MS_BUS_WIDTH_1                  0x00
 534 #define MS_BUS_WIDTH_4                  0x10
 535 #define MS_BUS_WIDTH_8                  0x18
 536 #define MS_2K_SECTOR_MODE               0x04
 537 #define MS_512_SECTOR_MODE              0x00
 538 #define MS_TOGGLE_TIMEOUT_EN            0x00
 539 #define MS_TOGGLE_TIMEOUT_DISEN         0x01
 540 #define MS_NO_CHECK_INT                 0x02
 541
 542 /* MS_TRANS_CFG */
 543 #define WAIT_INT                        0x80
 544 #define NO_WAIT_INT                     0x00
 545 #define NO_AUTO_READ_INT_REG            0x00
 546 #define AUTO_READ_INT_REG               0x40
 547 #define MS_CRC16_ERR                    0x20
 548 #define MS_RDY_TIMEOUT                  0x10
 549 #define MS_INT_CMDNK                    0x08
 550 #define MS_INT_BREQ                     0x04
 551 #define MS_INT_ERR                      0x02
 552 #define MS_INT_CED                      0x01
 553
 554 /* MS_TRANSFER */
 555 #define MS_TRANSFER_START               0x80
 556 #define MS_TRANSFER_END                 0x40
 557 #define MS_TRANSFER_ERR                 0x20
 558 #define MS_BS_STATE                     0x10
 559 #define MS_TM_READ_BYTES                0x00
 560 #define MS_TM_NORMAL_READ               0x01
 561 #define MS_TM_WRITE_BYTES               0x04
 562 #define MS_TM_NORMAL_WRITE              0x05
 563 #define MS_TM_AUTO_READ                 0x08
 564 #define MS_TM_AUTO_WRITE                0x0C
 565 #define MS_TM_SET_CMD                   0x06
 566 #define MS_TM_COPY_PAGE                 0x07
 567 #define MS_TM_MULTI_READ                0x02
 568 #define MS_TM_MULTI_WRITE               0x03
 569
 570 /* MC_FIFO_CTL */
 571 #define FIFO_FLUSH                      0x01
 572
 573 /* MC_DMA_RST */
 574 #define DMA_RESET  0x01
 575
 576 /* MC_DMA_CTL */
 577 #define DMA_TC_EQ_0                     0x80
 578 #define DMA_DIR_TO_CARD                 0x00
 579 #define DMA_DIR_FROM_CARD               0x02
 580 #define DMA_EN                          0x01
 581 #define DMA_128                         (0 << 2)
 582 #define DMA_256                         (1 << 2)
 583 #define DMA_512                         (2 << 2)
 584 #define DMA_1024                        (3 << 2)
 585 #define DMA_PACK_SIZE_MASK              0x0C
 586
 587 /* CARD_INT_PEND */
 588 #define XD_INT                          0x10
 589 #define MS_INT                          0x08
 590 #define SD_INT                          0x04
 591
 592 /* LED operations*/
 593 static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
 594 {
 595         return  rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
 596 }
 597
 598 static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
 599 {
 600         return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
 601 }
 602
 603 /* HW error clearing */
 604 static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
 605 {
 606         rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
 607 }
 608
 609 static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
 610 {
 611         rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
 612                         FIFO_FLUSH, FIFO_FLUSH);
 613         rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
 614 }
 615 #endif /* __RTS51139_H */