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printf: Remove unused 'bprintf'
[drm/drm-misc.git] / sound / soc / codecs / msm8916-wcd-analog.c
blob9ca38181297559b9124655f3ae42ce2011a5d465
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/regulator/consumer.h>
9 #include <linux/types.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <sound/soc.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include <sound/tlv.h>
17 #include <sound/jack.h>
18
19 #define CDC_D_REVISION1 (0xf000)
20 #define CDC_D_PERPH_SUBTYPE (0xf005)
21 #define CDC_D_INT_EN_SET (0xf015)
22 #define CDC_D_INT_EN_CLR (0xf016)
23 #define MBHC_SWITCH_INT BIT(7)
24 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
25 #define MBHC_BUTTON_PRESS_DET BIT(5)
26 #define MBHC_BUTTON_RELEASE_DET BIT(4)
27 #define CDC_D_CDC_RST_CTL (0xf046)
28 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
29 #define RST_CTL_DIG_SW_RST_N_RESET 0
30 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
31
32 #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
33 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
34 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
35 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
36
37 #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
38 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
40 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
41 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
42 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
43 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
44
45 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
46 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
47 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
48 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
49 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
50 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
51 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
52 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
53 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
54 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
55 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
56
57 #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
58 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
59 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
60 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
61 #define CONN_TX1_SERIAL_TX1_ZERO 0x2
62
63 #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
64 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
65 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
66 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
67 #define CONN_TX2_SERIAL_TX2_ZERO 0x2
68 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
69 #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
70 #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
71 #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
72 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
73 #define CDC_D_SEC_ACCESS (0xf0D0)
74 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
75 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
76 #define CDC_A_REVISION1 (0xf100)
77 #define CDC_A_REVISION2 (0xf101)
78 #define CDC_A_REVISION3 (0xf102)
79 #define CDC_A_REVISION4 (0xf103)
80 #define CDC_A_PERPH_TYPE (0xf104)
81 #define CDC_A_PERPH_SUBTYPE (0xf105)
82 #define CDC_A_INT_RT_STS (0xf110)
83 #define CDC_A_INT_SET_TYPE (0xf111)
84 #define CDC_A_INT_POLARITY_HIGH (0xf112)
85 #define CDC_A_INT_POLARITY_LOW (0xf113)
86 #define CDC_A_INT_LATCHED_CLR (0xf114)
87 #define CDC_A_INT_EN_SET (0xf115)
88 #define CDC_A_INT_EN_CLR (0xf116)
89 #define CDC_A_INT_LATCHED_STS (0xf118)
90 #define CDC_A_INT_PENDING_STS (0xf119)
91 #define CDC_A_INT_MID_SEL (0xf11A)
92 #define CDC_A_INT_PRIORITY (0xf11B)
93 #define CDC_A_MICB_1_EN (0xf140)
94 #define MICB_1_EN_MICB_ENABLE BIT(7)
95 #define MICB_1_EN_BYP_CAP_MASK BIT(6)
96 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
97 #define MICB_1_EN_EXT_BYP_CAP 0
98 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
99 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
100 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
102 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
103 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
104 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
105
106 #define CDC_A_MICB_1_VAL (0xf141)
107 #define MICB_MIN_VAL 1600
108 #define MICB_STEP_SIZE 50
109 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
110 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
111 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
112 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
113 #define CDC_A_MICB_1_CTL (0xf142)
114
115 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
116 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
117 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
118 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
119 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
120 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
121
122 #define CDC_A_MICB_1_INT_RBIAS (0xf143)
123 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
124 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
125 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
126
127 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
128 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
130
131 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
132 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
133 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
134 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
135 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
137
138 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
139 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
140 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
141 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
142 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
144
145 #define CDC_A_MICB_2_EN (0xf144)
146 #define CDC_A_MICB_2_EN_ENABLE BIT(7)
147 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
148 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
149 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
150 #define CDC_A_MASTER_BIAS_CTL (0xf146)
151 #define CDC_A_MBHC_DET_CTL_1 (0xf147)
152 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
153 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
154 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
158 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
161 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
162 #define CDC_A_MBHC_DET_CTL_2 (0xf150)
163 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
165 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
166 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
167 #define CDC_A_GND_PLUG_TYPE_NO BIT(3)
168 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
170 #define CDC_A_MBHC_FSM_CTL (0xf151)
171 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
173 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
175 #define CDC_A_MBHC_DBNC_TIMER (0xf152)
176 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
177 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
178 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
179 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
180 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
181 #define CDC_A_MBHC_BTN3_CTL (0xf156)
182 #define CDC_A_MBHC_BTN4_CTL (0xf157)
183 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
184 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
185 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
186 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
187 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
188 CDC_A_MBHC_BTN_VREF_FINE_MASK)
189 #define CDC_A_MBHC_RESULT_1 (0xf158)
190 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
191 #define CDC_A_TX_1_EN (0xf160)
192 #define CDC_A_TX_2_EN (0xf161)
193 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
194 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
195 #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
196 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
197 #define CDC_A_TX_3_EN (0xf167)
198 #define CDC_A_NCP_EN (0xf180)
199 #define CDC_A_NCP_CLK (0xf181)
200 #define CDC_A_NCP_FBCTRL (0xf183)
201 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
203 #define CDC_A_NCP_BIAS (0xf184)
204 #define CDC_A_NCP_VCTRL (0xf185)
205 #define CDC_A_NCP_TEST (0xf186)
206 #define CDC_A_NCP_CLIM_ADDR (0xf187)
207 #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
208 #define CDC_A_RX_COM_OCP_CTL (0xf191)
209 #define CDC_A_RX_COM_OCP_COUNT (0xf192)
210 #define CDC_A_RX_COM_BIAS_DAC (0xf193)
211 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
213 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
214 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
215
216 #define CDC_A_RX_HPH_BIAS_PA (0xf194)
217 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
218 #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
219 #define CDC_A_RX_HPH_CNP_EN (0xf197)
220 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
221 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
223 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
224 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
225 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
226
227 #define CDC_A_RX_EAR_CTL (0xf19E)
228 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
230 #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)
231 #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)
232 #define RX_EAR_CTL_PA_SEL_MASK BIT(7)
233 #define RX_EAR_CTL_PA_SEL BIT(7)
234
235 #define CDC_A_SPKR_DAC_CTL (0xf1B0)
236 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
237 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
238
239 #define CDC_A_SPKR_DRV_CTL (0xf1B2)
240 #define SPKR_DRV_CTL_DEF_MASK 0xEF
241 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
242 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
243 #define SPKR_DRV_CAL_EN BIT(6)
244 #define SPKR_DRV_SETTLE_EN BIT(5)
245 #define SPKR_DRV_FW_EN BIT(3)
246 #define SPKR_DRV_BOOST_SET BIT(2)
247 #define SPKR_DRV_CMFB_SET BIT(1)
248 #define SPKR_DRV_GAIN_SET BIT(0)
249 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
250 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
251 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
252 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
253 #define CDC_A_SPKR_OCP_CTL (0xf1B4)
254 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
255 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
256 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
257 #define SPKR_PWRSTG_CTL_MASK 0xE0
258 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
259 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
260 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
261 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
262 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
263 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
264
265 #define CDC_A_SPKR_DRV_DBG (0xf1B7)
266 #define CDC_A_CURRENT_LIMIT (0xf1C0)
267 #define CDC_A_BOOST_EN_CTL (0xf1C3)
268 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
269 #define CDC_A_SEC_ACCESS (0xf1D0)
270 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
271 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
272
273 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
274 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
275 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
276 SNDRV_PCM_FMTBIT_S32_LE)
277
278 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
279 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
280 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
281
282 static const char * const supply_names[] = {
283 "vdd-cdc-io",
284 "vdd-cdc-tx-rx-cx",
285 };
286
287 #define MBHC_MAX_BUTTONS (5)
288
289 struct pm8916_wcd_analog_priv {
290 u16 pmic_rev;
291 u16 codec_version;
292 bool mbhc_btn_enabled;
293 /* special event to detect accessory type */
294 int mbhc_btn0_released;
295 bool detect_accessory_type;
296 struct clk *mclk;
297 struct snd_soc_component *component;
298 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
299 struct snd_soc_jack *jack;
300 bool hphl_jack_type_normally_open;
301 bool gnd_jack_type_normally_open;
302 /* Voltage threshold when internal current source of 100uA is used */
303 u32 vref_btn_cs[MBHC_MAX_BUTTONS];
304 /* Voltage threshold when microphone bias is ON */
305 u32 vref_btn_micb[MBHC_MAX_BUTTONS];
306 unsigned int micbias1_cap_mode;
307 unsigned int micbias2_cap_mode;
308 unsigned int micbias_mv;
309 };
310
311 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
312 static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
313 static const char *const hph_text[] = { "ZERO", "Switch", };
314
315 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
316 ARRAY_SIZE(hph_text), hph_text);
317
318 static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum);
319 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
320 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
321
322 /* ADC2 MUX */
323 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
324 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
325
326 /* RDAC2 MUX */
327 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
328 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
329
330 static const struct snd_kcontrol_new spkr_switch[] = {
331 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
332 };
333
334 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
335 "RDAC2 MUX Mux", rdac2_mux_enum);
336 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
337 "ADC2 MUX Mux", adc2_enum);
338
339 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
340 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
341
342 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
343 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
344 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
345 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
346 };
347
348 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
349 {
350 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
351
352 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
353 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
354 MICB_1_CTL_INT_PRECHARG_BYP_MASK,
355 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
356 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
357
358 if (wcd->micbias_mv) {
359 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
360 MICB_1_VAL_MICB_OUT_VAL_MASK,
361 MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
362 /*
363 * Special headset needs MICBIAS as 2.7V so wait for
364 * 50 msec for the MICBIAS to reach 2.7 volts.
365 */
366 if (wcd->micbias_mv >= 2700)
367 msleep(50);
368 }
369
370 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
371 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
372 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
373
374 }
375
376 static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
377 int event, unsigned int cap_mode)
378 {
379 switch (event) {
380 case SND_SOC_DAPM_POST_PMU:
381 pm8916_wcd_analog_micbias_enable(component);
382 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
383 MICB_1_EN_BYP_CAP_MASK, cap_mode);
384 break;
385 }
386
387 return 0;
388 }
389
390 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
391 struct snd_kcontrol *kcontrol,
392 int event)
393 {
394 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
395
396 switch (event) {
397 case SND_SOC_DAPM_PRE_PMU:
398 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
399 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
400 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
401 break;
402 }
403
404 return 0;
405 }
406
407 static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
408 struct snd_kcontrol *kcontrol,
409 int event)
410 {
411 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
412 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
413
414 return pm8916_wcd_analog_enable_micbias(component, event,
415 wcd->micbias1_cap_mode);
416 }
417
418 static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
419 struct snd_kcontrol *kcontrol,
420 int event)
421 {
422 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
423 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
424
425 return pm8916_wcd_analog_enable_micbias(component, event,
426 wcd->micbias2_cap_mode);
427
428 }
429
430 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
431 bool micbias2_enabled)
432 {
433 struct snd_soc_component *component = priv->component;
434 u32 coarse, fine, reg_val, reg_addr;
435 int *vrefs, i;
436
437 if (!micbias2_enabled) { /* use internal 100uA Current source */
438 /* Enable internal 2.2k Internal Rbias Resistor */
439 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
440 MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
441 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
442 /* Remove pull down on MIC BIAS2 */
443 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
444 CDC_A_MICB_2_PULL_DOWN_EN_MASK,
445 0);
446 /* enable 100uA internal current source */
447 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
448 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
449 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
450 }
451 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
452 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
453 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
454
455 if (micbias2_enabled)
456 vrefs = &priv->vref_btn_micb[0];
457 else
458 vrefs = &priv->vref_btn_cs[0];
459
460 /* program vref ranges for all the buttons */
461 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
462 for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
463 /* split mv in to coarse parts of 100mv & fine parts of 12mv */
464 coarse = (vrefs[i] / 100);
465 fine = ((vrefs[i] % 100) / 12);
466 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
467 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
468 snd_soc_component_update_bits(component, reg_addr,
469 CDC_A_MBHC_BTN_VREF_MASK,
470 reg_val);
471 reg_addr++;
472 }
473
474 return 0;
475 }
476
477 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
478 {
479 struct snd_soc_component *component = wcd->component;
480 bool micbias_enabled = false;
481 u32 plug_type = 0;
482 u32 int_en_mask;
483
484 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
485 CDC_A_MBHC_DET_CTL_L_DET_EN |
486 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
487 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
488 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
489
490 if (wcd->hphl_jack_type_normally_open)
491 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
492
493 if (wcd->gnd_jack_type_normally_open)
494 plug_type |= CDC_A_GND_PLUG_TYPE_NO;
495
496 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
497 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
498 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
499 plug_type |
500 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
501
502
503 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
504 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
505 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
506
507 /* enable MBHC clock */
508 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
509 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
510 DIG_CLK_CTL_D_MBHC_CLK_EN);
511
512 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
513 micbias_enabled = true;
514
515 pm8916_mbhc_configure_bias(wcd, micbias_enabled);
516
517 int_en_mask = MBHC_SWITCH_INT;
518 if (wcd->mbhc_btn_enabled)
519 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
520
521 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
522 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
523 wcd->mbhc_btn0_released = false;
524 wcd->detect_accessory_type = true;
525 }
526
527 static int pm8916_wcd_analog_enable_micbias_int2(struct
528 snd_soc_dapm_widget
529 *w, struct snd_kcontrol
530 *kcontrol, int event)
531 {
532 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
533 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
534
535 switch (event) {
536 case SND_SOC_DAPM_PRE_PMU:
537 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
538 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);
539 break;
540 case SND_SOC_DAPM_POST_PMU:
541 pm8916_mbhc_configure_bias(wcd, true);
542 break;
543 case SND_SOC_DAPM_POST_PMD:
544 pm8916_mbhc_configure_bias(wcd, false);
545 break;
546 }
547
548 return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);
549 }
550
551 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
552 struct snd_kcontrol *kcontrol,
553 int event)
554 {
555 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
556 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
557 u8 init_bit_shift;
558
559 if (w->reg == CDC_A_TX_1_EN)
560 init_bit_shift = 5;
561 else
562 init_bit_shift = 4;
563
564 switch (event) {
565 case SND_SOC_DAPM_PRE_PMU:
566 if (w->reg == CDC_A_TX_2_EN)
567 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
568 MICB_1_CTL_CFILT_REF_SEL_MASK,
569 MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
570 /*
571 * Add delay of 10 ms to give sufficient time for the voltage
572 * to shoot up and settle so that the txfe init does not
573 * happen when the input voltage is changing too much.
574 */
575 usleep_range(10000, 10010);
576 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
577 1 << init_bit_shift);
578 switch (w->reg) {
579 case CDC_A_TX_1_EN:
580 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
581 CONN_TX1_SERIAL_TX1_MUX,
582 CONN_TX1_SERIAL_TX1_ADC_1);
583 break;
584 case CDC_A_TX_2_EN:
585 case CDC_A_TX_3_EN:
586 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
587 CONN_TX2_SERIAL_TX2_MUX,
588 CONN_TX2_SERIAL_TX2_ADC_2);
589 break;
590 }
591 break;
592 case SND_SOC_DAPM_POST_PMU:
593 /*
594 * Add delay of 12 ms before deasserting the init
595 * to reduce the tx pop
596 */
597 usleep_range(12000, 12010);
598 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
599 break;
600 case SND_SOC_DAPM_POST_PMD:
601 switch (w->reg) {
602 case CDC_A_TX_1_EN:
603 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
604 CONN_TX1_SERIAL_TX1_MUX,
605 CONN_TX1_SERIAL_TX1_ZERO);
606 break;
607 case CDC_A_TX_2_EN:
608 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
609 MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
610 fallthrough;
611 case CDC_A_TX_3_EN:
612 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
613 CONN_TX2_SERIAL_TX2_MUX,
614 CONN_TX2_SERIAL_TX2_ZERO);
615 break;
616 }
617
618
619 break;
620 }
621 return 0;
622 }
623
624 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
625 struct snd_kcontrol *kcontrol,
626 int event)
627 {
628 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
629
630 switch (event) {
631 case SND_SOC_DAPM_PRE_PMU:
632 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
633 SPKR_PWRSTG_CTL_DAC_EN_MASK |
634 SPKR_PWRSTG_CTL_BBM_MASK |
635 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
636 SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
637 SPKR_PWRSTG_CTL_DAC_EN|
638 SPKR_PWRSTG_CTL_BBM_EN |
639 SPKR_PWRSTG_CTL_HBRDGE_EN |
640 SPKR_PWRSTG_CTL_CLAMP_EN);
641
642 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
643 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
644 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
645 break;
646 case SND_SOC_DAPM_POST_PMU:
647 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
648 SPKR_DRV_CTL_DEF_MASK,
649 SPKR_DRV_CTL_DEF_VAL);
650 snd_soc_component_update_bits(component, w->reg,
651 SPKR_DRV_CLASSD_PA_EN_MASK,
652 SPKR_DRV_CLASSD_PA_EN_ENABLE);
653 break;
654 case SND_SOC_DAPM_POST_PMD:
655 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
656 SPKR_PWRSTG_CTL_DAC_EN_MASK|
657 SPKR_PWRSTG_CTL_BBM_MASK |
658 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
659 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
660
661 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
662 SPKR_DAC_CTL_DAC_RESET_MASK,
663 SPKR_DAC_CTL_DAC_RESET_NORMAL);
664 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
665 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
666 break;
667 }
668 return 0;
669 }
670
671 static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
672 struct snd_kcontrol *kcontrol,
673 int event)
674 {
675 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
676
677 switch (event) {
678 case SND_SOC_DAPM_PRE_PMU:
679 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
680 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL);
681 break;
682 case SND_SOC_DAPM_POST_PMU:
683 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
684 RX_EAR_CTL_PA_EAR_PA_EN_MASK,
685 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE);
686 break;
687 case SND_SOC_DAPM_POST_PMD:
688 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
689 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);
690 /* Delay to reduce ear turn off pop */
691 usleep_range(7000, 7100);
692 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
693 RX_EAR_CTL_PA_SEL_MASK, 0);
694 break;
695 }
696 return 0;
697 }
698
699 static const struct reg_default wcd_reg_defaults_2_0[] = {
700 {CDC_A_RX_COM_OCP_CTL, 0xD1},
701 {CDC_A_RX_COM_OCP_COUNT, 0xFF},
702 {CDC_D_SEC_ACCESS, 0xA5},
703 {CDC_D_PERPH_RESET_CTL3, 0x0F},
704 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
705 {CDC_A_NCP_FBCTRL, 0x28},
706 {CDC_A_SPKR_DRV_CTL, 0x69},
707 {CDC_A_SPKR_DRV_DBG, 0x01},
708 {CDC_A_BOOST_EN_CTL, 0x5F},
709 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
710 {CDC_A_SEC_ACCESS, 0xA5},
711 {CDC_A_PERPH_RESET_CTL3, 0x0F},
712 {CDC_A_CURRENT_LIMIT, 0x82},
713 {CDC_A_SPKR_DAC_CTL, 0x03},
714 {CDC_A_SPKR_OCP_CTL, 0xE1},
715 {CDC_A_MASTER_BIAS_CTL, 0x30},
716 };
717
718 static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
719 {
720 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
721 int err, reg;
722
723 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
724 if (err != 0) {
725 dev_err(component->dev, "failed to enable regulators (%d)\n", err);
726 return err;
727 }
728
729 snd_soc_component_init_regmap(component,
730 dev_get_regmap(component->dev->parent, NULL));
731 snd_soc_component_set_drvdata(component, priv);
732 priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1);
733 priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE);
734
735 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
736 priv->pmic_rev, priv->codec_version);
737
738 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
739 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
740
741 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
742 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
743 wcd_reg_defaults_2_0[reg].def);
744
745 priv->component = component;
746
747 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
748 RST_CTL_DIG_SW_RST_N_MASK,
749 RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
750
751 pm8916_wcd_setup_mbhc(priv);
752
753 return 0;
754 }
755
756 static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
757 {
758 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
759
760 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
761 RST_CTL_DIG_SW_RST_N_MASK, 0);
762
763 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
764 priv->supplies);
765 }
766
767 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
768
769 {"PDM_RX1", NULL, "PDM Playback"},
770 {"PDM_RX2", NULL, "PDM Playback"},
771 {"PDM_RX3", NULL, "PDM Playback"},
772 {"PDM Capture", NULL, "PDM_TX"},
773
774 /* ADC Connections */
775 {"PDM_TX", NULL, "ADC2"},
776 {"PDM_TX", NULL, "ADC3"},
777 {"ADC2", NULL, "ADC2 MUX"},
778 {"ADC3", NULL, "ADC2 MUX"},
779 {"ADC2 MUX", "INP2", "ADC2_INP2"},
780 {"ADC2 MUX", "INP3", "ADC2_INP3"},
781
782 {"PDM_TX", NULL, "ADC1"},
783 {"ADC1", NULL, "AMIC1"},
784 {"ADC2_INP2", NULL, "AMIC2"},
785 {"ADC2_INP3", NULL, "AMIC3"},
786
787 /* RDAC Connections */
788 {"HPHR DAC", NULL, "RDAC2 MUX"},
789 {"RDAC2 MUX", "RX1", "PDM_RX1"},
790 {"RDAC2 MUX", "RX2", "PDM_RX2"},
791 {"HPHL DAC", NULL, "PDM_RX1"},
792 {"PDM_RX1", NULL, "RXD1_CLK"},
793 {"PDM_RX2", NULL, "RXD2_CLK"},
794 {"PDM_RX3", NULL, "RXD3_CLK"},
795
796 {"PDM_RX1", NULL, "RXD_PDM_CLK"},
797 {"PDM_RX2", NULL, "RXD_PDM_CLK"},
798 {"PDM_RX3", NULL, "RXD_PDM_CLK"},
799
800 {"ADC1", NULL, "TXD_CLK"},
801 {"ADC2", NULL, "TXD_CLK"},
802 {"ADC3", NULL, "TXD_CLK"},
803
804 {"ADC1", NULL, "TXA_CLK25"},
805 {"ADC2", NULL, "TXA_CLK25"},
806 {"ADC3", NULL, "TXA_CLK25"},
807
808 {"PDM_RX1", NULL, "A_MCLK2"},
809 {"PDM_RX2", NULL, "A_MCLK2"},
810 {"PDM_RX3", NULL, "A_MCLK2"},
811
812 {"PDM_TX", NULL, "A_MCLK2"},
813 {"A_MCLK2", NULL, "A_MCLK"},
814
815 /* Earpiece (RX MIX1) */
816 {"EAR", NULL, "EAR_S"},
817 {"EAR_S", "Switch", "EAR PA"},
818 {"EAR PA", NULL, "RX_BIAS"},
819 {"EAR PA", NULL, "HPHL DAC"},
820 {"EAR PA", NULL, "HPHR DAC"},
821 {"EAR PA", NULL, "EAR CP"},
822
823 /* Headset (RX MIX1 and RX MIX2) */
824 {"HPH_L", NULL, "HPHL PA"},
825 {"HPH_R", NULL, "HPHR PA"},
826
827 {"HPHL DAC", NULL, "EAR_HPHL_CLK"},
828 {"HPHR DAC", NULL, "EAR_HPHR_CLK"},
829
830 {"CP", NULL, "NCP_CLK"},
831
832 {"HPHL PA", NULL, "HPHL"},
833 {"HPHR PA", NULL, "HPHR"},
834 {"HPHL PA", NULL, "CP"},
835 {"HPHL PA", NULL, "RX_BIAS"},
836 {"HPHR PA", NULL, "CP"},
837 {"HPHR PA", NULL, "RX_BIAS"},
838 {"HPHL", "Switch", "HPHL DAC"},
839 {"HPHR", "Switch", "HPHR DAC"},
840
841 {"RX_BIAS", NULL, "DAC_REF"},
842
843 {"SPK_OUT", NULL, "SPK PA"},
844 {"SPK PA", NULL, "RX_BIAS"},
845 {"SPK PA", NULL, "SPKR_CLK"},
846 {"SPK PA", NULL, "SPK DAC"},
847 {"SPK DAC", "Switch", "PDM_RX3"},
848
849 {"MIC_BIAS1", NULL, "INT_LDO_H"},
850 {"MIC_BIAS2", NULL, "INT_LDO_H"},
851 {"MIC_BIAS1", NULL, "vdd-micbias"},
852 {"MIC_BIAS2", NULL, "vdd-micbias"},
853
854 {"MIC BIAS External1", NULL, "MIC_BIAS1"},
855 {"MIC BIAS Internal1", NULL, "MIC_BIAS1"},
856 {"MIC BIAS External2", NULL, "MIC_BIAS2"},
857 {"MIC BIAS Internal2", NULL, "MIC_BIAS2"},
858 {"MIC BIAS Internal3", NULL, "MIC_BIAS1"},
859 };
860
861 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
862
863 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
864 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
865 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
866 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
867
868 SND_SOC_DAPM_INPUT("AMIC1"),
869 SND_SOC_DAPM_INPUT("AMIC3"),
870 SND_SOC_DAPM_INPUT("AMIC2"),
871 SND_SOC_DAPM_OUTPUT("EAR"),
872 SND_SOC_DAPM_OUTPUT("HPH_L"),
873 SND_SOC_DAPM_OUTPUT("HPH_R"),
874
875 /* RX stuff */
876 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
877
878 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
879 0, 0, NULL, 0,
880 pm8916_wcd_analog_enable_ear_pa,
881 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
882 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
883 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
884 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
885
886 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
887 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
888 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
889 0),
890 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
891 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
892 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
893 0),
894 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
895 spkr_switch, ARRAY_SIZE(spkr_switch)),
896
897 /* Speaker */
898 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
899 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
900 6, 0, NULL, 0,
901 pm8916_wcd_analog_enable_spk_pa,
902 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
903 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
904 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
905 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
906
907 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
908 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
909
910 /* TX */
911 SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
912 pm8916_wcd_analog_enable_micbias1,
913 SND_SOC_DAPM_POST_PMU),
914 SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
915 pm8916_wcd_analog_enable_micbias2,
916 SND_SOC_DAPM_POST_PMU),
917
918 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
919 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
920
921 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
922 pm8916_wcd_analog_enable_micbias_int,
923 SND_SOC_DAPM_PRE_PMU),
924 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
925 pm8916_wcd_analog_enable_micbias_int2,
926 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
927 SND_SOC_DAPM_POST_PMD),
928 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
929 pm8916_wcd_analog_enable_micbias_int,
930 SND_SOC_DAPM_PRE_PMU),
931
932 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
933 pm8916_wcd_analog_enable_adc,
934 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
935 SND_SOC_DAPM_POST_PMD),
936 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
937 pm8916_wcd_analog_enable_adc,
938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
939 SND_SOC_DAPM_POST_PMD),
940 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
941 pm8916_wcd_analog_enable_adc,
942 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
943 SND_SOC_DAPM_POST_PMD),
944
945 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
946 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
947
948 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
949 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
950
951 /* Analog path clocks */
952 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
953 0),
954 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
955 0),
956 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
957 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
958
959 /* Digital path clocks */
960
961 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
962 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
963 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
964
965 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
966 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
967 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
968 0),
969
970 /* System Clock source */
971 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
972 /* TX ADC and RX DAC Clock source. */
973 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
974 };
975
976 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
977 struct snd_soc_jack *jack,
978 void *data)
979 {
980 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
981
982 wcd->jack = jack;
983
984 return 0;
985 }
986
987 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
988 {
989 struct pm8916_wcd_analog_priv *priv = arg;
990
991 if (priv->detect_accessory_type) {
992 struct snd_soc_component *component = priv->component;
993 u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1);
994
995 /* check if its BTN0 thats released */
996 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
997 priv->mbhc_btn0_released = true;
998
999 } else {
1000 snd_soc_jack_report(priv->jack, 0, btn_mask);
1001 }
1002
1003 return IRQ_HANDLED;
1004 }
1005
1006 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
1007 {
1008 struct pm8916_wcd_analog_priv *priv = arg;
1009 struct snd_soc_component *component = priv->component;
1010 u32 btn_result;
1011
1012 btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) &
1013 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
1014
1015 switch (btn_result) {
1016 case 0xf:
1017 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
1018 break;
1019 case 0x7:
1020 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
1021 break;
1022 case 0x3:
1023 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
1024 break;
1025 case 0x1:
1026 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
1027 break;
1028 case 0x0:
1029 /* handle BTN_0 specially for type detection */
1030 if (!priv->detect_accessory_type)
1031 snd_soc_jack_report(priv->jack,
1032 SND_JACK_BTN_0, btn_mask);
1033 break;
1034 default:
1035 dev_err(component->dev,
1036 "Unexpected button press result (%x)", btn_result);
1037 break;
1038 }
1039
1040 return IRQ_HANDLED;
1041 }
1042
1043 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
1044 {
1045 struct pm8916_wcd_analog_priv *priv = arg;
1046 struct snd_soc_component *component = priv->component;
1047 bool ins = false;
1048
1049 if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &
1050 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
1051 ins = true;
1052
1053 /* Set the detection type appropriately */
1054 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
1055 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
1056 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
1057
1058
1059 if (ins) { /* hs insertion */
1060 bool micbias_enabled = false;
1061
1062 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &
1063 CDC_A_MICB_2_EN_ENABLE)
1064 micbias_enabled = true;
1065
1066 pm8916_mbhc_configure_bias(priv, micbias_enabled);
1067
1068 /*
1069 * if only a btn0 press event is receive just before
1070 * insert event then its a 3 pole headphone else if
1071 * both press and release event received then its
1072 * a headset.
1073 */
1074 if (priv->mbhc_btn0_released)
1075 snd_soc_jack_report(priv->jack,
1076 SND_JACK_HEADSET, hs_jack_mask);
1077 else
1078 snd_soc_jack_report(priv->jack,
1079 SND_JACK_HEADPHONE, hs_jack_mask);
1080
1081 priv->detect_accessory_type = false;
1082
1083 } else { /* removal */
1084 snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
1085 priv->detect_accessory_type = true;
1086 priv->mbhc_btn0_released = false;
1087 }
1088
1089 return IRQ_HANDLED;
1090 }
1091
1092 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
1093 [0] = {
1094 .name = "pm8916_wcd_analog_pdm_rx",
1095 .id = 0,
1096 .playback = {
1097 .stream_name = "PDM Playback",
1098 .rates = MSM8916_WCD_ANALOG_RATES,
1099 .formats = MSM8916_WCD_ANALOG_FORMATS,
1100 .channels_min = 1,
1101 .channels_max = 3,
1102 },
1103 },
1104 [1] = {
1105 .name = "pm8916_wcd_analog_pdm_tx",
1106 .id = 1,
1107 .capture = {
1108 .stream_name = "PDM Capture",
1109 .rates = MSM8916_WCD_ANALOG_RATES,
1110 .formats = MSM8916_WCD_ANALOG_FORMATS,
1111 .channels_min = 1,
1112 .channels_max = 4,
1113 },
1114 },
1115 };
1116
1117 static const struct snd_soc_component_driver pm8916_wcd_analog = {
1118 .probe = pm8916_wcd_analog_probe,
1119 .remove = pm8916_wcd_analog_remove,
1120 .set_jack = pm8916_wcd_analog_set_jack,
1121 .controls = pm8916_wcd_analog_snd_controls,
1122 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
1123 .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
1124 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
1125 .dapm_routes = pm8916_wcd_analog_audio_map,
1126 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
1127 .idle_bias_on = 1,
1128 .use_pmdown_time = 1,
1129 .endianness = 1,
1130 };
1131
1132 static int pm8916_wcd_analog_parse_dt(struct device *dev,
1133 struct pm8916_wcd_analog_priv *priv)
1134 {
1135 int rval;
1136
1137 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
1138 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1139 else
1140 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1141
1142 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
1143 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1144 else
1145 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1146
1147 of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
1148 &priv->micbias_mv);
1149
1150 if (of_property_read_bool(dev->of_node,
1151 "qcom,hphl-jack-type-normally-open"))
1152 priv->hphl_jack_type_normally_open = true;
1153 else
1154 priv->hphl_jack_type_normally_open = false;
1155
1156 if (of_property_read_bool(dev->of_node,
1157 "qcom,gnd-jack-type-normally-open"))
1158 priv->gnd_jack_type_normally_open = true;
1159 else
1160 priv->gnd_jack_type_normally_open = false;
1161
1162 priv->mbhc_btn_enabled = true;
1163 rval = of_property_read_u32_array(dev->of_node,
1164 "qcom,mbhc-vthreshold-low",
1165 &priv->vref_btn_cs[0],
1166 MBHC_MAX_BUTTONS);
1167 if (rval < 0) {
1168 priv->mbhc_btn_enabled = false;
1169 } else {
1170 rval = of_property_read_u32_array(dev->of_node,
1171 "qcom,mbhc-vthreshold-high",
1172 &priv->vref_btn_micb[0],
1173 MBHC_MAX_BUTTONS);
1174 if (rval < 0)
1175 priv->mbhc_btn_enabled = false;
1176 }
1177
1178 if (!priv->mbhc_btn_enabled)
1179 dev_err(dev,
1180 "DT property missing, MBHC btn detection disabled\n");
1181
1182
1183 return 0;
1184 }
1185
1186 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
1187 {
1188 struct pm8916_wcd_analog_priv *priv;
1189 struct device *dev = &pdev->dev;
1190 int ret, i, irq;
1191
1192 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1193 if (!priv)
1194 return -ENOMEM;
1195
1196 ret = pm8916_wcd_analog_parse_dt(dev, priv);
1197 if (ret < 0)
1198 return ret;
1199
1200 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1201 priv->supplies[i].supply = supply_names[i];
1202
1203 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
1204 priv->supplies);
1205 if (ret) {
1206 dev_err(dev, "Failed to get regulator supplies %d\n", ret);
1207 return ret;
1208 }
1209
1210 irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
1211 if (irq < 0)
1212 return irq;
1213
1214 ret = devm_request_threaded_irq(dev, irq, NULL,
1215 pm8916_mbhc_switch_irq_handler,
1216 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1217 IRQF_ONESHOT,
1218 "mbhc switch irq", priv);
1219 if (ret) {
1220 dev_err(dev, "cannot request mbhc switch irq\n");
1221 return ret;
1222 }
1223
1224 if (priv->mbhc_btn_enabled) {
1225 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
1226 if (irq < 0)
1227 return irq;
1228
1229 ret = devm_request_threaded_irq(dev, irq, NULL,
1230 mbhc_btn_press_irq_handler,
1231 IRQF_TRIGGER_RISING |
1232 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1233 "mbhc btn press irq", priv);
1234 if (ret) {
1235 dev_err(dev, "cannot request mbhc button press irq\n");
1236 return ret;
1237 }
1238
1239 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
1240 if (irq < 0)
1241 return irq;
1242
1243 ret = devm_request_threaded_irq(dev, irq, NULL,
1244 mbhc_btn_release_irq_handler,
1245 IRQF_TRIGGER_RISING |
1246 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1247 "mbhc btn release irq", priv);
1248 if (ret) {
1249 dev_err(dev, "cannot request mbhc button release irq\n");
1250 return ret;
1251 }
1252 }
1253
1254 dev_set_drvdata(dev, priv);
1255
1256 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
1257 pm8916_wcd_analog_dai,
1258 ARRAY_SIZE(pm8916_wcd_analog_dai));
1259 }
1260
1261 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
1262 { .compatible = "qcom,pm8916-wcd-analog-codec", },
1263 { }
1264 };
1265
1266 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
1267
1268 static struct platform_driver pm8916_wcd_analog_spmi_driver = {
1269 .driver = {
1270 .name = "qcom,pm8916-wcd-spmi-codec",
1271 .of_match_table = pm8916_wcd_analog_spmi_match_table,
1272 },
1273 .probe = pm8916_wcd_analog_spmi_probe,
1274 };
1275
1276 module_platform_driver(pm8916_wcd_analog_spmi_driver);
1277
1278 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1279 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
1280 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes