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printf: Remove unused 'bprintf'
[drm/drm-misc.git] / sound / soc / codecs / rt5663.c
blob9d32debd368956278656bf6f4190e18a57102b82
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 *
5 * Copyright 2016 Realtek Semiconductor Corp.
6 * Author: Jack Yu <jack.yu@realtek.com>
7 */
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/pm.h>
13 #include <linux/i2c.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
16 #include <linux/acpi.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/workqueue.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/jack.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27
28 #include "rt5663.h"
29 #include "rl6231.h"
30
31 #define RT5663_DEVICE_ID_2 0x6451
32 #define RT5663_DEVICE_ID_1 0x6406
33
34 #define RT5663_POWER_ON_DELAY_MS 300
35 #define RT5663_SUPPLY_CURRENT_UA 500000
36
37 enum {
38 CODEC_VER_1,
39 CODEC_VER_0,
40 };
41
42 struct impedance_mapping_table {
43 unsigned int imp_min;
44 unsigned int imp_max;
45 unsigned int vol;
46 unsigned int dc_offset_l_manual;
47 unsigned int dc_offset_r_manual;
48 unsigned int dc_offset_l_manual_mic;
49 unsigned int dc_offset_r_manual_mic;
50 };
51
52 static const char *const rt5663_supply_names[] = {
53 "avdd",
54 "cpvdd",
55 };
56
57 struct rt5663_priv {
58 struct snd_soc_component *component;
59 struct rt5663_platform_data pdata;
60 struct regmap *regmap;
61 struct delayed_work jack_detect_work, jd_unplug_work;
62 struct snd_soc_jack *hs_jack;
63 struct timer_list btn_check_timer;
64 struct impedance_mapping_table *imp_table;
65 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
66
67 int codec_ver;
68 int sysclk;
69 int sysclk_src;
70 int lrck;
71
72 int pll_src;
73 int pll_in;
74 int pll_out;
75
76 int jack_type;
77 unsigned int irq;
78 };
79
80 static const struct reg_sequence rt5663_patch_list[] = {
81 { 0x002a, 0x8020 },
82 { 0x0086, 0x0028 },
83 { 0x0100, 0xa020 },
84 { 0x0117, 0x0f28 },
85 { 0x02fb, 0x8089 },
86 };
87
88 static const struct reg_default rt5663_v2_reg[] = {
89 { 0x0000, 0x0000 },
90 { 0x0001, 0xc8c8 },
91 { 0x0002, 0x8080 },
92 { 0x0003, 0x8000 },
93 { 0x0004, 0xc80a },
94 { 0x0005, 0x0000 },
95 { 0x0006, 0x0000 },
96 { 0x0007, 0x0000 },
97 { 0x000a, 0x0000 },
98 { 0x000b, 0x0000 },
99 { 0x000c, 0x0000 },
100 { 0x000d, 0x0000 },
101 { 0x000f, 0x0808 },
102 { 0x0010, 0x4000 },
103 { 0x0011, 0x0000 },
104 { 0x0012, 0x1404 },
105 { 0x0013, 0x1000 },
106 { 0x0014, 0xa00a },
107 { 0x0015, 0x0404 },
108 { 0x0016, 0x0404 },
109 { 0x0017, 0x0011 },
110 { 0x0018, 0xafaf },
111 { 0x0019, 0xafaf },
112 { 0x001a, 0xafaf },
113 { 0x001b, 0x0011 },
114 { 0x001c, 0x2f2f },
115 { 0x001d, 0x2f2f },
116 { 0x001e, 0x2f2f },
117 { 0x001f, 0x0000 },
118 { 0x0020, 0x0000 },
119 { 0x0021, 0x0000 },
120 { 0x0022, 0x5757 },
121 { 0x0023, 0x0039 },
122 { 0x0024, 0x000b },
123 { 0x0026, 0xc0c0 },
124 { 0x0027, 0xc0c0 },
125 { 0x0028, 0xc0c0 },
126 { 0x0029, 0x8080 },
127 { 0x002a, 0xaaaa },
128 { 0x002b, 0xaaaa },
129 { 0x002c, 0xaba8 },
130 { 0x002d, 0x0000 },
131 { 0x002e, 0x0000 },
132 { 0x002f, 0x0000 },
133 { 0x0030, 0x0000 },
134 { 0x0031, 0x5000 },
135 { 0x0032, 0x0000 },
136 { 0x0033, 0x0000 },
137 { 0x0034, 0x0000 },
138 { 0x0035, 0x0000 },
139 { 0x003a, 0x0000 },
140 { 0x003b, 0x0000 },
141 { 0x003c, 0x00ff },
142 { 0x003d, 0x0000 },
143 { 0x003e, 0x00ff },
144 { 0x003f, 0x0000 },
145 { 0x0040, 0x0000 },
146 { 0x0041, 0x00ff },
147 { 0x0042, 0x0000 },
148 { 0x0043, 0x00ff },
149 { 0x0044, 0x0c0c },
150 { 0x0049, 0xc00b },
151 { 0x004a, 0x0000 },
152 { 0x004b, 0x031f },
153 { 0x004d, 0x0000 },
154 { 0x004e, 0x001f },
155 { 0x004f, 0x0000 },
156 { 0x0050, 0x001f },
157 { 0x0052, 0xf000 },
158 { 0x0061, 0x0000 },
159 { 0x0062, 0x0000 },
160 { 0x0063, 0x003e },
161 { 0x0064, 0x0000 },
162 { 0x0065, 0x0000 },
163 { 0x0066, 0x003f },
164 { 0x0067, 0x0000 },
165 { 0x006b, 0x0000 },
166 { 0x006d, 0xff00 },
167 { 0x006e, 0x2808 },
168 { 0x006f, 0x000a },
169 { 0x0070, 0x8000 },
170 { 0x0071, 0x8000 },
171 { 0x0072, 0x8000 },
172 { 0x0073, 0x7000 },
173 { 0x0074, 0x7770 },
174 { 0x0075, 0x0002 },
175 { 0x0076, 0x0001 },
176 { 0x0078, 0x00f0 },
177 { 0x0079, 0x0000 },
178 { 0x007a, 0x0000 },
179 { 0x007b, 0x0000 },
180 { 0x007c, 0x0000 },
181 { 0x007d, 0x0123 },
182 { 0x007e, 0x4500 },
183 { 0x007f, 0x8003 },
184 { 0x0080, 0x0000 },
185 { 0x0081, 0x0000 },
186 { 0x0082, 0x0000 },
187 { 0x0083, 0x0000 },
188 { 0x0084, 0x0000 },
189 { 0x0085, 0x0000 },
190 { 0x0086, 0x0008 },
191 { 0x0087, 0x0000 },
192 { 0x0088, 0x0000 },
193 { 0x0089, 0x0000 },
194 { 0x008a, 0x0000 },
195 { 0x008b, 0x0000 },
196 { 0x008c, 0x0003 },
197 { 0x008e, 0x0060 },
198 { 0x008f, 0x1000 },
199 { 0x0091, 0x0c26 },
200 { 0x0092, 0x0073 },
201 { 0x0093, 0x0000 },
202 { 0x0094, 0x0080 },
203 { 0x0098, 0x0000 },
204 { 0x0099, 0x0000 },
205 { 0x009a, 0x0007 },
206 { 0x009f, 0x0000 },
207 { 0x00a0, 0x0000 },
208 { 0x00a1, 0x0002 },
209 { 0x00a2, 0x0001 },
210 { 0x00a3, 0x0002 },
211 { 0x00a4, 0x0001 },
212 { 0x00ae, 0x2040 },
213 { 0x00af, 0x0000 },
214 { 0x00b6, 0x0000 },
215 { 0x00b7, 0x0000 },
216 { 0x00b8, 0x0000 },
217 { 0x00b9, 0x0000 },
218 { 0x00ba, 0x0002 },
219 { 0x00bb, 0x0000 },
220 { 0x00be, 0x0000 },
221 { 0x00c0, 0x0000 },
222 { 0x00c1, 0x0aaa },
223 { 0x00c2, 0xaa80 },
224 { 0x00c3, 0x0003 },
225 { 0x00c4, 0x0000 },
226 { 0x00d0, 0x0000 },
227 { 0x00d1, 0x2244 },
228 { 0x00d2, 0x0000 },
229 { 0x00d3, 0x3300 },
230 { 0x00d4, 0x2200 },
231 { 0x00d9, 0x0809 },
232 { 0x00da, 0x0000 },
233 { 0x00db, 0x0008 },
234 { 0x00dc, 0x00c0 },
235 { 0x00dd, 0x6724 },
236 { 0x00de, 0x3131 },
237 { 0x00df, 0x0008 },
238 { 0x00e0, 0x4000 },
239 { 0x00e1, 0x3131 },
240 { 0x00e2, 0x600c },
241 { 0x00ea, 0xb320 },
242 { 0x00eb, 0x0000 },
243 { 0x00ec, 0xb300 },
244 { 0x00ed, 0x0000 },
245 { 0x00ee, 0xb320 },
246 { 0x00ef, 0x0000 },
247 { 0x00f0, 0x0201 },
248 { 0x00f1, 0x0ddd },
249 { 0x00f2, 0x0ddd },
250 { 0x00f6, 0x0000 },
251 { 0x00f7, 0x0000 },
252 { 0x00f8, 0x0000 },
253 { 0x00fa, 0x0000 },
254 { 0x00fb, 0x0000 },
255 { 0x00fc, 0x0000 },
256 { 0x00fd, 0x0000 },
257 { 0x00fe, 0x10ec },
258 { 0x00ff, 0x6451 },
259 { 0x0100, 0xaaaa },
260 { 0x0101, 0x000a },
261 { 0x010a, 0xaaaa },
262 { 0x010b, 0xa0a0 },
263 { 0x010c, 0xaeae },
264 { 0x010d, 0xaaaa },
265 { 0x010e, 0xaaaa },
266 { 0x010f, 0xaaaa },
267 { 0x0110, 0xe002 },
268 { 0x0111, 0xa602 },
269 { 0x0112, 0xaaaa },
270 { 0x0113, 0x2000 },
271 { 0x0117, 0x0f00 },
272 { 0x0125, 0x0420 },
273 { 0x0132, 0x0000 },
274 { 0x0133, 0x0000 },
275 { 0x0136, 0x5555 },
276 { 0x0137, 0x5540 },
277 { 0x0138, 0x3700 },
278 { 0x0139, 0x79a1 },
279 { 0x013a, 0x2020 },
280 { 0x013b, 0x2020 },
281 { 0x013c, 0x2005 },
282 { 0x013f, 0x0000 },
283 { 0x0145, 0x0002 },
284 { 0x0146, 0x0000 },
285 { 0x0147, 0x0000 },
286 { 0x0148, 0x0000 },
287 { 0x0160, 0x4ec0 },
288 { 0x0161, 0x0080 },
289 { 0x0162, 0x0200 },
290 { 0x0163, 0x0800 },
291 { 0x0164, 0x0000 },
292 { 0x0165, 0x0000 },
293 { 0x0166, 0x0000 },
294 { 0x0167, 0x000f },
295 { 0x0168, 0x000f },
296 { 0x0170, 0x4e80 },
297 { 0x0171, 0x0080 },
298 { 0x0172, 0x0200 },
299 { 0x0173, 0x0800 },
300 { 0x0174, 0x00ff },
301 { 0x0175, 0x0000 },
302 { 0x0190, 0x4131 },
303 { 0x0191, 0x4131 },
304 { 0x0192, 0x4131 },
305 { 0x0193, 0x4131 },
306 { 0x0194, 0x0000 },
307 { 0x0195, 0x0000 },
308 { 0x0196, 0x0000 },
309 { 0x0197, 0x0000 },
310 { 0x0198, 0x0000 },
311 { 0x0199, 0x0000 },
312 { 0x01a0, 0x1e64 },
313 { 0x01a1, 0x06a3 },
314 { 0x01a2, 0x0000 },
315 { 0x01a3, 0x0000 },
316 { 0x01a4, 0x0000 },
317 { 0x01a5, 0x0000 },
318 { 0x01a6, 0x0000 },
319 { 0x01a7, 0x0000 },
320 { 0x01a8, 0x0000 },
321 { 0x01a9, 0x0000 },
322 { 0x01aa, 0x0000 },
323 { 0x01ab, 0x0000 },
324 { 0x01b5, 0x0000 },
325 { 0x01b6, 0x01c3 },
326 { 0x01b7, 0x02a0 },
327 { 0x01b8, 0x03e9 },
328 { 0x01b9, 0x1389 },
329 { 0x01ba, 0xc351 },
330 { 0x01bb, 0x0009 },
331 { 0x01bc, 0x0018 },
332 { 0x01bd, 0x002a },
333 { 0x01be, 0x004c },
334 { 0x01bf, 0x0097 },
335 { 0x01c0, 0x433d },
336 { 0x01c1, 0x0000 },
337 { 0x01c2, 0x0000 },
338 { 0x01c3, 0x0000 },
339 { 0x01c4, 0x0000 },
340 { 0x01c5, 0x0000 },
341 { 0x01c6, 0x0000 },
342 { 0x01c7, 0x0000 },
343 { 0x01c8, 0x40af },
344 { 0x01c9, 0x0702 },
345 { 0x01ca, 0x0000 },
346 { 0x01cb, 0x0000 },
347 { 0x01cc, 0x5757 },
348 { 0x01cd, 0x5757 },
349 { 0x01ce, 0x5757 },
350 { 0x01cf, 0x5757 },
351 { 0x01d0, 0x5757 },
352 { 0x01d1, 0x5757 },
353 { 0x01d2, 0x5757 },
354 { 0x01d3, 0x5757 },
355 { 0x01d4, 0x5757 },
356 { 0x01d5, 0x5757 },
357 { 0x01d6, 0x003c },
358 { 0x01da, 0x0000 },
359 { 0x01db, 0x0000 },
360 { 0x01dc, 0x0000 },
361 { 0x01de, 0x7c00 },
362 { 0x01df, 0x0320 },
363 { 0x01e0, 0x06a1 },
364 { 0x01e1, 0x0000 },
365 { 0x01e2, 0x0000 },
366 { 0x01e3, 0x0000 },
367 { 0x01e4, 0x0000 },
368 { 0x01e5, 0x0000 },
369 { 0x01e6, 0x0001 },
370 { 0x01e7, 0x0000 },
371 { 0x01e8, 0x0000 },
372 { 0x01ea, 0x0000 },
373 { 0x01eb, 0x0000 },
374 { 0x01ec, 0x0000 },
375 { 0x01ed, 0x0000 },
376 { 0x01ee, 0x0000 },
377 { 0x01ef, 0x0000 },
378 { 0x01f0, 0x0000 },
379 { 0x01f1, 0x0000 },
380 { 0x01f2, 0x0000 },
381 { 0x01f3, 0x0000 },
382 { 0x01f4, 0x0000 },
383 { 0x0200, 0x0000 },
384 { 0x0201, 0x0000 },
385 { 0x0202, 0x0000 },
386 { 0x0203, 0x0000 },
387 { 0x0204, 0x0000 },
388 { 0x0205, 0x0000 },
389 { 0x0206, 0x0000 },
390 { 0x0207, 0x0000 },
391 { 0x0208, 0x0000 },
392 { 0x0210, 0x60b1 },
393 { 0x0211, 0xa000 },
394 { 0x0212, 0x024c },
395 { 0x0213, 0xf7ff },
396 { 0x0214, 0x024c },
397 { 0x0215, 0x0102 },
398 { 0x0216, 0x00a3 },
399 { 0x0217, 0x0048 },
400 { 0x0218, 0x92c0 },
401 { 0x0219, 0x0000 },
402 { 0x021a, 0x00c8 },
403 { 0x021b, 0x0020 },
404 { 0x02fa, 0x0000 },
405 { 0x02fb, 0x0000 },
406 { 0x02fc, 0x0000 },
407 { 0x02ff, 0x0110 },
408 { 0x0300, 0x001f },
409 { 0x0301, 0x032c },
410 { 0x0302, 0x5f21 },
411 { 0x0303, 0x4000 },
412 { 0x0304, 0x4000 },
413 { 0x0305, 0x06d5 },
414 { 0x0306, 0x8000 },
415 { 0x0307, 0x0700 },
416 { 0x0310, 0x4560 },
417 { 0x0311, 0xa4a8 },
418 { 0x0312, 0x7418 },
419 { 0x0313, 0x0000 },
420 { 0x0314, 0x0006 },
421 { 0x0315, 0xffff },
422 { 0x0316, 0xc400 },
423 { 0x0317, 0x0000 },
424 { 0x0330, 0x00a6 },
425 { 0x0331, 0x04c3 },
426 { 0x0332, 0x27c8 },
427 { 0x0333, 0xbf50 },
428 { 0x0334, 0x0045 },
429 { 0x0335, 0x0007 },
430 { 0x0336, 0x7418 },
431 { 0x0337, 0x0501 },
432 { 0x0338, 0x0000 },
433 { 0x0339, 0x0010 },
434 { 0x033a, 0x1010 },
435 { 0x03c0, 0x7e00 },
436 { 0x03c1, 0x8000 },
437 { 0x03c2, 0x8000 },
438 { 0x03c3, 0x8000 },
439 { 0x03c4, 0x8000 },
440 { 0x03c5, 0x8000 },
441 { 0x03c6, 0x8000 },
442 { 0x03c7, 0x8000 },
443 { 0x03c8, 0x8000 },
444 { 0x03c9, 0x8000 },
445 { 0x03ca, 0x8000 },
446 { 0x03cb, 0x8000 },
447 { 0x03cc, 0x8000 },
448 { 0x03d0, 0x0000 },
449 { 0x03d1, 0x0000 },
450 { 0x03d2, 0x0000 },
451 { 0x03d3, 0x0000 },
452 { 0x03d4, 0x2000 },
453 { 0x03d5, 0x2000 },
454 { 0x03d6, 0x0000 },
455 { 0x03d7, 0x0000 },
456 { 0x03d8, 0x2000 },
457 { 0x03d9, 0x2000 },
458 { 0x03da, 0x2000 },
459 { 0x03db, 0x2000 },
460 { 0x03dc, 0x0000 },
461 { 0x03dd, 0x0000 },
462 { 0x03de, 0x0000 },
463 { 0x03df, 0x2000 },
464 { 0x03e0, 0x0000 },
465 { 0x03e1, 0x0000 },
466 { 0x03e2, 0x0000 },
467 { 0x03e3, 0x0000 },
468 { 0x03e4, 0x0000 },
469 { 0x03e5, 0x0000 },
470 { 0x03e6, 0x0000 },
471 { 0x03e7, 0x0000 },
472 { 0x03e8, 0x0000 },
473 { 0x03e9, 0x0000 },
474 { 0x03ea, 0x0000 },
475 { 0x03eb, 0x0000 },
476 { 0x03ec, 0x0000 },
477 { 0x03ed, 0x0000 },
478 { 0x03ee, 0x0000 },
479 { 0x03ef, 0x0000 },
480 { 0x03f0, 0x0800 },
481 { 0x03f1, 0x0800 },
482 { 0x03f2, 0x0800 },
483 { 0x03f3, 0x0800 },
484 { 0x03fe, 0x0000 },
485 { 0x03ff, 0x0000 },
486 { 0x07f0, 0x0000 },
487 { 0x07fa, 0x0000 },
488 };
489
490 static const struct reg_default rt5663_reg[] = {
491 { 0x0000, 0x0000 },
492 { 0x0002, 0x0008 },
493 { 0x0005, 0x1000 },
494 { 0x0006, 0x1000 },
495 { 0x000a, 0x0000 },
496 { 0x0010, 0x000f },
497 { 0x0015, 0x42f1 },
498 { 0x0016, 0x0000 },
499 { 0x0018, 0x000b },
500 { 0x0019, 0xafaf },
501 { 0x001c, 0x2f2f },
502 { 0x001f, 0x0000 },
503 { 0x0022, 0x5757 },
504 { 0x0023, 0x0039 },
505 { 0x0026, 0xc0c0 },
506 { 0x0029, 0x8080 },
507 { 0x002a, 0x8020 },
508 { 0x002c, 0x000c },
509 { 0x002d, 0x0000 },
510 { 0x0040, 0x0808 },
511 { 0x0061, 0x0000 },
512 { 0x0062, 0x0000 },
513 { 0x0063, 0x003e },
514 { 0x0064, 0x0000 },
515 { 0x0065, 0x0000 },
516 { 0x0066, 0x0000 },
517 { 0x006b, 0x0000 },
518 { 0x006e, 0x0000 },
519 { 0x006f, 0x0000 },
520 { 0x0070, 0x8020 },
521 { 0x0073, 0x1000 },
522 { 0x0074, 0xe400 },
523 { 0x0075, 0x0002 },
524 { 0x0076, 0x0001 },
525 { 0x0077, 0x00f0 },
526 { 0x0078, 0x0000 },
527 { 0x0079, 0x0000 },
528 { 0x007a, 0x0123 },
529 { 0x007b, 0x8003 },
530 { 0x0080, 0x0000 },
531 { 0x0081, 0x0000 },
532 { 0x0082, 0x0000 },
533 { 0x0083, 0x0000 },
534 { 0x0084, 0x0000 },
535 { 0x0086, 0x0028 },
536 { 0x0087, 0x0000 },
537 { 0x008a, 0x0000 },
538 { 0x008b, 0x0000 },
539 { 0x008c, 0x0003 },
540 { 0x008e, 0x0008 },
541 { 0x008f, 0x1000 },
542 { 0x0090, 0x0646 },
543 { 0x0091, 0x0e3e },
544 { 0x0092, 0x1071 },
545 { 0x0093, 0x0000 },
546 { 0x0094, 0x0080 },
547 { 0x0097, 0x0000 },
548 { 0x0098, 0x0000 },
549 { 0x009a, 0x0000 },
550 { 0x009f, 0x0000 },
551 { 0x00ae, 0x6000 },
552 { 0x00af, 0x0000 },
553 { 0x00b6, 0x0000 },
554 { 0x00b7, 0x0000 },
555 { 0x00b8, 0x0000 },
556 { 0x00ba, 0x0000 },
557 { 0x00bb, 0x0000 },
558 { 0x00be, 0x0000 },
559 { 0x00bf, 0x0000 },
560 { 0x00c0, 0x0000 },
561 { 0x00c1, 0x0000 },
562 { 0x00c5, 0x0000 },
563 { 0x00cb, 0xa02f },
564 { 0x00cc, 0x0000 },
565 { 0x00cd, 0x0e02 },
566 { 0x00d9, 0x08f9 },
567 { 0x00db, 0x0008 },
568 { 0x00dc, 0x00c0 },
569 { 0x00dd, 0x6729 },
570 { 0x00de, 0x3131 },
571 { 0x00df, 0x0008 },
572 { 0x00e0, 0x4000 },
573 { 0x00e1, 0x3131 },
574 { 0x00e2, 0x0043 },
575 { 0x00e4, 0x400b },
576 { 0x00e5, 0x8031 },
577 { 0x00e6, 0x3080 },
578 { 0x00e7, 0x4100 },
579 { 0x00e8, 0x1400 },
580 { 0x00e9, 0xe00a },
581 { 0x00ea, 0x0404 },
582 { 0x00eb, 0x0404 },
583 { 0x00ec, 0xb320 },
584 { 0x00ed, 0x0000 },
585 { 0x00f4, 0x0000 },
586 { 0x00f6, 0x0000 },
587 { 0x00f8, 0x0000 },
588 { 0x00fa, 0x8000 },
589 { 0x00fd, 0x0001 },
590 { 0x00fe, 0x10ec },
591 { 0x00ff, 0x6406 },
592 { 0x0100, 0xa020 },
593 { 0x0108, 0x4444 },
594 { 0x0109, 0x4444 },
595 { 0x010a, 0xaaaa },
596 { 0x010b, 0x00a0 },
597 { 0x010c, 0x8aaa },
598 { 0x010d, 0xaaaa },
599 { 0x010e, 0x2aaa },
600 { 0x010f, 0x002a },
601 { 0x0110, 0xa0a4 },
602 { 0x0111, 0x4602 },
603 { 0x0112, 0x0101 },
604 { 0x0113, 0x2000 },
605 { 0x0114, 0x0000 },
606 { 0x0116, 0x0000 },
607 { 0x0117, 0x0f28 },
608 { 0x0118, 0x0006 },
609 { 0x0125, 0x2424 },
610 { 0x0126, 0x5550 },
611 { 0x0127, 0x0400 },
612 { 0x0128, 0x7711 },
613 { 0x0132, 0x0004 },
614 { 0x0137, 0x5441 },
615 { 0x0139, 0x79a1 },
616 { 0x013a, 0x30c0 },
617 { 0x013b, 0x2000 },
618 { 0x013c, 0x2005 },
619 { 0x013d, 0x30c0 },
620 { 0x013e, 0x0000 },
621 { 0x0140, 0x3700 },
622 { 0x0141, 0x1f00 },
623 { 0x0144, 0x0000 },
624 { 0x0145, 0x0002 },
625 { 0x0146, 0x0000 },
626 { 0x0160, 0x0e80 },
627 { 0x0161, 0x0080 },
628 { 0x0162, 0x0200 },
629 { 0x0163, 0x0800 },
630 { 0x0164, 0x0000 },
631 { 0x0165, 0x0000 },
632 { 0x0166, 0x0000 },
633 { 0x0167, 0x1417 },
634 { 0x0168, 0x0017 },
635 { 0x0169, 0x0017 },
636 { 0x0180, 0x2000 },
637 { 0x0181, 0x0000 },
638 { 0x0182, 0x0000 },
639 { 0x0183, 0x2000 },
640 { 0x0184, 0x0000 },
641 { 0x0185, 0x0000 },
642 { 0x01b0, 0x4b30 },
643 { 0x01b1, 0x0000 },
644 { 0x01b2, 0xd870 },
645 { 0x01b3, 0x0000 },
646 { 0x01b4, 0x0030 },
647 { 0x01b5, 0x5757 },
648 { 0x01b6, 0x5757 },
649 { 0x01b7, 0x5757 },
650 { 0x01b8, 0x5757 },
651 { 0x01c0, 0x433d },
652 { 0x01c1, 0x0540 },
653 { 0x01c2, 0x0000 },
654 { 0x01c3, 0x0000 },
655 { 0x01c4, 0x0000 },
656 { 0x01c5, 0x0009 },
657 { 0x01c6, 0x0018 },
658 { 0x01c7, 0x002a },
659 { 0x01c8, 0x004c },
660 { 0x01c9, 0x0097 },
661 { 0x01ca, 0x01c3 },
662 { 0x01cb, 0x03e9 },
663 { 0x01cc, 0x1389 },
664 { 0x01cd, 0xc351 },
665 { 0x01ce, 0x0000 },
666 { 0x01cf, 0x0000 },
667 { 0x01d0, 0x0000 },
668 { 0x01d1, 0x0000 },
669 { 0x01d2, 0x0000 },
670 { 0x01d3, 0x003c },
671 { 0x01d4, 0x5757 },
672 { 0x01d5, 0x5757 },
673 { 0x01d6, 0x5757 },
674 { 0x01d7, 0x5757 },
675 { 0x01d8, 0x5757 },
676 { 0x01d9, 0x5757 },
677 { 0x01da, 0x0000 },
678 { 0x01db, 0x0000 },
679 { 0x01dd, 0x0009 },
680 { 0x01de, 0x7f00 },
681 { 0x01df, 0x00c8 },
682 { 0x01e0, 0x0691 },
683 { 0x01e1, 0x0000 },
684 { 0x01e2, 0x0000 },
685 { 0x01e3, 0x0000 },
686 { 0x01e4, 0x0000 },
687 { 0x01e5, 0x0040 },
688 { 0x01e6, 0x0000 },
689 { 0x01e7, 0x0000 },
690 { 0x01e8, 0x0000 },
691 { 0x01ea, 0x0000 },
692 { 0x01eb, 0x0000 },
693 { 0x01ec, 0x0000 },
694 { 0x01ed, 0x0000 },
695 { 0x01ee, 0x0000 },
696 { 0x01ef, 0x0000 },
697 { 0x01f0, 0x0000 },
698 { 0x01f1, 0x0000 },
699 { 0x01f2, 0x0000 },
700 { 0x0200, 0x0000 },
701 { 0x0201, 0x2244 },
702 { 0x0202, 0xaaaa },
703 { 0x0250, 0x8010 },
704 { 0x0251, 0x0000 },
705 { 0x0252, 0x028a },
706 { 0x02fa, 0x0000 },
707 { 0x02fb, 0x8089 },
708 { 0x02fc, 0x0300 },
709 { 0x0300, 0x0000 },
710 { 0x03d0, 0x0000 },
711 { 0x03d1, 0x0000 },
712 { 0x03d2, 0x0000 },
713 { 0x03d3, 0x0000 },
714 { 0x03d4, 0x2000 },
715 { 0x03d5, 0x2000 },
716 { 0x03d6, 0x0000 },
717 { 0x03d7, 0x0000 },
718 { 0x03d8, 0x2000 },
719 { 0x03d9, 0x2000 },
720 { 0x03da, 0x2000 },
721 { 0x03db, 0x2000 },
722 { 0x03dc, 0x0000 },
723 { 0x03dd, 0x0000 },
724 { 0x03de, 0x0000 },
725 { 0x03df, 0x2000 },
726 { 0x03e0, 0x0000 },
727 { 0x03e1, 0x0000 },
728 { 0x03e2, 0x0000 },
729 { 0x03e3, 0x0000 },
730 { 0x03e4, 0x0000 },
731 { 0x03e5, 0x0000 },
732 { 0x03e6, 0x0000 },
733 { 0x03e7, 0x0000 },
734 { 0x03e8, 0x0000 },
735 { 0x03e9, 0x0000 },
736 { 0x03ea, 0x0000 },
737 { 0x03eb, 0x0000 },
738 { 0x03ec, 0x0000 },
739 { 0x03ed, 0x0000 },
740 { 0x03ee, 0x0000 },
741 { 0x03ef, 0x0000 },
742 { 0x03f0, 0x0800 },
743 { 0x03f1, 0x0800 },
744 { 0x03f2, 0x0800 },
745 { 0x03f3, 0x0800 },
746 };
747
748 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
749 {
750 switch (reg) {
751 case RT5663_RESET:
752 case RT5663_SIL_DET_CTL:
753 case RT5663_HP_IMP_GAIN_2:
754 case RT5663_AD_DA_MIXER:
755 case RT5663_FRAC_DIV_2:
756 case RT5663_MICBIAS_1:
757 case RT5663_ASRC_11_2:
758 case RT5663_ADC_EQ_1:
759 case RT5663_INT_ST_1:
760 case RT5663_INT_ST_2:
761 case RT5663_GPIO_STA1:
762 case RT5663_SIN_GEN_1:
763 case RT5663_IL_CMD_1:
764 case RT5663_IL_CMD_5:
765 case RT5663_IL_CMD_PWRSAV1:
766 case RT5663_EM_JACK_TYPE_1:
767 case RT5663_EM_JACK_TYPE_2:
768 case RT5663_EM_JACK_TYPE_3:
769 case RT5663_JD_CTRL2:
770 case RT5663_VENDOR_ID:
771 case RT5663_VENDOR_ID_1:
772 case RT5663_VENDOR_ID_2:
773 case RT5663_PLL_INT_REG:
774 case RT5663_SOFT_RAMP:
775 case RT5663_STO_DRE_1:
776 case RT5663_STO_DRE_5:
777 case RT5663_STO_DRE_6:
778 case RT5663_STO_DRE_7:
779 case RT5663_MIC_DECRO_1:
780 case RT5663_MIC_DECRO_4:
781 case RT5663_HP_IMP_SEN_1:
782 case RT5663_HP_IMP_SEN_3:
783 case RT5663_HP_IMP_SEN_4:
784 case RT5663_HP_IMP_SEN_5:
785 case RT5663_HP_CALIB_1_1:
786 case RT5663_HP_CALIB_9:
787 case RT5663_HP_CALIB_ST1:
788 case RT5663_HP_CALIB_ST2:
789 case RT5663_HP_CALIB_ST3:
790 case RT5663_HP_CALIB_ST4:
791 case RT5663_HP_CALIB_ST5:
792 case RT5663_HP_CALIB_ST6:
793 case RT5663_HP_CALIB_ST7:
794 case RT5663_HP_CALIB_ST8:
795 case RT5663_HP_CALIB_ST9:
796 case RT5663_ANA_JD:
797 return true;
798 default:
799 return false;
800 }
801 }
802
803 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
804 {
805 switch (reg) {
806 case RT5663_RESET:
807 case RT5663_HP_OUT_EN:
808 case RT5663_HP_LCH_DRE:
809 case RT5663_HP_RCH_DRE:
810 case RT5663_CALIB_BST:
811 case RT5663_RECMIX:
812 case RT5663_SIL_DET_CTL:
813 case RT5663_PWR_SAV_SILDET:
814 case RT5663_SIDETONE_CTL:
815 case RT5663_STO1_DAC_DIG_VOL:
816 case RT5663_STO1_ADC_DIG_VOL:
817 case RT5663_STO1_BOOST:
818 case RT5663_HP_IMP_GAIN_1:
819 case RT5663_HP_IMP_GAIN_2:
820 case RT5663_STO1_ADC_MIXER:
821 case RT5663_AD_DA_MIXER:
822 case RT5663_STO_DAC_MIXER:
823 case RT5663_DIG_SIDE_MIXER:
824 case RT5663_BYPASS_STO_DAC:
825 case RT5663_CALIB_REC_MIX:
826 case RT5663_PWR_DIG_1:
827 case RT5663_PWR_DIG_2:
828 case RT5663_PWR_ANLG_1:
829 case RT5663_PWR_ANLG_2:
830 case RT5663_PWR_ANLG_3:
831 case RT5663_PWR_MIXER:
832 case RT5663_SIG_CLK_DET:
833 case RT5663_PRE_DIV_GATING_1:
834 case RT5663_PRE_DIV_GATING_2:
835 case RT5663_I2S1_SDP:
836 case RT5663_ADDA_CLK_1:
837 case RT5663_ADDA_RST:
838 case RT5663_FRAC_DIV_1:
839 case RT5663_FRAC_DIV_2:
840 case RT5663_TDM_1:
841 case RT5663_TDM_2:
842 case RT5663_TDM_3:
843 case RT5663_TDM_4:
844 case RT5663_TDM_5:
845 case RT5663_GLB_CLK:
846 case RT5663_PLL_1:
847 case RT5663_PLL_2:
848 case RT5663_ASRC_1:
849 case RT5663_ASRC_2:
850 case RT5663_ASRC_4:
851 case RT5663_DUMMY_REG:
852 case RT5663_ASRC_8:
853 case RT5663_ASRC_9:
854 case RT5663_ASRC_11:
855 case RT5663_DEPOP_1:
856 case RT5663_DEPOP_2:
857 case RT5663_DEPOP_3:
858 case RT5663_HP_CHARGE_PUMP_1:
859 case RT5663_HP_CHARGE_PUMP_2:
860 case RT5663_MICBIAS_1:
861 case RT5663_RC_CLK:
862 case RT5663_ASRC_11_2:
863 case RT5663_DUMMY_REG_2:
864 case RT5663_REC_PATH_GAIN:
865 case RT5663_AUTO_1MRC_CLK:
866 case RT5663_ADC_EQ_1:
867 case RT5663_ADC_EQ_2:
868 case RT5663_IRQ_1:
869 case RT5663_IRQ_2:
870 case RT5663_IRQ_3:
871 case RT5663_IRQ_4:
872 case RT5663_IRQ_5:
873 case RT5663_INT_ST_1:
874 case RT5663_INT_ST_2:
875 case RT5663_GPIO_1:
876 case RT5663_GPIO_2:
877 case RT5663_GPIO_STA1:
878 case RT5663_SIN_GEN_1:
879 case RT5663_SIN_GEN_2:
880 case RT5663_SIN_GEN_3:
881 case RT5663_SOF_VOL_ZC1:
882 case RT5663_IL_CMD_1:
883 case RT5663_IL_CMD_2:
884 case RT5663_IL_CMD_3:
885 case RT5663_IL_CMD_4:
886 case RT5663_IL_CMD_5:
887 case RT5663_IL_CMD_6:
888 case RT5663_IL_CMD_7:
889 case RT5663_IL_CMD_8:
890 case RT5663_IL_CMD_PWRSAV1:
891 case RT5663_IL_CMD_PWRSAV2:
892 case RT5663_EM_JACK_TYPE_1:
893 case RT5663_EM_JACK_TYPE_2:
894 case RT5663_EM_JACK_TYPE_3:
895 case RT5663_EM_JACK_TYPE_4:
896 case RT5663_EM_JACK_TYPE_5:
897 case RT5663_EM_JACK_TYPE_6:
898 case RT5663_STO1_HPF_ADJ1:
899 case RT5663_STO1_HPF_ADJ2:
900 case RT5663_FAST_OFF_MICBIAS:
901 case RT5663_JD_CTRL1:
902 case RT5663_JD_CTRL2:
903 case RT5663_DIG_MISC:
904 case RT5663_VENDOR_ID:
905 case RT5663_VENDOR_ID_1:
906 case RT5663_VENDOR_ID_2:
907 case RT5663_DIG_VOL_ZCD:
908 case RT5663_ANA_BIAS_CUR_1:
909 case RT5663_ANA_BIAS_CUR_2:
910 case RT5663_ANA_BIAS_CUR_3:
911 case RT5663_ANA_BIAS_CUR_4:
912 case RT5663_ANA_BIAS_CUR_5:
913 case RT5663_ANA_BIAS_CUR_6:
914 case RT5663_BIAS_CUR_5:
915 case RT5663_BIAS_CUR_6:
916 case RT5663_BIAS_CUR_7:
917 case RT5663_BIAS_CUR_8:
918 case RT5663_DACREF_LDO:
919 case RT5663_DUMMY_REG_3:
920 case RT5663_BIAS_CUR_9:
921 case RT5663_DUMMY_REG_4:
922 case RT5663_VREFADJ_OP:
923 case RT5663_VREF_RECMIX:
924 case RT5663_CHARGE_PUMP_1:
925 case RT5663_CHARGE_PUMP_1_2:
926 case RT5663_CHARGE_PUMP_1_3:
927 case RT5663_CHARGE_PUMP_2:
928 case RT5663_DIG_IN_PIN1:
929 case RT5663_PAD_DRV_CTL:
930 case RT5663_PLL_INT_REG:
931 case RT5663_CHOP_DAC_L:
932 case RT5663_CHOP_ADC:
933 case RT5663_CALIB_ADC:
934 case RT5663_CHOP_DAC_R:
935 case RT5663_DUMMY_CTL_DACLR:
936 case RT5663_DUMMY_REG_5:
937 case RT5663_SOFT_RAMP:
938 case RT5663_TEST_MODE_1:
939 case RT5663_TEST_MODE_2:
940 case RT5663_TEST_MODE_3:
941 case RT5663_STO_DRE_1:
942 case RT5663_STO_DRE_2:
943 case RT5663_STO_DRE_3:
944 case RT5663_STO_DRE_4:
945 case RT5663_STO_DRE_5:
946 case RT5663_STO_DRE_6:
947 case RT5663_STO_DRE_7:
948 case RT5663_STO_DRE_8:
949 case RT5663_STO_DRE_9:
950 case RT5663_STO_DRE_10:
951 case RT5663_MIC_DECRO_1:
952 case RT5663_MIC_DECRO_2:
953 case RT5663_MIC_DECRO_3:
954 case RT5663_MIC_DECRO_4:
955 case RT5663_MIC_DECRO_5:
956 case RT5663_MIC_DECRO_6:
957 case RT5663_HP_DECRO_1:
958 case RT5663_HP_DECRO_2:
959 case RT5663_HP_DECRO_3:
960 case RT5663_HP_DECRO_4:
961 case RT5663_HP_DECOUP:
962 case RT5663_HP_IMP_SEN_MAP8:
963 case RT5663_HP_IMP_SEN_MAP9:
964 case RT5663_HP_IMP_SEN_MAP10:
965 case RT5663_HP_IMP_SEN_MAP11:
966 case RT5663_HP_IMP_SEN_1:
967 case RT5663_HP_IMP_SEN_2:
968 case RT5663_HP_IMP_SEN_3:
969 case RT5663_HP_IMP_SEN_4:
970 case RT5663_HP_IMP_SEN_5:
971 case RT5663_HP_IMP_SEN_6:
972 case RT5663_HP_IMP_SEN_7:
973 case RT5663_HP_IMP_SEN_8:
974 case RT5663_HP_IMP_SEN_9:
975 case RT5663_HP_IMP_SEN_10:
976 case RT5663_HP_IMP_SEN_11:
977 case RT5663_HP_IMP_SEN_12:
978 case RT5663_HP_IMP_SEN_13:
979 case RT5663_HP_IMP_SEN_14:
980 case RT5663_HP_IMP_SEN_15:
981 case RT5663_HP_IMP_SEN_16:
982 case RT5663_HP_IMP_SEN_17:
983 case RT5663_HP_IMP_SEN_18:
984 case RT5663_HP_IMP_SEN_19:
985 case RT5663_HP_IMPSEN_DIG5:
986 case RT5663_HP_IMPSEN_MAP1:
987 case RT5663_HP_IMPSEN_MAP2:
988 case RT5663_HP_IMPSEN_MAP3:
989 case RT5663_HP_IMPSEN_MAP4:
990 case RT5663_HP_IMPSEN_MAP5:
991 case RT5663_HP_IMPSEN_MAP7:
992 case RT5663_HP_LOGIC_1:
993 case RT5663_HP_LOGIC_2:
994 case RT5663_HP_CALIB_1:
995 case RT5663_HP_CALIB_1_1:
996 case RT5663_HP_CALIB_2:
997 case RT5663_HP_CALIB_3:
998 case RT5663_HP_CALIB_4:
999 case RT5663_HP_CALIB_5:
1000 case RT5663_HP_CALIB_5_1:
1001 case RT5663_HP_CALIB_6:
1002 case RT5663_HP_CALIB_7:
1003 case RT5663_HP_CALIB_9:
1004 case RT5663_HP_CALIB_10:
1005 case RT5663_HP_CALIB_11:
1006 case RT5663_HP_CALIB_ST1:
1007 case RT5663_HP_CALIB_ST2:
1008 case RT5663_HP_CALIB_ST3:
1009 case RT5663_HP_CALIB_ST4:
1010 case RT5663_HP_CALIB_ST5:
1011 case RT5663_HP_CALIB_ST6:
1012 case RT5663_HP_CALIB_ST7:
1013 case RT5663_HP_CALIB_ST8:
1014 case RT5663_HP_CALIB_ST9:
1015 case RT5663_HP_AMP_DET:
1016 case RT5663_DUMMY_REG_6:
1017 case RT5663_HP_BIAS:
1018 case RT5663_CBJ_1:
1019 case RT5663_CBJ_2:
1020 case RT5663_CBJ_3:
1021 case RT5663_DUMMY_1:
1022 case RT5663_DUMMY_2:
1023 case RT5663_DUMMY_3:
1024 case RT5663_ANA_JD:
1025 case RT5663_ADC_LCH_LPF1_A1:
1026 case RT5663_ADC_RCH_LPF1_A1:
1027 case RT5663_ADC_LCH_LPF1_H0:
1028 case RT5663_ADC_RCH_LPF1_H0:
1029 case RT5663_ADC_LCH_BPF1_A1:
1030 case RT5663_ADC_RCH_BPF1_A1:
1031 case RT5663_ADC_LCH_BPF1_A2:
1032 case RT5663_ADC_RCH_BPF1_A2:
1033 case RT5663_ADC_LCH_BPF1_H0:
1034 case RT5663_ADC_RCH_BPF1_H0:
1035 case RT5663_ADC_LCH_BPF2_A1:
1036 case RT5663_ADC_RCH_BPF2_A1:
1037 case RT5663_ADC_LCH_BPF2_A2:
1038 case RT5663_ADC_RCH_BPF2_A2:
1039 case RT5663_ADC_LCH_BPF2_H0:
1040 case RT5663_ADC_RCH_BPF2_H0:
1041 case RT5663_ADC_LCH_BPF3_A1:
1042 case RT5663_ADC_RCH_BPF3_A1:
1043 case RT5663_ADC_LCH_BPF3_A2:
1044 case RT5663_ADC_RCH_BPF3_A2:
1045 case RT5663_ADC_LCH_BPF3_H0:
1046 case RT5663_ADC_RCH_BPF3_H0:
1047 case RT5663_ADC_LCH_BPF4_A1:
1048 case RT5663_ADC_RCH_BPF4_A1:
1049 case RT5663_ADC_LCH_BPF4_A2:
1050 case RT5663_ADC_RCH_BPF4_A2:
1051 case RT5663_ADC_LCH_BPF4_H0:
1052 case RT5663_ADC_RCH_BPF4_H0:
1053 case RT5663_ADC_LCH_HPF1_A1:
1054 case RT5663_ADC_RCH_HPF1_A1:
1055 case RT5663_ADC_LCH_HPF1_H0:
1056 case RT5663_ADC_RCH_HPF1_H0:
1057 case RT5663_ADC_EQ_PRE_VOL_L:
1058 case RT5663_ADC_EQ_PRE_VOL_R:
1059 case RT5663_ADC_EQ_POST_VOL_L:
1060 case RT5663_ADC_EQ_POST_VOL_R:
1061 return true;
1062 default:
1063 return false;
1064 }
1065 }
1066
1067 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1068 {
1069 switch (reg) {
1070 case RT5663_RESET:
1071 case RT5663_CBJ_TYPE_2:
1072 case RT5663_PDM_OUT_CTL:
1073 case RT5663_PDM_I2C_DATA_CTL1:
1074 case RT5663_PDM_I2C_DATA_CTL4:
1075 case RT5663_ALC_BK_GAIN:
1076 case RT5663_PLL_2:
1077 case RT5663_MICBIAS_1:
1078 case RT5663_ADC_EQ_1:
1079 case RT5663_INT_ST_1:
1080 case RT5663_GPIO_STA2:
1081 case RT5663_IL_CMD_1:
1082 case RT5663_IL_CMD_5:
1083 case RT5663_A_JD_CTRL:
1084 case RT5663_JD_CTRL2:
1085 case RT5663_VENDOR_ID:
1086 case RT5663_VENDOR_ID_1:
1087 case RT5663_VENDOR_ID_2:
1088 case RT5663_STO_DRE_1:
1089 case RT5663_STO_DRE_5:
1090 case RT5663_STO_DRE_6:
1091 case RT5663_STO_DRE_7:
1092 case RT5663_MONO_DYNA_6:
1093 case RT5663_STO1_SIL_DET:
1094 case RT5663_MONOL_SIL_DET:
1095 case RT5663_MONOR_SIL_DET:
1096 case RT5663_STO2_DAC_SIL:
1097 case RT5663_MONO_AMP_CAL_ST1:
1098 case RT5663_MONO_AMP_CAL_ST2:
1099 case RT5663_MONO_AMP_CAL_ST3:
1100 case RT5663_MONO_AMP_CAL_ST4:
1101 case RT5663_HP_IMP_SEN_2:
1102 case RT5663_HP_IMP_SEN_3:
1103 case RT5663_HP_IMP_SEN_4:
1104 case RT5663_HP_IMP_SEN_10:
1105 case RT5663_HP_CALIB_1:
1106 case RT5663_HP_CALIB_10:
1107 case RT5663_HP_CALIB_ST1:
1108 case RT5663_HP_CALIB_ST4:
1109 case RT5663_HP_CALIB_ST5:
1110 case RT5663_HP_CALIB_ST6:
1111 case RT5663_HP_CALIB_ST7:
1112 case RT5663_HP_CALIB_ST8:
1113 case RT5663_HP_CALIB_ST9:
1114 case RT5663_HP_CALIB_ST10:
1115 case RT5663_HP_CALIB_ST11:
1116 return true;
1117 default:
1118 return false;
1119 }
1120 }
1121
1122 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1123 {
1124 switch (reg) {
1125 case RT5663_LOUT_CTRL:
1126 case RT5663_HP_AMP_2:
1127 case RT5663_MONO_OUT:
1128 case RT5663_MONO_GAIN:
1129 case RT5663_AEC_BST:
1130 case RT5663_IN1_IN2:
1131 case RT5663_IN3_IN4:
1132 case RT5663_INL1_INR1:
1133 case RT5663_CBJ_TYPE_2:
1134 case RT5663_CBJ_TYPE_3:
1135 case RT5663_CBJ_TYPE_4:
1136 case RT5663_CBJ_TYPE_5:
1137 case RT5663_CBJ_TYPE_8:
1138 case RT5663_DAC3_DIG_VOL:
1139 case RT5663_DAC3_CTRL:
1140 case RT5663_MONO_ADC_DIG_VOL:
1141 case RT5663_STO2_ADC_DIG_VOL:
1142 case RT5663_MONO_ADC_BST_GAIN:
1143 case RT5663_STO2_ADC_BST_GAIN:
1144 case RT5663_SIDETONE_CTRL:
1145 case RT5663_MONO1_ADC_MIXER:
1146 case RT5663_STO2_ADC_MIXER:
1147 case RT5663_MONO_DAC_MIXER:
1148 case RT5663_DAC2_SRC_CTRL:
1149 case RT5663_IF_3_4_DATA_CTL:
1150 case RT5663_IF_5_DATA_CTL:
1151 case RT5663_PDM_OUT_CTL:
1152 case RT5663_PDM_I2C_DATA_CTL1:
1153 case RT5663_PDM_I2C_DATA_CTL2:
1154 case RT5663_PDM_I2C_DATA_CTL3:
1155 case RT5663_PDM_I2C_DATA_CTL4:
1156 case RT5663_RECMIX1_NEW:
1157 case RT5663_RECMIX1L_0:
1158 case RT5663_RECMIX1L:
1159 case RT5663_RECMIX1R_0:
1160 case RT5663_RECMIX1R:
1161 case RT5663_RECMIX2_NEW:
1162 case RT5663_RECMIX2_L_2:
1163 case RT5663_RECMIX2_R:
1164 case RT5663_RECMIX2_R_2:
1165 case RT5663_CALIB_REC_LR:
1166 case RT5663_ALC_BK_GAIN:
1167 case RT5663_MONOMIX_GAIN:
1168 case RT5663_MONOMIX_IN_GAIN:
1169 case RT5663_OUT_MIXL_GAIN:
1170 case RT5663_OUT_LMIX_IN_GAIN:
1171 case RT5663_OUT_RMIX_IN_GAIN:
1172 case RT5663_OUT_RMIX_IN_GAIN1:
1173 case RT5663_LOUT_MIXER_CTRL:
1174 case RT5663_PWR_VOL:
1175 case RT5663_ADCDAC_RST:
1176 case RT5663_I2S34_SDP:
1177 case RT5663_I2S5_SDP:
1178 case RT5663_TDM_6:
1179 case RT5663_TDM_7:
1180 case RT5663_TDM_8:
1181 case RT5663_TDM_9:
1182 case RT5663_ASRC_3:
1183 case RT5663_ASRC_6:
1184 case RT5663_ASRC_7:
1185 case RT5663_PLL_TRK_13:
1186 case RT5663_I2S_M_CLK_CTL:
1187 case RT5663_FDIV_I2S34_M_CLK:
1188 case RT5663_FDIV_I2S34_M_CLK2:
1189 case RT5663_FDIV_I2S5_M_CLK:
1190 case RT5663_FDIV_I2S5_M_CLK2:
1191 case RT5663_V2_IRQ_4:
1192 case RT5663_GPIO_3:
1193 case RT5663_GPIO_4:
1194 case RT5663_GPIO_STA2:
1195 case RT5663_HP_AMP_DET1:
1196 case RT5663_HP_AMP_DET2:
1197 case RT5663_HP_AMP_DET3:
1198 case RT5663_MID_BD_HP_AMP:
1199 case RT5663_LOW_BD_HP_AMP:
1200 case RT5663_SOF_VOL_ZC2:
1201 case RT5663_ADC_STO2_ADJ1:
1202 case RT5663_ADC_STO2_ADJ2:
1203 case RT5663_A_JD_CTRL:
1204 case RT5663_JD1_TRES_CTRL:
1205 case RT5663_JD2_TRES_CTRL:
1206 case RT5663_V2_JD_CTRL2:
1207 case RT5663_DUM_REG_2:
1208 case RT5663_DUM_REG_3:
1209 case RT5663_VENDOR_ID:
1210 case RT5663_VENDOR_ID_1:
1211 case RT5663_VENDOR_ID_2:
1212 case RT5663_DACADC_DIG_VOL2:
1213 case RT5663_DIG_IN_PIN2:
1214 case RT5663_PAD_DRV_CTL1:
1215 case RT5663_SOF_RAM_DEPOP:
1216 case RT5663_VOL_TEST:
1217 case RT5663_TEST_MODE_4:
1218 case RT5663_TEST_MODE_5:
1219 case RT5663_STO_DRE_9:
1220 case RT5663_MONO_DYNA_1:
1221 case RT5663_MONO_DYNA_2:
1222 case RT5663_MONO_DYNA_3:
1223 case RT5663_MONO_DYNA_4:
1224 case RT5663_MONO_DYNA_5:
1225 case RT5663_MONO_DYNA_6:
1226 case RT5663_STO1_SIL_DET:
1227 case RT5663_MONOL_SIL_DET:
1228 case RT5663_MONOR_SIL_DET:
1229 case RT5663_STO2_DAC_SIL:
1230 case RT5663_PWR_SAV_CTL1:
1231 case RT5663_PWR_SAV_CTL2:
1232 case RT5663_PWR_SAV_CTL3:
1233 case RT5663_PWR_SAV_CTL4:
1234 case RT5663_PWR_SAV_CTL5:
1235 case RT5663_PWR_SAV_CTL6:
1236 case RT5663_MONO_AMP_CAL1:
1237 case RT5663_MONO_AMP_CAL2:
1238 case RT5663_MONO_AMP_CAL3:
1239 case RT5663_MONO_AMP_CAL4:
1240 case RT5663_MONO_AMP_CAL5:
1241 case RT5663_MONO_AMP_CAL6:
1242 case RT5663_MONO_AMP_CAL7:
1243 case RT5663_MONO_AMP_CAL_ST1:
1244 case RT5663_MONO_AMP_CAL_ST2:
1245 case RT5663_MONO_AMP_CAL_ST3:
1246 case RT5663_MONO_AMP_CAL_ST4:
1247 case RT5663_MONO_AMP_CAL_ST5:
1248 case RT5663_V2_HP_IMP_SEN_13:
1249 case RT5663_V2_HP_IMP_SEN_14:
1250 case RT5663_V2_HP_IMP_SEN_6:
1251 case RT5663_V2_HP_IMP_SEN_7:
1252 case RT5663_V2_HP_IMP_SEN_8:
1253 case RT5663_V2_HP_IMP_SEN_9:
1254 case RT5663_V2_HP_IMP_SEN_10:
1255 case RT5663_HP_LOGIC_3:
1256 case RT5663_HP_CALIB_ST10:
1257 case RT5663_HP_CALIB_ST11:
1258 case RT5663_PRO_REG_TBL_4:
1259 case RT5663_PRO_REG_TBL_5:
1260 case RT5663_PRO_REG_TBL_6:
1261 case RT5663_PRO_REG_TBL_7:
1262 case RT5663_PRO_REG_TBL_8:
1263 case RT5663_PRO_REG_TBL_9:
1264 case RT5663_SAR_ADC_INL_1:
1265 case RT5663_SAR_ADC_INL_2:
1266 case RT5663_SAR_ADC_INL_3:
1267 case RT5663_SAR_ADC_INL_4:
1268 case RT5663_SAR_ADC_INL_5:
1269 case RT5663_SAR_ADC_INL_6:
1270 case RT5663_SAR_ADC_INL_7:
1271 case RT5663_SAR_ADC_INL_8:
1272 case RT5663_SAR_ADC_INL_9:
1273 case RT5663_SAR_ADC_INL_10:
1274 case RT5663_SAR_ADC_INL_11:
1275 case RT5663_SAR_ADC_INL_12:
1276 case RT5663_DRC_CTRL_1:
1277 case RT5663_DRC1_CTRL_2:
1278 case RT5663_DRC1_CTRL_3:
1279 case RT5663_DRC1_CTRL_4:
1280 case RT5663_DRC1_CTRL_5:
1281 case RT5663_DRC1_CTRL_6:
1282 case RT5663_DRC1_HD_CTRL_1:
1283 case RT5663_DRC1_HD_CTRL_2:
1284 case RT5663_DRC1_PRI_REG_1:
1285 case RT5663_DRC1_PRI_REG_2:
1286 case RT5663_DRC1_PRI_REG_3:
1287 case RT5663_DRC1_PRI_REG_4:
1288 case RT5663_DRC1_PRI_REG_5:
1289 case RT5663_DRC1_PRI_REG_6:
1290 case RT5663_DRC1_PRI_REG_7:
1291 case RT5663_DRC1_PRI_REG_8:
1292 case RT5663_ALC_PGA_CTL_1:
1293 case RT5663_ALC_PGA_CTL_2:
1294 case RT5663_ALC_PGA_CTL_3:
1295 case RT5663_ALC_PGA_CTL_4:
1296 case RT5663_ALC_PGA_CTL_5:
1297 case RT5663_ALC_PGA_CTL_6:
1298 case RT5663_ALC_PGA_CTL_7:
1299 case RT5663_ALC_PGA_CTL_8:
1300 case RT5663_ALC_PGA_REG_1:
1301 case RT5663_ALC_PGA_REG_2:
1302 case RT5663_ALC_PGA_REG_3:
1303 case RT5663_ADC_EQ_RECOV_1:
1304 case RT5663_ADC_EQ_RECOV_2:
1305 case RT5663_ADC_EQ_RECOV_3:
1306 case RT5663_ADC_EQ_RECOV_4:
1307 case RT5663_ADC_EQ_RECOV_5:
1308 case RT5663_ADC_EQ_RECOV_6:
1309 case RT5663_ADC_EQ_RECOV_7:
1310 case RT5663_ADC_EQ_RECOV_8:
1311 case RT5663_ADC_EQ_RECOV_9:
1312 case RT5663_ADC_EQ_RECOV_10:
1313 case RT5663_ADC_EQ_RECOV_11:
1314 case RT5663_ADC_EQ_RECOV_12:
1315 case RT5663_ADC_EQ_RECOV_13:
1316 case RT5663_VID_HIDDEN:
1317 case RT5663_VID_CUSTOMER:
1318 case RT5663_SCAN_MODE:
1319 case RT5663_I2C_BYPA:
1320 return true;
1321 case RT5663_TDM_1:
1322 case RT5663_DEPOP_3:
1323 case RT5663_ASRC_11_2:
1324 case RT5663_INT_ST_2:
1325 case RT5663_GPIO_STA1:
1326 case RT5663_SIN_GEN_1:
1327 case RT5663_SIN_GEN_2:
1328 case RT5663_SIN_GEN_3:
1329 case RT5663_IL_CMD_PWRSAV1:
1330 case RT5663_IL_CMD_PWRSAV2:
1331 case RT5663_EM_JACK_TYPE_1:
1332 case RT5663_EM_JACK_TYPE_2:
1333 case RT5663_EM_JACK_TYPE_3:
1334 case RT5663_EM_JACK_TYPE_4:
1335 case RT5663_FAST_OFF_MICBIAS:
1336 case RT5663_ANA_BIAS_CUR_1:
1337 case RT5663_ANA_BIAS_CUR_2:
1338 case RT5663_BIAS_CUR_9:
1339 case RT5663_DUMMY_REG_4:
1340 case RT5663_VREF_RECMIX:
1341 case RT5663_CHARGE_PUMP_1_2:
1342 case RT5663_CHARGE_PUMP_1_3:
1343 case RT5663_CHARGE_PUMP_2:
1344 case RT5663_CHOP_DAC_R:
1345 case RT5663_DUMMY_CTL_DACLR:
1346 case RT5663_DUMMY_REG_5:
1347 case RT5663_SOFT_RAMP:
1348 case RT5663_TEST_MODE_1:
1349 case RT5663_STO_DRE_10:
1350 case RT5663_MIC_DECRO_1:
1351 case RT5663_MIC_DECRO_2:
1352 case RT5663_MIC_DECRO_3:
1353 case RT5663_MIC_DECRO_4:
1354 case RT5663_MIC_DECRO_5:
1355 case RT5663_MIC_DECRO_6:
1356 case RT5663_HP_DECRO_1:
1357 case RT5663_HP_DECRO_2:
1358 case RT5663_HP_DECRO_3:
1359 case RT5663_HP_DECRO_4:
1360 case RT5663_HP_DECOUP:
1361 case RT5663_HP_IMPSEN_MAP4:
1362 case RT5663_HP_IMPSEN_MAP5:
1363 case RT5663_HP_IMPSEN_MAP7:
1364 case RT5663_HP_CALIB_1:
1365 case RT5663_CBJ_1:
1366 case RT5663_CBJ_2:
1367 case RT5663_CBJ_3:
1368 return false;
1369 default:
1370 return rt5663_readable_register(dev, reg);
1371 }
1372 }
1373
1374 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1375 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1376 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1377 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1378
1379 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1380 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1381 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1382 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1383 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1384 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1385 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1386 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1387 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1388 );
1389
1390 /* Interface data select */
1391 static const char * const rt5663_if1_adc_data_select[] = {
1392 "L/R", "R/L", "L/L", "R/R"
1393 };
1394
1395 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1396 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1397
1398 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1399 bool enable)
1400 {
1401 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1402
1403 if (enable) {
1404 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1405 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1406 /* reset in-line command */
1407 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1408 RT5663_RESET_4BTN_INL_MASK,
1409 RT5663_RESET_4BTN_INL_RESET);
1410 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1411 RT5663_RESET_4BTN_INL_MASK,
1412 RT5663_RESET_4BTN_INL_NOR);
1413 switch (rt5663->codec_ver) {
1414 case CODEC_VER_1:
1415 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1416 RT5663_V2_EN_IRQ_INLINE_MASK,
1417 RT5663_V2_EN_IRQ_INLINE_NOR);
1418 break;
1419 case CODEC_VER_0:
1420 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1421 RT5663_EN_IRQ_INLINE_MASK,
1422 RT5663_EN_IRQ_INLINE_NOR);
1423 break;
1424 default:
1425 dev_err(component->dev, "Unknown CODEC Version\n");
1426 }
1427 } else {
1428 switch (rt5663->codec_ver) {
1429 case CODEC_VER_1:
1430 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1431 RT5663_V2_EN_IRQ_INLINE_MASK,
1432 RT5663_V2_EN_IRQ_INLINE_BYP);
1433 break;
1434 case CODEC_VER_0:
1435 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1436 RT5663_EN_IRQ_INLINE_MASK,
1437 RT5663_EN_IRQ_INLINE_BYP);
1438 break;
1439 default:
1440 dev_err(component->dev, "Unknown CODEC Version\n");
1441 }
1442 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1443 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1444 /* reset in-line command */
1445 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1446 RT5663_RESET_4BTN_INL_MASK,
1447 RT5663_RESET_4BTN_INL_RESET);
1448 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1449 RT5663_RESET_4BTN_INL_MASK,
1450 RT5663_RESET_4BTN_INL_NOR);
1451 }
1452 }
1453
1454 /**
1455 * rt5663_v2_jack_detect - Detect headset.
1456 * @component: SoC audio component device.
1457 * @jack_insert: Jack insert or not.
1458 *
1459 * Detect whether is headset or not when jack inserted.
1460 *
1461 * Returns detect status.
1462 */
1463
1464 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1465 {
1466 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1467 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1468 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1469
1470 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1471 if (jack_insert) {
1472 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1473 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1474
1475 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1476 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1477 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1478 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1479 snd_soc_dapm_sync(dapm);
1480 snd_soc_component_update_bits(component, RT5663_RC_CLK,
1481 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1482 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1483
1484 while (i < 5) {
1485 msleep(sleep_time[i]);
1486 val = snd_soc_component_read(component, RT5663_CBJ_TYPE_2) & 0x0003;
1487 if (val == 0x1 || val == 0x2 || val == 0x3)
1488 break;
1489 dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1490 __func__, val, sleep_time[i]);
1491 i++;
1492 }
1493 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1494 switch (val) {
1495 case 1:
1496 case 2:
1497 rt5663->jack_type = SND_JACK_HEADSET;
1498 rt5663_enable_push_button_irq(component, true);
1499 break;
1500 default:
1501 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1502 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1503 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1504 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1505 snd_soc_dapm_sync(dapm);
1506 rt5663->jack_type = SND_JACK_HEADPHONE;
1507 break;
1508 }
1509 } else {
1510 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1511
1512 if (rt5663->jack_type == SND_JACK_HEADSET) {
1513 rt5663_enable_push_button_irq(component, false);
1514 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1515 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1516 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1517 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1518 snd_soc_dapm_sync(dapm);
1519 }
1520 rt5663->jack_type = 0;
1521 }
1522
1523 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1524 return rt5663->jack_type;
1525 }
1526
1527 /**
1528 * rt5663_jack_detect - Detect headset.
1529 * @component: SoC audio component device.
1530 * @jack_insert: Jack insert or not.
1531 *
1532 * Detect whether is headset or not when jack inserted.
1533 *
1534 * Returns detect status.
1535 */
1536 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1537 {
1538 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1539 int val, i = 0;
1540
1541 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1542
1543 if (jack_insert) {
1544 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1545 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1546 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1547 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1548 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1549 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1550 snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1551 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1552 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1553 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1554 snd_soc_component_update_bits(component, RT5663_CBJ_1,
1555 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1556 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1557 snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1558 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1559 /* BST1 power on for JD */
1560 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1561 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1562 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1563 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1564 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1565 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1566 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1567 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1568 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1569 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1570 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1571 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1572 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1573 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1574 msleep(20);
1575 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1576 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1577 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1578 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1579 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1580 snd_soc_component_update_bits(component, RT5663_IRQ_1,
1581 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1582 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1583 RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1584 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1585 RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1586
1587 while (true) {
1588 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1589 if (!(val & 0x80))
1590 usleep_range(10000, 10005);
1591 else
1592 break;
1593
1594 if (i > 200)
1595 break;
1596 i++;
1597 }
1598
1599 val = snd_soc_component_read(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1600 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1601
1602 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1603 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1604 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1605
1606 switch (val) {
1607 case 1:
1608 case 2:
1609 rt5663->jack_type = SND_JACK_HEADSET;
1610 rt5663_enable_push_button_irq(component, true);
1611
1612 if (rt5663->pdata.impedance_sensing_num)
1613 break;
1614
1615 if (rt5663->pdata.dc_offset_l_manual_mic) {
1616 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1617 rt5663->pdata.dc_offset_l_manual_mic >>
1618 16);
1619 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1620 rt5663->pdata.dc_offset_l_manual_mic &
1621 0xffff);
1622 }
1623
1624 if (rt5663->pdata.dc_offset_r_manual_mic) {
1625 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1626 rt5663->pdata.dc_offset_r_manual_mic >>
1627 16);
1628 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1629 rt5663->pdata.dc_offset_r_manual_mic &
1630 0xffff);
1631 }
1632 break;
1633 default:
1634 rt5663->jack_type = SND_JACK_HEADPHONE;
1635 snd_soc_component_update_bits(component,
1636 RT5663_PWR_ANLG_1,
1637 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1638 RT5663_PWR_VREF2_MASK, 0);
1639 if (rt5663->pdata.impedance_sensing_num)
1640 break;
1641
1642 if (rt5663->pdata.dc_offset_l_manual) {
1643 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1644 rt5663->pdata.dc_offset_l_manual >> 16);
1645 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1646 rt5663->pdata.dc_offset_l_manual &
1647 0xffff);
1648 }
1649
1650 if (rt5663->pdata.dc_offset_r_manual) {
1651 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1652 rt5663->pdata.dc_offset_r_manual >> 16);
1653 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1654 rt5663->pdata.dc_offset_r_manual &
1655 0xffff);
1656 }
1657 break;
1658 }
1659 } else {
1660 if (rt5663->jack_type == SND_JACK_HEADSET)
1661 rt5663_enable_push_button_irq(component, false);
1662 rt5663->jack_type = 0;
1663 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1664 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1665 RT5663_PWR_VREF2_MASK, 0);
1666 }
1667
1668 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1669 return rt5663->jack_type;
1670 }
1671
1672 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1673 {
1674 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1675 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1676
1677 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1678 if (rt5663->imp_table[i].vol == 7)
1679 break;
1680 }
1681
1682 if (rt5663->jack_type == SND_JACK_HEADSET) {
1683 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1684 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1685 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1686 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1687 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1688 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1689 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1690 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1691 } else {
1692 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1693 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1694 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1695 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1696 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1697 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1698 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1699 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1700 }
1701
1702 reg84 = snd_soc_component_read(component, RT5663_ASRC_2);
1703 reg26 = snd_soc_component_read(component, RT5663_STO1_ADC_MIXER);
1704 reg2fa = snd_soc_component_read(component, RT5663_DUMMY_1);
1705 reg91 = snd_soc_component_read(component, RT5663_HP_CHARGE_PUMP_1);
1706 reg10 = snd_soc_component_read(component, RT5663_RECMIX);
1707 reg80 = snd_soc_component_read(component, RT5663_GLB_CLK);
1708
1709 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1710 snd_soc_component_write(component, RT5663_ASRC_2, 0);
1711 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1712 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1713 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1714 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1715 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1716 usleep_range(10000, 10005);
1717 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1718 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1719 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1720 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1721 RT5663_SCLK_SRC_RCCLK);
1722 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1723 RT5663_DIG_25M_CLK_EN);
1724 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1725 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1726 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1727 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1728 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1729 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1730 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1731 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1732 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1733 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1734 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1735 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1736 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1737 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1738 RT5663_PWR_ADC_R1,
1739 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1740 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1741 RT5663_PWR_ADC_R1);
1742 msleep(40);
1743 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1744 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1745 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1746 msleep(30);
1747 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1748 snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1749 snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1750 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1751 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1752 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1753 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1754 snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1755 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1756 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1757 snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1758 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1759 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1760 snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1761 snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1762 snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1763 snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1764 snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1765 snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1766 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1767 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1768 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1769
1770 for (i = 0; i < 100; i++) {
1771 msleep(20);
1772 if (snd_soc_component_read(component, RT5663_INT_ST_1) & 0x2)
1773 break;
1774 }
1775
1776 value = snd_soc_component_read(component, RT5663_HP_IMP_SEN_4);
1777
1778 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1779 snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1780 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1781 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1782 RT5663_DIG_25M_CLK_DIS);
1783 snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1784 snd_soc_component_write(component, RT5663_RECMIX, reg10);
1785 snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1786 snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1787 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1788 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1789 snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1790 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1791 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1792 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1793 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1794 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1795 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1796 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1797 RT5663_PWR_ADC_R1, 0);
1798 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1799 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1800 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1801 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1802 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1803 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1804 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1805 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1806 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1807 snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1808
1809 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1810 if (value >= rt5663->imp_table[i].imp_min &&
1811 value <= rt5663->imp_table[i].imp_max)
1812 break;
1813 }
1814
1815 snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1816 rt5663->imp_table[i].vol);
1817 snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1818 rt5663->imp_table[i].vol);
1819
1820 if (rt5663->jack_type == SND_JACK_HEADSET) {
1821 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1822 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1823 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1824 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1825 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1826 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1827 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1828 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1829 } else {
1830 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1831 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1832 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1833 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1834 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1835 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1836 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1837 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1838 }
1839
1840 return 0;
1841 }
1842
1843 static int rt5663_button_detect(struct snd_soc_component *component)
1844 {
1845 int btn_type, val;
1846
1847 val = snd_soc_component_read(component, RT5663_IL_CMD_5);
1848 dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1849 btn_type = val & 0xfff0;
1850 snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1851
1852 return btn_type;
1853 }
1854
1855 static irqreturn_t rt5663_irq(int irq, void *data)
1856 {
1857 struct rt5663_priv *rt5663 = data;
1858
1859 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1860 __func__);
1861
1862 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1863 msecs_to_jiffies(250));
1864
1865 return IRQ_HANDLED;
1866 }
1867
1868 static int rt5663_set_jack_detect(struct snd_soc_component *component,
1869 struct snd_soc_jack *hs_jack, void *data)
1870 {
1871 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1872
1873 rt5663->hs_jack = hs_jack;
1874
1875 rt5663_irq(0, rt5663);
1876
1877 return 0;
1878 }
1879
1880 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1881 {
1882 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1883 int val = snd_soc_component_read(component, RT5663_INT_ST_1);
1884
1885 dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1886
1887 /* JD1 */
1888 switch (rt5663->codec_ver) {
1889 case CODEC_VER_1:
1890 return !(val & 0x2000);
1891 case CODEC_VER_0:
1892 return !(val & 0x1000);
1893 default:
1894 dev_err(component->dev, "Unknown CODEC Version\n");
1895 }
1896
1897 return false;
1898 }
1899
1900 static void rt5663_jack_detect_work(struct work_struct *work)
1901 {
1902 struct rt5663_priv *rt5663 =
1903 container_of(work, struct rt5663_priv, jack_detect_work.work);
1904 struct snd_soc_component *component = rt5663->component;
1905 int btn_type, report = 0;
1906
1907 if (!component)
1908 return;
1909
1910 if (rt5663_check_jd_status(component)) {
1911 /* jack in */
1912 if (rt5663->jack_type == 0) {
1913 /* jack was out, report jack type */
1914 switch (rt5663->codec_ver) {
1915 case CODEC_VER_1:
1916 report = rt5663_v2_jack_detect(
1917 rt5663->component, 1);
1918 break;
1919 case CODEC_VER_0:
1920 report = rt5663_jack_detect(rt5663->component, 1);
1921 if (rt5663->pdata.impedance_sensing_num)
1922 rt5663_impedance_sensing(rt5663->component);
1923 break;
1924 default:
1925 dev_err(component->dev, "Unknown CODEC Version\n");
1926 }
1927
1928 /* Delay the jack insert report to avoid pop noise */
1929 msleep(30);
1930 } else {
1931 /* jack is already in, report button event */
1932 report = SND_JACK_HEADSET;
1933 btn_type = rt5663_button_detect(rt5663->component);
1934 /**
1935 * rt5663 can report three kinds of button behavior,
1936 * one click, double click and hold. However,
1937 * currently we will report button pressed/released
1938 * event. So all the three button behaviors are
1939 * treated as button pressed.
1940 */
1941 switch (btn_type) {
1942 case 0x8000:
1943 case 0x4000:
1944 case 0x2000:
1945 report |= SND_JACK_BTN_0;
1946 break;
1947 case 0x1000:
1948 case 0x0800:
1949 case 0x0400:
1950 report |= SND_JACK_BTN_1;
1951 break;
1952 case 0x0200:
1953 case 0x0100:
1954 case 0x0080:
1955 report |= SND_JACK_BTN_2;
1956 break;
1957 case 0x0040:
1958 case 0x0020:
1959 case 0x0010:
1960 report |= SND_JACK_BTN_3;
1961 break;
1962 case 0x0000: /* unpressed */
1963 break;
1964 default:
1965 btn_type = 0;
1966 dev_err(rt5663->component->dev,
1967 "Unexpected button code 0x%04x\n",
1968 btn_type);
1969 break;
1970 }
1971 /* button release or spurious interrput*/
1972 if (btn_type == 0) {
1973 report = rt5663->jack_type;
1974 cancel_delayed_work_sync(
1975 &rt5663->jd_unplug_work);
1976 } else {
1977 queue_delayed_work(system_wq,
1978 &rt5663->jd_unplug_work,
1979 msecs_to_jiffies(500));
1980 }
1981 }
1982 } else {
1983 /* jack out */
1984 switch (rt5663->codec_ver) {
1985 case CODEC_VER_1:
1986 report = rt5663_v2_jack_detect(rt5663->component, 0);
1987 break;
1988 case CODEC_VER_0:
1989 report = rt5663_jack_detect(rt5663->component, 0);
1990 break;
1991 default:
1992 dev_err(component->dev, "Unknown CODEC Version\n");
1993 }
1994 }
1995 dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1996 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1997 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1998 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1999 }
2000
2001 static void rt5663_jd_unplug_work(struct work_struct *work)
2002 {
2003 struct rt5663_priv *rt5663 =
2004 container_of(work, struct rt5663_priv, jd_unplug_work.work);
2005 struct snd_soc_component *component = rt5663->component;
2006
2007 if (!component)
2008 return;
2009
2010 if (!rt5663_check_jd_status(component)) {
2011 /* jack out */
2012 switch (rt5663->codec_ver) {
2013 case CODEC_VER_1:
2014 rt5663_v2_jack_detect(rt5663->component, 0);
2015 break;
2016 case CODEC_VER_0:
2017 rt5663_jack_detect(rt5663->component, 0);
2018 break;
2019 default:
2020 dev_err(component->dev, "Unknown CODEC Version\n");
2021 }
2022
2023 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2024 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2025 SND_JACK_BTN_2 | SND_JACK_BTN_3);
2026 } else {
2027 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2028 msecs_to_jiffies(500));
2029 }
2030 }
2031
2032 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2033 /* DAC Digital Volume */
2034 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2035 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2036 87, 0, dac_vol_tlv),
2037 /* ADC Digital Volume Control */
2038 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2039 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2040 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2041 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2042 63, 0, adc_vol_tlv),
2043 };
2044
2045 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2046 /* Headphone Output Volume */
2047 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2048 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2049 rt5663_v2_hp_vol_tlv),
2050 /* Mic Boost Volume */
2051 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2052 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2053 };
2054
2055 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2056 /* Mic Boost Volume*/
2057 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2058 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2059 /* Data Swap for Slot0/1 in ADCDAT1 */
2060 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2061 };
2062
2063 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2064 /* Headphone Output Volume */
2065 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2066 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2067 rt5663_hp_vol_tlv),
2068 };
2069
2070 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2071 struct snd_soc_dapm_widget *sink)
2072 {
2073 unsigned int val;
2074 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2075
2076 val = snd_soc_component_read(component, RT5663_GLB_CLK);
2077 val &= RT5663_SCLK_SRC_MASK;
2078 if (val == RT5663_SCLK_SRC_PLL1)
2079 return 1;
2080 else
2081 return 0;
2082 }
2083
2084 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2085 struct snd_soc_dapm_widget *sink)
2086 {
2087 unsigned int reg, shift, val;
2088 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2089 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2090
2091 if (rt5663->codec_ver == CODEC_VER_1) {
2092 switch (w->shift) {
2093 case RT5663_ADC_STO1_ASRC_SHIFT:
2094 reg = RT5663_ASRC_3;
2095 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2096 break;
2097 case RT5663_DAC_STO1_ASRC_SHIFT:
2098 reg = RT5663_ASRC_2;
2099 shift = RT5663_DA_STO1_TRACK_SHIFT;
2100 break;
2101 default:
2102 return 0;
2103 }
2104 } else {
2105 switch (w->shift) {
2106 case RT5663_ADC_STO1_ASRC_SHIFT:
2107 reg = RT5663_ASRC_2;
2108 shift = RT5663_AD_STO1_TRACK_SHIFT;
2109 break;
2110 case RT5663_DAC_STO1_ASRC_SHIFT:
2111 reg = RT5663_ASRC_2;
2112 shift = RT5663_DA_STO1_TRACK_SHIFT;
2113 break;
2114 default:
2115 return 0;
2116 }
2117 }
2118
2119 val = (snd_soc_component_read(component, reg) >> shift) & 0x7;
2120
2121 if (val)
2122 return 1;
2123
2124 return 0;
2125 }
2126
2127 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2128 struct snd_soc_dapm_widget *sink)
2129 {
2130 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2131 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2132 int da_asrc_en, ad_asrc_en;
2133
2134 da_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
2135 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2136 switch (rt5663->codec_ver) {
2137 case CODEC_VER_1:
2138 ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_3) &
2139 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2140 break;
2141 case CODEC_VER_0:
2142 ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
2143 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2144 break;
2145 default:
2146 dev_err(component->dev, "Unknown CODEC Version\n");
2147 return 1;
2148 }
2149
2150 if (da_asrc_en || ad_asrc_en)
2151 if (rt5663->sysclk > rt5663->lrck * 384)
2152 return 1;
2153
2154 dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2155
2156 return 0;
2157 }
2158
2159 /**
2160 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2161 * @component: SoC audio component device.
2162 * @filter_mask: mask of filters.
2163 * @clk_src: clock source
2164 *
2165 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2166 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2167 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2168 * ASRC function will track i2s clock and generate a corresponding system clock
2169 * for codec. This function provides an API to select the clock source for a
2170 * set of filters specified by the mask. And the codec driver will turn on ASRC
2171 * for these filters if ASRC is selected as their clock source.
2172 */
2173 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2174 unsigned int filter_mask, unsigned int clk_src)
2175 {
2176 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2177 unsigned int asrc2_mask = 0;
2178 unsigned int asrc2_value = 0;
2179 unsigned int asrc3_mask = 0;
2180 unsigned int asrc3_value = 0;
2181
2182 switch (clk_src) {
2183 case RT5663_CLK_SEL_SYS:
2184 case RT5663_CLK_SEL_I2S1_ASRC:
2185 break;
2186
2187 default:
2188 return -EINVAL;
2189 }
2190
2191 if (filter_mask & RT5663_DA_STEREO_FILTER) {
2192 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2193 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2194 }
2195
2196 if (filter_mask & RT5663_AD_STEREO_FILTER) {
2197 switch (rt5663->codec_ver) {
2198 case CODEC_VER_1:
2199 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2200 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2201 break;
2202 case CODEC_VER_0:
2203 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2204 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2205 break;
2206 default:
2207 dev_err(component->dev, "Unknown CODEC Version\n");
2208 }
2209 }
2210
2211 if (asrc2_mask)
2212 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2213 asrc2_value);
2214
2215 if (asrc3_mask)
2216 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2217 asrc3_value);
2218
2219 return 0;
2220 }
2221 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2222
2223 /* Analog Mixer */
2224 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2225 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2226 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2227 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2228 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2229 };
2230
2231 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2232 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2233 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2234 };
2235
2236 /* Digital Mixer */
2237 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2238 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2239 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2240 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2241 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2242 };
2243
2244 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2245 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2246 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2247 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2248 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2249 };
2250
2251 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2252 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2253 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2254 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2255 RT5663_M_DAC1_L_SHIFT, 1, 1),
2256 };
2257
2258 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2259 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2260 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2261 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2262 RT5663_M_DAC1_R_SHIFT, 1, 1),
2263 };
2264
2265 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2266 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2267 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2268 };
2269
2270 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2271 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2272 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2273 };
2274
2275 /* Out Switch */
2276 static const struct snd_kcontrol_new rt5663_hpo_switch =
2277 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2278 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2279
2280 /* Stereo ADC source */
2281 static const char * const rt5663_sto1_adc_src[] = {
2282 "ADC L", "ADC R"
2283 };
2284
2285 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2286 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2287
2288 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2289 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2290
2291 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2292 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2293
2294 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2295 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2296
2297 /* RT5663: Analog DACL1 input source */
2298 static const char * const rt5663_alg_dacl_src[] = {
2299 "DAC L", "STO DAC MIXL"
2300 };
2301
2302 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2303 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2304
2305 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2306 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2307
2308 /* RT5663: Analog DACR1 input source */
2309 static const char * const rt5663_alg_dacr_src[] = {
2310 "DAC R", "STO DAC MIXR"
2311 };
2312
2313 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2314 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2315
2316 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2317 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2318
2319 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2320 struct snd_kcontrol *kcontrol, int event)
2321 {
2322 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2323 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2324
2325 switch (event) {
2326 case SND_SOC_DAPM_POST_PMU:
2327 if (rt5663->codec_ver == CODEC_VER_1) {
2328 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2329 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2330 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2331 RT5663_HP_SIG_SRC1_MASK,
2332 RT5663_HP_SIG_SRC1_SILENCE);
2333 } else {
2334 snd_soc_component_update_bits(component,
2335 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2336 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2337 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2338 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2339 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2340 snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2341 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2342 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2343 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2344 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2345 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2346 0x8000);
2347 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2348 0x3000);
2349 snd_soc_component_update_bits(component,
2350 RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
2351 }
2352 break;
2353
2354 case SND_SOC_DAPM_PRE_PMD:
2355 if (rt5663->codec_ver == CODEC_VER_1) {
2356 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2357 RT5663_HP_SIG_SRC1_MASK,
2358 RT5663_HP_SIG_SRC1_REG);
2359 } else {
2360 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2361 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2362 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2363 snd_soc_component_update_bits(component,
2364 RT5663_DACREF_LDO, 0x3e0e, 0);
2365 snd_soc_component_update_bits(component,
2366 RT5663_DIG_VOL_ZCD, 0x00c0, 0);
2367 }
2368 break;
2369
2370 default:
2371 return 0;
2372 }
2373
2374 return 0;
2375 }
2376
2377 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2378 struct snd_kcontrol *kcontrol, int event)
2379 {
2380 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2381 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2382
2383 switch (event) {
2384 case SND_SOC_DAPM_PRE_PMU:
2385 if (rt5663->codec_ver == CODEC_VER_0) {
2386 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2387 0x0030);
2388 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2389 0x0003);
2390 }
2391 break;
2392
2393 case SND_SOC_DAPM_POST_PMD:
2394 if (rt5663->codec_ver == CODEC_VER_0) {
2395 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2396 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2397 }
2398 break;
2399
2400 default:
2401 return 0;
2402 }
2403
2404 return 0;
2405 }
2406
2407 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2408 struct snd_kcontrol *kcontrol, int event)
2409 {
2410 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2411
2412 switch (event) {
2413 case SND_SOC_DAPM_POST_PMU:
2414 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2415 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2416 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2417 break;
2418
2419 case SND_SOC_DAPM_PRE_PMD:
2420 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2421 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2422 break;
2423
2424 default:
2425 return 0;
2426 }
2427
2428 return 0;
2429 }
2430
2431 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2432 struct snd_kcontrol *kcontrol, int event)
2433 {
2434 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2435
2436 switch (event) {
2437 case SND_SOC_DAPM_POST_PMU:
2438 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2439 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2440 break;
2441
2442 case SND_SOC_DAPM_PRE_PMD:
2443 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2444 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2445 break;
2446
2447 default:
2448 return 0;
2449 }
2450
2451 return 0;
2452 }
2453
2454 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2455 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2456 NULL, 0),
2457
2458 /* micbias */
2459 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2460 RT5663_PWR_MB1_SHIFT, 0),
2461 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2462 RT5663_PWR_MB2_SHIFT, 0),
2463
2464 /* Input Lines */
2465 SND_SOC_DAPM_INPUT("IN1P"),
2466 SND_SOC_DAPM_INPUT("IN1N"),
2467
2468 /* REC Mixer Power */
2469 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2470 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2471
2472 /* ADCs */
2473 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2474 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2475 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2476 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2477 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2478
2479 /* ADC Mixer */
2480 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2481 0, 0, rt5663_sto1_adc_l_mix,
2482 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2483
2484 /* ADC Filter Power */
2485 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2486 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2487
2488 /* Digital Interface */
2489 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2490 NULL, 0),
2491 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2492 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2493 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2496
2497 /* Audio Interface */
2498 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2499 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2500
2501 /* DAC mixer before sound effect */
2502 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2503 ARRAY_SIZE(rt5663_adda_l_mix)),
2504 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2505 ARRAY_SIZE(rt5663_adda_r_mix)),
2506 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2507 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2508
2509 /* DAC Mixer */
2510 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2511 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2512 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2513 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2514 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2515 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2516
2517 /* DACs */
2518 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2519 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2520 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2521 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2522 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2523 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2524
2525 /* Headphone*/
2526 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2527 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2528 SND_SOC_DAPM_POST_PMD),
2529 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2530 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2531
2532 /* Output Lines */
2533 SND_SOC_DAPM_OUTPUT("HPOL"),
2534 SND_SOC_DAPM_OUTPUT("HPOR"),
2535 };
2536
2537 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2538 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2539 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2540 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2541 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2542 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2543 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2544
2545 /* ASRC */
2546 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2547 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2548 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2549 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2550 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2551 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2552
2553 /* Input Lines */
2554 SND_SOC_DAPM_INPUT("IN2P"),
2555 SND_SOC_DAPM_INPUT("IN2N"),
2556
2557 /* Boost */
2558 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2559 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2560 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2561 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2562 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2563 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2564 SND_SOC_DAPM_POST_PMU),
2565
2566 /* REC Mixer */
2567 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2568 ARRAY_SIZE(rt5663_recmix1l)),
2569 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2570 ARRAY_SIZE(rt5663_recmix1r)),
2571 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2572 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2573
2574 /* ADC */
2575 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2576 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2577 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2578
2579 /* ADC Mux */
2580 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2581 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2583 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2585 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2586 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2587 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2588
2589 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2590 &rt5663_sto1_adcl_mux),
2591 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2592 &rt5663_sto1_adcr_mux),
2593
2594 /* ADC Mix */
2595 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2596 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2597
2598 /* Analog DAC Clock */
2599 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2600 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2601
2602 /* Headphone out */
2603 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2604 &rt5663_hpo_switch),
2605 };
2606
2607 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2608 /* System Clock Pre Divider Gating */
2609 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2610 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2611 SND_SOC_DAPM_PRE_PMD),
2612
2613 /* LDO */
2614 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2615 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2616
2617 /* ASRC */
2618 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2619 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2620 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2621 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2623 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2624
2625 /* Boost */
2626 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2627
2628 /* STO ADC */
2629 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2630 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2631
2632 /* Analog DAC source */
2633 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2634 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2635 };
2636
2637 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2638 /* PLL */
2639 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2640
2641 /* ASRC */
2642 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2643 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2644 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2645
2646 { "ADC L", NULL, "ADC L Power" },
2647 { "ADC L", NULL, "ADC Clock" },
2648
2649 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2650
2651 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2652 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2653 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2654
2655 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2656 { "IF ADC", NULL, "IF1 ADC1" },
2657 { "AIFTX", NULL, "IF ADC" },
2658 { "AIFTX", NULL, "I2S" },
2659
2660 { "AIFRX", NULL, "I2S" },
2661 { "IF DAC", NULL, "AIFRX" },
2662 { "IF1 DAC1 L", NULL, "IF DAC" },
2663 { "IF1 DAC1 R", NULL, "IF DAC" },
2664
2665 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2666 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2667 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2668 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2669 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2670 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2671 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2672
2673 { "DAC L1", NULL, "ADDA MIXL" },
2674 { "DAC R1", NULL, "ADDA MIXR" },
2675
2676 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2677 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2678 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2679 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2680 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2681 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2682
2683 { "HP Amp", NULL, "HP Charge Pump" },
2684 { "HP Amp", NULL, "DAC L" },
2685 { "HP Amp", NULL, "DAC R" },
2686 };
2687
2688 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2689 { "MICBIAS1", NULL, "LDO2" },
2690 { "MICBIAS2", NULL, "LDO2" },
2691
2692 { "BST1 CBJ", NULL, "IN1P" },
2693 { "BST1 CBJ", NULL, "IN1N" },
2694 { "BST1 CBJ", NULL, "CBJ Power" },
2695
2696 { "BST2", NULL, "IN2P" },
2697 { "BST2", NULL, "IN2N" },
2698 { "BST2", NULL, "BST2 Power" },
2699
2700 { "RECMIX1L", "BST2 Switch", "BST2" },
2701 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2702 { "RECMIX1L", NULL, "RECMIX1L Power" },
2703 { "RECMIX1R", "BST2 Switch", "BST2" },
2704 { "RECMIX1R", NULL, "RECMIX1R Power" },
2705
2706 { "ADC L", NULL, "RECMIX1L" },
2707 { "ADC R", NULL, "RECMIX1R" },
2708 { "ADC R", NULL, "ADC R Power" },
2709 { "ADC R", NULL, "ADC Clock" },
2710
2711 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2712 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2713 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2714
2715 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2716 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2717 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2718 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2719
2720 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2721 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2722 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2723
2724 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2725
2726 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2727
2728 { "DAC L", NULL, "STO1 DAC MIXL" },
2729 { "DAC L", NULL, "LDO DAC" },
2730 { "DAC L", NULL, "DAC Clock" },
2731 { "DAC R", NULL, "STO1 DAC MIXR" },
2732 { "DAC R", NULL, "LDO DAC" },
2733 { "DAC R", NULL, "DAC Clock" },
2734
2735 { "HPO Playback", "Switch", "HP Amp" },
2736 { "HPOL", NULL, "HPO Playback" },
2737 { "HPOR", NULL, "HPO Playback" },
2738 };
2739
2740 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2741 { "I2S", NULL, "Pre Div Power" },
2742
2743 { "BST1", NULL, "IN1P" },
2744 { "BST1", NULL, "IN1N" },
2745 { "BST1", NULL, "RECMIX1L Power" },
2746
2747 { "ADC L", NULL, "BST1" },
2748
2749 { "STO1 ADC L1", NULL, "ADC L" },
2750
2751 { "DAC L Mux", "DAC L", "DAC L1" },
2752 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2753 { "DAC R Mux", "DAC R", "DAC R1"},
2754 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2755
2756 { "DAC L", NULL, "DAC L Mux" },
2757 { "DAC R", NULL, "DAC R Mux" },
2758
2759 { "HPOL", NULL, "HP Amp" },
2760 { "HPOR", NULL, "HP Amp" },
2761 };
2762
2763 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2764 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2765 {
2766 struct snd_soc_component *component = dai->component;
2767 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2768 unsigned int val_len = 0;
2769 int pre_div;
2770
2771 rt5663->lrck = params_rate(params);
2772
2773 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2774 rt5663->lrck, rt5663->sysclk);
2775
2776 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2777 if (pre_div < 0) {
2778 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2779 rt5663->lrck, dai->id);
2780 return -EINVAL;
2781 }
2782
2783 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2784
2785 switch (params_width(params)) {
2786 case 8:
2787 val_len = RT5663_I2S_DL_8;
2788 break;
2789 case 16:
2790 val_len = RT5663_I2S_DL_16;
2791 break;
2792 case 20:
2793 val_len = RT5663_I2S_DL_20;
2794 break;
2795 case 24:
2796 val_len = RT5663_I2S_DL_24;
2797 break;
2798 default:
2799 return -EINVAL;
2800 }
2801
2802 snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2803 RT5663_I2S_DL_MASK, val_len);
2804
2805 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2806 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2807
2808 return 0;
2809 }
2810
2811 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2812 {
2813 struct snd_soc_component *component = dai->component;
2814 unsigned int reg_val = 0;
2815
2816 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2817 case SND_SOC_DAIFMT_CBM_CFM:
2818 break;
2819 case SND_SOC_DAIFMT_CBS_CFS:
2820 reg_val |= RT5663_I2S_MS_S;
2821 break;
2822 default:
2823 return -EINVAL;
2824 }
2825
2826 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2827 case SND_SOC_DAIFMT_NB_NF:
2828 break;
2829 case SND_SOC_DAIFMT_IB_NF:
2830 reg_val |= RT5663_I2S_BP_INV;
2831 break;
2832 default:
2833 return -EINVAL;
2834 }
2835
2836 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2837 case SND_SOC_DAIFMT_I2S:
2838 break;
2839 case SND_SOC_DAIFMT_LEFT_J:
2840 reg_val |= RT5663_I2S_DF_LEFT;
2841 break;
2842 case SND_SOC_DAIFMT_DSP_A:
2843 reg_val |= RT5663_I2S_DF_PCM_A;
2844 break;
2845 case SND_SOC_DAIFMT_DSP_B:
2846 reg_val |= RT5663_I2S_DF_PCM_B;
2847 break;
2848 default:
2849 return -EINVAL;
2850 }
2851
2852 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2853 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2854
2855 return 0;
2856 }
2857
2858 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2859 unsigned int freq, int dir)
2860 {
2861 struct snd_soc_component *component = dai->component;
2862 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2863 unsigned int reg_val = 0;
2864
2865 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2866 return 0;
2867
2868 switch (clk_id) {
2869 case RT5663_SCLK_S_MCLK:
2870 reg_val |= RT5663_SCLK_SRC_MCLK;
2871 break;
2872 case RT5663_SCLK_S_PLL1:
2873 reg_val |= RT5663_SCLK_SRC_PLL1;
2874 break;
2875 case RT5663_SCLK_S_RCCLK:
2876 reg_val |= RT5663_SCLK_SRC_RCCLK;
2877 break;
2878 default:
2879 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2880 return -EINVAL;
2881 }
2882 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2883 reg_val);
2884 rt5663->sysclk = freq;
2885 rt5663->sysclk_src = clk_id;
2886
2887 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2888 freq, clk_id);
2889
2890 return 0;
2891 }
2892
2893 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2894 unsigned int freq_in, unsigned int freq_out)
2895 {
2896 struct snd_soc_component *component = dai->component;
2897 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2898 struct rl6231_pll_code pll_code;
2899 int ret;
2900 int mask, shift, val;
2901
2902 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2903 freq_out == rt5663->pll_out)
2904 return 0;
2905
2906 if (!freq_in || !freq_out) {
2907 dev_dbg(component->dev, "PLL disabled\n");
2908
2909 rt5663->pll_in = 0;
2910 rt5663->pll_out = 0;
2911 snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2912 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2913 return 0;
2914 }
2915
2916 switch (rt5663->codec_ver) {
2917 case CODEC_VER_1:
2918 mask = RT5663_V2_PLL1_SRC_MASK;
2919 shift = RT5663_V2_PLL1_SRC_SHIFT;
2920 break;
2921 case CODEC_VER_0:
2922 mask = RT5663_PLL1_SRC_MASK;
2923 shift = RT5663_PLL1_SRC_SHIFT;
2924 break;
2925 default:
2926 dev_err(component->dev, "Unknown CODEC Version\n");
2927 return -EINVAL;
2928 }
2929
2930 switch (source) {
2931 case RT5663_PLL1_S_MCLK:
2932 val = 0x0;
2933 break;
2934 case RT5663_PLL1_S_BCLK1:
2935 val = 0x1;
2936 break;
2937 default:
2938 dev_err(component->dev, "Unknown PLL source %d\n", source);
2939 return -EINVAL;
2940 }
2941 snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2942
2943 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2944 if (ret < 0) {
2945 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2946 return ret;
2947 }
2948
2949 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2950 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2951 pll_code.k_code);
2952
2953 snd_soc_component_write(component, RT5663_PLL_1,
2954 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2955 snd_soc_component_write(component, RT5663_PLL_2,
2956 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT) |
2957 (pll_code.m_bp << RT5663_PLL_M_BP_SHIFT));
2958
2959 rt5663->pll_in = freq_in;
2960 rt5663->pll_out = freq_out;
2961 rt5663->pll_src = source;
2962
2963 return 0;
2964 }
2965
2966 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2967 unsigned int rx_mask, int slots, int slot_width)
2968 {
2969 struct snd_soc_component *component = dai->component;
2970 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2971 unsigned int val = 0, reg;
2972
2973 if (rx_mask || tx_mask)
2974 val |= RT5663_TDM_MODE_TDM;
2975
2976 switch (slots) {
2977 case 4:
2978 val |= RT5663_TDM_IN_CH_4;
2979 val |= RT5663_TDM_OUT_CH_4;
2980 break;
2981 case 6:
2982 val |= RT5663_TDM_IN_CH_6;
2983 val |= RT5663_TDM_OUT_CH_6;
2984 break;
2985 case 8:
2986 val |= RT5663_TDM_IN_CH_8;
2987 val |= RT5663_TDM_OUT_CH_8;
2988 break;
2989 case 2:
2990 break;
2991 default:
2992 return -EINVAL;
2993 }
2994
2995 switch (slot_width) {
2996 case 20:
2997 val |= RT5663_TDM_IN_LEN_20;
2998 val |= RT5663_TDM_OUT_LEN_20;
2999 break;
3000 case 24:
3001 val |= RT5663_TDM_IN_LEN_24;
3002 val |= RT5663_TDM_OUT_LEN_24;
3003 break;
3004 case 32:
3005 val |= RT5663_TDM_IN_LEN_32;
3006 val |= RT5663_TDM_OUT_LEN_32;
3007 break;
3008 case 16:
3009 break;
3010 default:
3011 return -EINVAL;
3012 }
3013
3014 switch (rt5663->codec_ver) {
3015 case CODEC_VER_1:
3016 reg = RT5663_TDM_2;
3017 break;
3018 case CODEC_VER_0:
3019 reg = RT5663_TDM_1;
3020 break;
3021 default:
3022 dev_err(component->dev, "Unknown CODEC Version\n");
3023 return -EINVAL;
3024 }
3025
3026 snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3027 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3028 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3029
3030 return 0;
3031 }
3032
3033 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3034 {
3035 struct snd_soc_component *component = dai->component;
3036 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3037 unsigned int reg;
3038
3039 dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3040
3041 if (rt5663->codec_ver == CODEC_VER_1)
3042 reg = RT5663_TDM_9;
3043 else
3044 reg = RT5663_TDM_5;
3045
3046 switch (ratio) {
3047 case 32:
3048 snd_soc_component_update_bits(component, reg,
3049 RT5663_TDM_LENGTN_MASK,
3050 RT5663_TDM_LENGTN_16);
3051 break;
3052 case 40:
3053 snd_soc_component_update_bits(component, reg,
3054 RT5663_TDM_LENGTN_MASK,
3055 RT5663_TDM_LENGTN_20);
3056 break;
3057 case 48:
3058 snd_soc_component_update_bits(component, reg,
3059 RT5663_TDM_LENGTN_MASK,
3060 RT5663_TDM_LENGTN_24);
3061 break;
3062 case 64:
3063 snd_soc_component_update_bits(component, reg,
3064 RT5663_TDM_LENGTN_MASK,
3065 RT5663_TDM_LENGTN_32);
3066 break;
3067 default:
3068 dev_err(component->dev, "Invalid ratio!\n");
3069 return -EINVAL;
3070 }
3071
3072 return 0;
3073 }
3074
3075 static int rt5663_set_bias_level(struct snd_soc_component *component,
3076 enum snd_soc_bias_level level)
3077 {
3078 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3079
3080 switch (level) {
3081 case SND_SOC_BIAS_ON:
3082 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3083 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3084 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3085 break;
3086
3087 case SND_SOC_BIAS_PREPARE:
3088 if (rt5663->codec_ver == CODEC_VER_1) {
3089 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3090 RT5663_DIG_GATE_CTRL_MASK,
3091 RT5663_DIG_GATE_CTRL_EN);
3092 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3093 RT5663_EN_ANA_CLK_DET_MASK |
3094 RT5663_PWR_CLK_DET_MASK,
3095 RT5663_EN_ANA_CLK_DET_AUTO |
3096 RT5663_PWR_CLK_DET_EN);
3097 }
3098 break;
3099
3100 case SND_SOC_BIAS_STANDBY:
3101 if (rt5663->codec_ver == CODEC_VER_1)
3102 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3103 RT5663_DIG_GATE_CTRL_MASK,
3104 RT5663_DIG_GATE_CTRL_DIS);
3105 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3106 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3107 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3108 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3109 RT5663_PWR_VREF2 | RT5663_PWR_MB);
3110 usleep_range(10000, 10005);
3111 if (rt5663->codec_ver == CODEC_VER_1) {
3112 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3113 RT5663_EN_ANA_CLK_DET_MASK |
3114 RT5663_PWR_CLK_DET_MASK,
3115 RT5663_EN_ANA_CLK_DET_DIS |
3116 RT5663_PWR_CLK_DET_DIS);
3117 }
3118 break;
3119
3120 case SND_SOC_BIAS_OFF:
3121 if (rt5663->jack_type != SND_JACK_HEADSET)
3122 snd_soc_component_update_bits(component,
3123 RT5663_PWR_ANLG_1,
3124 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3125 RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3126 RT5663_PWR_MB_MASK, 0);
3127 else
3128 snd_soc_component_update_bits(component,
3129 RT5663_PWR_ANLG_1,
3130 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3131 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3132 break;
3133
3134 default:
3135 break;
3136 }
3137
3138 return 0;
3139 }
3140
3141 static int rt5663_probe(struct snd_soc_component *component)
3142 {
3143 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3144 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3145
3146 rt5663->component = component;
3147
3148 switch (rt5663->codec_ver) {
3149 case CODEC_VER_1:
3150 snd_soc_dapm_new_controls(dapm,
3151 rt5663_v2_specific_dapm_widgets,
3152 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3153 snd_soc_dapm_add_routes(dapm,
3154 rt5663_v2_specific_dapm_routes,
3155 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3156 snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3157 ARRAY_SIZE(rt5663_v2_specific_controls));
3158 break;
3159 case CODEC_VER_0:
3160 snd_soc_dapm_new_controls(dapm,
3161 rt5663_specific_dapm_widgets,
3162 ARRAY_SIZE(rt5663_specific_dapm_widgets));
3163 snd_soc_dapm_add_routes(dapm,
3164 rt5663_specific_dapm_routes,
3165 ARRAY_SIZE(rt5663_specific_dapm_routes));
3166 snd_soc_add_component_controls(component, rt5663_specific_controls,
3167 ARRAY_SIZE(rt5663_specific_controls));
3168
3169 if (!rt5663->imp_table)
3170 snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3171 ARRAY_SIZE(rt5663_hpvol_controls));
3172 break;
3173 }
3174
3175 return 0;
3176 }
3177
3178 static void rt5663_remove(struct snd_soc_component *component)
3179 {
3180 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3181
3182 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3183 }
3184
3185 #ifdef CONFIG_PM
3186 static int rt5663_suspend(struct snd_soc_component *component)
3187 {
3188 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3189
3190 if (rt5663->irq)
3191 disable_irq(rt5663->irq);
3192
3193 cancel_delayed_work_sync(&rt5663->jack_detect_work);
3194 cancel_delayed_work_sync(&rt5663->jd_unplug_work);
3195
3196 regcache_cache_only(rt5663->regmap, true);
3197 regcache_mark_dirty(rt5663->regmap);
3198
3199 return 0;
3200 }
3201
3202 static int rt5663_resume(struct snd_soc_component *component)
3203 {
3204 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3205
3206 regcache_cache_only(rt5663->regmap, false);
3207 regcache_sync(rt5663->regmap);
3208
3209 rt5663_irq(0, rt5663);
3210
3211 if (rt5663->irq)
3212 enable_irq(rt5663->irq);
3213
3214 return 0;
3215 }
3216 #else
3217 #define rt5663_suspend NULL
3218 #define rt5663_resume NULL
3219 #endif
3220
3221 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3222 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3223 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3224
3225 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3226 .hw_params = rt5663_hw_params,
3227 .set_fmt = rt5663_set_dai_fmt,
3228 .set_sysclk = rt5663_set_dai_sysclk,
3229 .set_pll = rt5663_set_dai_pll,
3230 .set_tdm_slot = rt5663_set_tdm_slot,
3231 .set_bclk_ratio = rt5663_set_bclk_ratio,
3232 };
3233
3234 static struct snd_soc_dai_driver rt5663_dai[] = {
3235 {
3236 .name = "rt5663-aif",
3237 .id = RT5663_AIF,
3238 .playback = {
3239 .stream_name = "AIF Playback",
3240 .channels_min = 1,
3241 .channels_max = 2,
3242 .rates = RT5663_STEREO_RATES,
3243 .formats = RT5663_FORMATS,
3244 },
3245 .capture = {
3246 .stream_name = "AIF Capture",
3247 .channels_min = 1,
3248 .channels_max = 2,
3249 .rates = RT5663_STEREO_RATES,
3250 .formats = RT5663_FORMATS,
3251 },
3252 .ops = &rt5663_aif_dai_ops,
3253 },
3254 };
3255
3256 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3257 .probe = rt5663_probe,
3258 .remove = rt5663_remove,
3259 .suspend = rt5663_suspend,
3260 .resume = rt5663_resume,
3261 .set_bias_level = rt5663_set_bias_level,
3262 .controls = rt5663_snd_controls,
3263 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
3264 .dapm_widgets = rt5663_dapm_widgets,
3265 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3266 .dapm_routes = rt5663_dapm_routes,
3267 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3268 .set_jack = rt5663_set_jack_detect,
3269 .use_pmdown_time = 1,
3270 .endianness = 1,
3271 };
3272
3273 static const struct regmap_config rt5663_v2_regmap = {
3274 .reg_bits = 16,
3275 .val_bits = 16,
3276 .use_single_read = true,
3277 .use_single_write = true,
3278 .max_register = 0x07fa,
3279 .volatile_reg = rt5663_v2_volatile_register,
3280 .readable_reg = rt5663_v2_readable_register,
3281 .cache_type = REGCACHE_MAPLE,
3282 .reg_defaults = rt5663_v2_reg,
3283 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3284 };
3285
3286 static const struct regmap_config rt5663_regmap = {
3287 .reg_bits = 16,
3288 .val_bits = 16,
3289 .use_single_read = true,
3290 .use_single_write = true,
3291 .max_register = 0x03f3,
3292 .volatile_reg = rt5663_volatile_register,
3293 .readable_reg = rt5663_readable_register,
3294 .cache_type = REGCACHE_MAPLE,
3295 .reg_defaults = rt5663_reg,
3296 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3297 };
3298
3299 static const struct regmap_config temp_regmap = {
3300 .name = "nocache",
3301 .reg_bits = 16,
3302 .val_bits = 16,
3303 .use_single_read = true,
3304 .use_single_write = true,
3305 .max_register = 0x03f3,
3306 .cache_type = REGCACHE_NONE,
3307 };
3308
3309 static const struct i2c_device_id rt5663_i2c_id[] = {
3310 { "rt5663" },
3311 {}
3312 };
3313 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3314
3315 #if defined(CONFIG_OF)
3316 static const struct of_device_id rt5663_of_match[] = {
3317 { .compatible = "realtek,rt5663", },
3318 {},
3319 };
3320 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3321 #endif
3322
3323 #ifdef CONFIG_ACPI
3324 static const struct acpi_device_id rt5663_acpi_match[] = {
3325 { "10EC5663", 0},
3326 {},
3327 };
3328 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3329 #endif
3330
3331 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3332 {
3333 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3334 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3335 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3336 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3337 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3338 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3339 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3340 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3341 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3342 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3343 msleep(40);
3344 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3345 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3346 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3347 msleep(500);
3348 }
3349
3350 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3351 {
3352 int value, count;
3353
3354 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3355 msleep(20);
3356 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3357 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3358 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3359 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3360 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3361 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3362 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3363 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3364 regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3365 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3366 msleep(30);
3367 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3368 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3369 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3370 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3371 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3372 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3373 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3374 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3375 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3376 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3377
3378 count = 0;
3379 while (true) {
3380 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3381 if (!(value & 0x80))
3382 usleep_range(10000, 10005);
3383 else
3384 break;
3385
3386 if (++count > 200)
3387 break;
3388 }
3389
3390 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3391 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3392 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3393 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3394 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3395 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3396 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3397 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3398 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3399 regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3400 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3401 msleep(40);
3402 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3403 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3404 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3405 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3406 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3407 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3408 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3409 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3410 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3411 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3412 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3413 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3414 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3415 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3416 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3417 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3418 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3419 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3420 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3421 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3422 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3423 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3424 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3425
3426 count = 0;
3427 while (true) {
3428 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3429 if (value & 0x8000)
3430 usleep_range(10000, 10005);
3431 else
3432 break;
3433
3434 if (count > 200)
3435 return;
3436 count++;
3437 }
3438
3439 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3440 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3441 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3442
3443 count = 0;
3444 while (true) {
3445 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3446 if (value & 0x8000)
3447 usleep_range(10000, 10005);
3448 else
3449 break;
3450
3451 if (count > 200)
3452 return;
3453 count++;
3454 }
3455
3456 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3457 usleep_range(10000, 10005);
3458 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3459 usleep_range(10000, 10005);
3460 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3461 usleep_range(10000, 10005);
3462 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3463 usleep_range(10000, 10005);
3464 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3465 usleep_range(10000, 10005);
3466 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3467 usleep_range(10000, 10005);
3468 }
3469
3470 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3471 {
3472 int table_size;
3473 int ret;
3474
3475 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3476 &rt5663->pdata.dc_offset_l_manual);
3477 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3478 &rt5663->pdata.dc_offset_r_manual);
3479 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3480 &rt5663->pdata.dc_offset_l_manual_mic);
3481 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3482 &rt5663->pdata.dc_offset_r_manual_mic);
3483 device_property_read_u32(dev, "realtek,impedance_sensing_num",
3484 &rt5663->pdata.impedance_sensing_num);
3485
3486 if (rt5663->pdata.impedance_sensing_num) {
3487 table_size = sizeof(struct impedance_mapping_table) *
3488 rt5663->pdata.impedance_sensing_num;
3489 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3490 if (!rt5663->imp_table)
3491 return -ENOMEM;
3492 ret = device_property_read_u32_array(dev,
3493 "realtek,impedance_sensing_table",
3494 (u32 *)rt5663->imp_table, table_size);
3495 if (ret)
3496 return ret;
3497 }
3498
3499 return 0;
3500 }
3501
3502 static int rt5663_i2c_probe(struct i2c_client *i2c)
3503 {
3504 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3505 struct rt5663_priv *rt5663;
3506 int ret, i;
3507 unsigned int val;
3508 struct regmap *regmap;
3509
3510 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3511 GFP_KERNEL);
3512
3513 if (rt5663 == NULL)
3514 return -ENOMEM;
3515
3516 i2c_set_clientdata(i2c, rt5663);
3517
3518 if (pdata)
3519 rt5663->pdata = *pdata;
3520 else {
3521 ret = rt5663_parse_dp(rt5663, &i2c->dev);
3522 if (ret)
3523 return ret;
3524 }
3525
3526 for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
3527 rt5663->supplies[i].supply = rt5663_supply_names[i];
3528
3529 ret = devm_regulator_bulk_get(&i2c->dev,
3530 ARRAY_SIZE(rt5663->supplies),
3531 rt5663->supplies);
3532 if (ret) {
3533 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3534 return ret;
3535 }
3536
3537 /* Set load for regulator. */
3538 for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
3539 ret = regulator_set_load(rt5663->supplies[i].consumer,
3540 RT5663_SUPPLY_CURRENT_UA);
3541 if (ret < 0) {
3542 dev_err(&i2c->dev,
3543 "Failed to set regulator load on %s, ret: %d\n",
3544 rt5663->supplies[i].supply, ret);
3545 return ret;
3546 }
3547 }
3548
3549 ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
3550 rt5663->supplies);
3551
3552 if (ret) {
3553 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3554 return ret;
3555 }
3556 msleep(RT5663_POWER_ON_DELAY_MS);
3557
3558 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3559 if (IS_ERR(regmap)) {
3560 ret = PTR_ERR(regmap);
3561 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3562 ret);
3563 goto err_enable;
3564 }
3565
3566 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3567 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3568 dev_err(&i2c->dev,
3569 "Device with ID register %#x is not rt5663, retry one time.\n",
3570 val);
3571 msleep(100);
3572 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3573 }
3574
3575 switch (val) {
3576 case RT5663_DEVICE_ID_2:
3577 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3578 rt5663->codec_ver = CODEC_VER_1;
3579 break;
3580 case RT5663_DEVICE_ID_1:
3581 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3582 rt5663->codec_ver = CODEC_VER_0;
3583 break;
3584 default:
3585 dev_err(&i2c->dev,
3586 "Device with ID register %#x is not rt5663\n",
3587 val);
3588 ret = -ENODEV;
3589 goto err_enable;
3590 }
3591
3592 if (IS_ERR(rt5663->regmap)) {
3593 ret = PTR_ERR(rt5663->regmap);
3594 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3595 ret);
3596 goto err_enable;
3597 }
3598
3599 /* reset and calibrate */
3600 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3601 regcache_cache_bypass(rt5663->regmap, true);
3602 switch (rt5663->codec_ver) {
3603 case CODEC_VER_1:
3604 rt5663_v2_calibrate(rt5663);
3605 break;
3606 case CODEC_VER_0:
3607 rt5663_calibrate(rt5663);
3608 break;
3609 default:
3610 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3611 }
3612 regcache_cache_bypass(rt5663->regmap, false);
3613 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3614 dev_dbg(&i2c->dev, "calibrate done\n");
3615
3616 switch (rt5663->codec_ver) {
3617 case CODEC_VER_1:
3618 break;
3619 case CODEC_VER_0:
3620 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3621 ARRAY_SIZE(rt5663_patch_list));
3622 if (ret != 0)
3623 dev_warn(&i2c->dev,
3624 "Failed to apply regmap patch: %d\n", ret);
3625 break;
3626 default:
3627 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3628 }
3629
3630 /* GPIO1 as IRQ */
3631 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3632 RT5663_GP1_PIN_IRQ);
3633 /* 4btn inline command debounce */
3634 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3635 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3636
3637 switch (rt5663->codec_ver) {
3638 case CODEC_VER_1:
3639 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3640 /* JD1 */
3641 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3642 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3643 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3644 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3645 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3646 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3647 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3648
3649 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3650 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3651 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3652 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3653 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3654 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3655 /* Set GPIO4 and GPIO8 as input for combo jack */
3656 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3657 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3658 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3659 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3660 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3661 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3662 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3663 break;
3664 case CODEC_VER_0:
3665 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3666 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3667 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3668 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3669 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3670 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3671 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3672 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3673 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3674 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3675 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3676 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3677 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3678 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3679 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3680 RT5663_DATA_SWAP_ADCDAT1_MASK,
3681 RT5663_DATA_SWAP_ADCDAT1_LL);
3682 break;
3683 default:
3684 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3685 }
3686
3687 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3688 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3689
3690 if (i2c->irq) {
3691 ret = request_irq(i2c->irq, rt5663_irq,
3692 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3693 | IRQF_ONESHOT, "rt5663", rt5663);
3694 if (ret) {
3695 dev_err(&i2c->dev, "%s Failed to request IRQ: %d\n",
3696 __func__, ret);
3697 goto err_enable;
3698 }
3699 rt5663->irq = i2c->irq;
3700 }
3701
3702 ret = devm_snd_soc_register_component(&i2c->dev,
3703 &soc_component_dev_rt5663,
3704 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3705
3706 if (ret)
3707 goto err_enable;
3708
3709 return 0;
3710
3711
3712 /*
3713 * Error after enabling regulators should goto err_enable
3714 * to disable regulators.
3715 */
3716 err_enable:
3717 if (i2c->irq)
3718 free_irq(i2c->irq, rt5663);
3719
3720 regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3721 return ret;
3722 }
3723
3724 static void rt5663_i2c_remove(struct i2c_client *i2c)
3725 {
3726 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3727
3728 if (i2c->irq)
3729 free_irq(i2c->irq, rt5663);
3730
3731 regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3732 }
3733
3734 static void rt5663_i2c_shutdown(struct i2c_client *client)
3735 {
3736 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3737
3738 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3739 }
3740
3741 static struct i2c_driver rt5663_i2c_driver = {
3742 .driver = {
3743 .name = "rt5663",
3744 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3745 .of_match_table = of_match_ptr(rt5663_of_match),
3746 },
3747 .probe = rt5663_i2c_probe,
3748 .remove = rt5663_i2c_remove,
3749 .shutdown = rt5663_i2c_shutdown,
3750 .id_table = rt5663_i2c_id,
3751 };
3752 module_i2c_driver(rt5663_i2c_driver);
3753
3754 MODULE_DESCRIPTION("ASoC RT5663 driver");
3755 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3756 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes