sound/soc/codecs/uda1342.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Audio support for NXP UDA1342
   4  *
   5  * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
   6  * Copyright (c) 2024 Binbin Zhou <zhoubinbin@loongson.cn>
   7  */
   8
   9 #ifndef _UDA1342_H
  10 #define _UDA1342_H
  11
  12 #define UDA1342_CLK             0x00
  13 #define UDA1342_IFACE           0x01
  14 #define UDA1342_PM              0x02
  15 #define UDA1342_AMIX            0x03
  16 #define UDA1342_HP              0x04
  17 #define UDA1342_MVOL            0x11
  18 #define UDA1342_MIXVOL          0x12
  19 #define UDA1342_MODE            0x12
  20 #define UDA1342_DEEMP           0x13
  21 #define UDA1342_MIXER           0x14
  22 #define UDA1342_INTSTAT         0x18
  23 #define UDA1342_DEC             0x20
  24 #define UDA1342_PGA             0x21
  25 #define UDA1342_ADC             0x22
  26 #define UDA1342_AGC             0x23
  27 #define UDA1342_DECSTAT         0x28
  28 #define UDA1342_RESET           0x7f
  29
  30 /* Register flags */
  31 #define R00_EN_ADC              0x0800
  32 #define R00_EN_DEC              0x0400
  33 #define R00_EN_DAC              0x0200
  34 #define R00_EN_INT              0x0100
  35 #define R00_DAC_CLK             0x0010
  36 #define R01_SFORI_I2S           0x0000
  37 #define R01_SFORI_LSB16         0x0100
  38 #define R01_SFORI_LSB18         0x0200
  39 #define R01_SFORI_LSB20         0x0300
  40 #define R01_SFORI_MSB           0x0500
  41 #define R01_SFORI_MASK          0x0700
  42 #define R01_SFORO_I2S           0x0000
  43 #define R01_SFORO_LSB16         0x0001
  44 #define R01_SFORO_LSB18         0x0002
  45 #define R01_SFORO_LSB20         0x0003
  46 #define R01_SFORO_LSB24         0x0004
  47 #define R01_SFORO_MSB           0x0005
  48 #define R01_SFORO_MASK          0x0007
  49 #define R01_SEL_SOURCE          0x0040
  50 #define R01_SIM                 0x0010
  51 #define R02_PON_PLL             0x8000
  52 #define R02_PON_HP              0x2000
  53 #define R02_PON_DAC             0x0400
  54 #define R02_PON_BIAS            0x0100
  55 #define R02_EN_AVC              0x0080
  56 #define R02_PON_AVC             0x0040
  57 #define R02_PON_LNA             0x0010
  58 #define R02_PON_PGAL            0x0008
  59 #define R02_PON_ADCL            0x0004
  60 #define R02_PON_PGAR            0x0002
  61 #define R02_PON_ADCR            0x0001
  62 #define R13_MTM                 0x4000
  63 #define R14_SILENCE             0x0080
  64 #define R14_SDET_ON             0x0040
  65 #define R21_MT_ADC              0x8000
  66 #define R22_SEL_LNA             0x0008
  67 #define R22_SEL_MIC             0x0004
  68 #define R22_SKIP_DCFIL          0x0002
  69 #define R23_AGC_EN              0x0001
  70
  71 #define UDA1342_DAI_DUPLEX      0 /* playback and capture on single DAI */
  72 #define UDA1342_DAI_PLAYBACK    1 /* playback DAI */
  73 #define UDA1342_DAI_CAPTURE     2 /* capture DAI */
  74
  75 #define STATUS0_DAIFMT_MASK (~(7 << 1))
  76 #define STATUS0_SYSCLK_MASK (~(3 << 4))
  77
  78 #endif /* _UDA1342_H */