sound/soc/qcom/qdsp6/audioreach.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef __AUDIOREACH_H__
   4 #define __AUDIOREACH_H__
   5 #include <linux/types.h>
   6 #include <linux/soc/qcom/apr.h>
   7 #include <sound/soc.h>
   8 struct q6apm;
   9 struct q6apm_graph;
  10
  11 /* Module IDs */
  12 #define MODULE_ID_WR_SHARED_MEM_EP      0x07001000
  13 #define MODULE_ID_RD_SHARED_MEM_EP      0x07001001
  14 #define MODULE_ID_GAIN                  0x07001002
  15 #define MODULE_ID_PCM_CNV               0x07001003
  16 #define MODULE_ID_PCM_ENC               0x07001004
  17 #define MODULE_ID_PCM_DEC               0x07001005
  18 #define MODULE_ID_PLACEHOLDER_ENCODER   0x07001008
  19 #define MODULE_ID_PLACEHOLDER_DECODER   0x07001009
  20 #define MODULE_ID_SAL                   0x07001010
  21 #define MODULE_ID_MFC                   0x07001015
  22 #define MODULE_ID_CODEC_DMA_SINK        0x07001023
  23 #define MODULE_ID_CODEC_DMA_SOURCE      0x07001024
  24 #define MODULE_ID_I2S_SINK              0x0700100A
  25 #define MODULE_ID_I2S_SOURCE            0x0700100B
  26 #define MODULE_ID_DATA_LOGGING          0x0700101A
  27 #define MODULE_ID_AAC_DEC               0x0700101F
  28 #define MODULE_ID_FLAC_DEC              0x0700102F
  29 #define MODULE_ID_MP3_DECODE            0x0700103B
  30 #define MODULE_ID_GAPLESS               0x0700104D
  31 #define MODULE_ID_DISPLAY_PORT_SINK     0x07001069
  32
  33 #define APM_CMD_GET_SPF_STATE           0x01001021
  34 #define APM_CMD_RSP_GET_SPF_STATE       0x02001007
  35
  36 #define APM_MODULE_INSTANCE_ID          0x00000001
  37 #define PRM_MODULE_INSTANCE_ID          0x00000002
  38 #define AMDB_MODULE_INSTANCE_ID         0x00000003
  39 #define VCPM_MODULE_INSTANCE_ID         0x00000004
  40 #define AR_MODULE_INSTANCE_ID_START     0x00006000
  41 #define AR_MODULE_INSTANCE_ID_END       0x00007000
  42 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START     0x00007000
  43 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END       0x00008000
  44 #define AR_CONT_INSTANCE_ID_START       0x00005000
  45 #define AR_CONT_INSTANCE_ID_END         0x00006000
  46 #define AR_SG_INSTANCE_ID_START         0x00004000
  47
  48 #define APM_CMD_GRAPH_OPEN                      0x01001000
  49 #define APM_CMD_GRAPH_PREPARE                   0x01001001
  50 #define APM_CMD_GRAPH_START                     0x01001002
  51 #define APM_CMD_GRAPH_STOP                      0x01001003
  52 #define APM_CMD_GRAPH_CLOSE                     0x01001004
  53 #define APM_CMD_GRAPH_FLUSH                     0x01001005
  54 #define APM_CMD_SET_CFG                         0x01001006
  55 #define APM_CMD_GET_CFG                         0x01001007
  56 #define APM_CMD_SHARED_MEM_MAP_REGIONS          0x0100100C
  57 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS        0x0100100D
  58 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS      0x02001001
  59 #define APM_CMD_RSP_GET_CFG                     0x02001000
  60 #define APM_CMD_CLOSE_ALL                       0x01001013
  61 #define APM_CMD_REGISTER_SHARED_CFG             0x0100100A
  62
  63 #define APM_MEMORY_MAP_SHMEM8_4K_POOL           3
  64
  65 struct apm_cmd_shared_mem_map_regions {
  66         uint16_t mem_pool_id;
  67         uint16_t num_regions;
  68         uint32_t property_flag;
  69 } __packed;
  70
  71 struct apm_shared_map_region_payload {
  72         uint32_t shm_addr_lsw;
  73         uint32_t shm_addr_msw;
  74         uint32_t mem_size_bytes;
  75 } __packed;
  76
  77 struct apm_cmd_shared_mem_unmap_regions {
  78         uint32_t mem_map_handle;
  79 } __packed;
  80
  81 struct apm_cmd_rsp_shared_mem_map_regions {
  82         uint32_t mem_map_handle;
  83 } __packed;
  84
  85 /* APM module */
  86 #define APM_PARAM_ID_SUB_GRAPH_LIST             0x08001005
  87
  88 #define APM_PARAM_ID_MODULE_LIST                0x08001002
  89
  90 struct apm_param_id_modules_list {
  91         uint32_t num_modules_list;
  92 } __packed;
  93
  94 #define APM_PARAM_ID_MODULE_PROP                0x08001003
  95
  96 struct apm_param_id_module_prop {
  97         uint32_t num_modules_prop_cfg;
  98 } __packed;
  99
 100 struct apm_module_prop_cfg {
 101         uint32_t instance_id;
 102         uint32_t num_props;
 103 } __packed;
 104
 105 #define APM_PARAM_ID_MODULE_CONN                0x08001004
 106
 107 struct apm_param_id_module_conn {
 108         uint32_t num_connections;
 109 } __packed;
 110
 111 struct apm_module_conn_obj {
 112         uint32_t src_mod_inst_id;
 113         uint32_t src_mod_op_port_id;
 114         uint32_t dst_mod_inst_id;
 115         uint32_t dst_mod_ip_port_id;
 116 } __packed;
 117
 118 #define APM_PARAM_ID_GAIN                       0x08001006
 119
 120 struct param_id_gain_cfg {
 121         uint16_t gain;
 122         uint16_t reserved;
 123 } __packed;
 124
 125 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG          0x08001008
 126
 127 struct param_id_pcm_output_format_cfg {
 128         uint32_t data_format;
 129         uint32_t fmt_id;
 130         uint32_t payload_size;
 131 } __packed;
 132
 133 struct payload_pcm_output_format_cfg {
 134         uint16_t bit_width;
 135         uint16_t alignment;
 136         uint16_t bits_per_sample;
 137         uint16_t q_factor;
 138         uint16_t endianness;
 139         uint16_t interleaved;
 140         uint16_t reserved;
 141         uint16_t num_channels;
 142         uint8_t channel_mapping[];
 143 } __packed;
 144
 145 #define PARAM_ID_ENC_BITRATE                    0x08001052
 146
 147 struct param_id_enc_bitrate_param {
 148         uint32_t bitrate;
 149 } __packed;
 150
 151 #define DATA_FORMAT_FIXED_POINT         1
 152 #define DATA_FORMAT_GENERIC_COMPRESSED  5
 153 #define DATA_FORMAT_RAW_COMPRESSED      6
 154 #define PCM_LSB_ALIGNED                 1
 155 #define PCM_MSB_ALIGNED                 2
 156 #define PCM_LITTLE_ENDIAN               1
 157 #define PCM_BIT_ENDIAN                  2
 158
 159 #define MEDIA_FMT_ID_PCM        0x09001000
 160 #define MEDIA_FMT_ID_MP3        0x09001009
 161 #define SAMPLE_RATE_48K         48000
 162 #define BIT_WIDTH_16            16
 163
 164 #define APM_PARAM_ID_PROP_PORT_INFO             0x08001015
 165
 166 struct apm_modules_prop_info {
 167         uint32_t max_ip_port;
 168         uint32_t max_op_port;
 169 } __packed;
 170
 171 /* Shared memory module */
 172 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER       0x04001000
 173 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG       BIT(31)
 174 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG           BIT(30)
 175 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG           BIT(29)
 176 #define WR_SH_MEM_EP_EOF_FLAG                   BIT(4)
 177
 178 struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
 179         uint32_t buf_addr_lsw;
 180         uint32_t buf_addr_msw;
 181         uint32_t mem_map_handle;
 182         uint32_t buf_size;
 183         uint32_t timestamp_lsw;
 184         uint32_t timestamp_msw;
 185         uint32_t flags;
 186 } __packed;
 187
 188 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2    0x0400100A
 189
 190 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
 191         uint32_t buf_addr_lsw;
 192         uint32_t buf_addr_msw;
 193         uint32_t mem_map_handle;
 194         uint32_t buf_size;
 195         uint32_t timestamp_lsw;
 196         uint32_t timestamp_msw;
 197         uint32_t flags;
 198         uint32_t md_addr_lsw;
 199         uint32_t md_addr_msw;
 200         uint32_t md_map_handle;
 201         uint32_t md_buf_size;
 202 } __packed;
 203
 204 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE      0x05001000
 205
 206 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
 207         uint32_t buf_addr_lsw;
 208         uint32_t buf_addr_msw;
 209         uint32_t mem_map_handle;
 210         uint32_t status;
 211
 212 } __packed;
 213
 214 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2   0x05001004
 215
 216 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
 217         uint32_t buf_addr_lsw;
 218         uint32_t buf_addr_msw;
 219         uint32_t mem_map_handle;
 220         uint32_t status;
 221         uint32_t md_buf_addr_lsw;
 222         uint32_t md_buf_addr_msw;
 223         uint32_t md_mem_map_handle;
 224         uint32_t md_status;
 225 } __packed;
 226
 227 #define PARAM_ID_MEDIA_FORMAT                           0x0800100C
 228 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT              0x04001001
 229
 230 struct apm_media_format {
 231         uint32_t data_format;
 232         uint32_t fmt_id;
 233         uint32_t payload_size;
 234 } __packed;
 235
 236 #define MEDIA_FMT_ID_FLAC       0x09001004
 237
 238 struct payload_media_fmt_flac_t {
 239         uint16_t num_channels;
 240         uint16_t sample_size;
 241         uint16_t min_blk_size;
 242         uint16_t max_blk_size;
 243         uint32_t sample_rate;
 244         uint32_t min_frame_size;
 245         uint32_t max_frame_size;
 246 } __packed;
 247
 248 #define MEDIA_FMT_ID_AAC        0x09001001
 249
 250 struct payload_media_fmt_aac_t {
 251         uint16_t aac_fmt_flag;
 252         uint16_t audio_obj_type;
 253         uint16_t num_channels;
 254         uint16_t total_size_of_PCE_bits;
 255         uint32_t sample_rate;
 256 } __packed;
 257
 258 #define DATA_CMD_WR_SH_MEM_EP_EOS                       0x04001002
 259 #define WR_SH_MEM_EP_EOS_POLICY_LAST    1
 260 #define WR_SH_MEM_EP_EOS_POLICY_EACH    2
 261
 262 struct data_cmd_wr_sh_mem_ep_eos {
 263         uint32_t policy;
 264
 265 } __packed;
 266
 267 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER               0x04001003
 268
 269 struct data_cmd_rd_sh_mem_ep_data_buffer {
 270         uint32_t buf_addr_lsw;
 271         uint32_t buf_addr_msw;
 272         uint32_t mem_map_handle;
 273         uint32_t buf_size;
 274 } __packed;
 275
 276 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER           0x05001002
 277
 278 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
 279         uint32_t status;
 280         uint32_t buf_addr_lsw;
 281         uint32_t buf_addr_msw;
 282         uint32_t mem_map_handle;
 283         uint32_t data_size;
 284         uint32_t offset;
 285         uint32_t timestamp_lsw;
 286         uint32_t timestamp_msw;
 287         uint32_t flags;
 288         uint32_t num_frames;
 289 } __packed;
 290
 291 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2            0x0400100B
 292
 293 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
 294         uint32_t buf_addr_lsw;
 295         uint32_t buf_addr_msw;
 296         uint32_t mem_map_handle;
 297         uint32_t buf_size;
 298         uint32_t md_buf_addr_lsw;
 299         uint32_t md_buf_addr_msw;
 300         uint32_t md_mem_map_handle;
 301         uint32_t md_buf_size;
 302 } __packed;
 303
 304 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2        0x05001005
 305
 306 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
 307         uint32_t status;
 308         uint32_t buf_addr_lsw;
 309         uint32_t buf_addr_msw;
 310         uint32_t mem_map_handle;
 311         uint32_t data_size;
 312         uint32_t offset;
 313         uint32_t timestamp_lsw;
 314         uint32_t timestamp_msw;
 315         uint32_t flags;
 316         uint32_t num_frames;
 317         uint32_t md_status;
 318         uint32_t md_buf_addr_lsw;
 319         uint32_t md_buf_addr_msw;
 320         uint32_t md_mem_map_handle;
 321         uint32_t md_size;
 322 } __packed;
 323
 324 #define PARAM_ID_RD_SH_MEM_CFG                          0x08001007
 325
 326 struct param_id_rd_sh_mem_cfg {
 327         uint32_t num_frames_per_buffer;
 328         uint32_t metadata_control_flags;
 329
 330 } __packed;
 331
 332 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED              0x05001001
 333
 334 struct data_cmd_wr_sh_mem_ep_eos_rendered {
 335         uint32_t module_instance_id;
 336         uint32_t render_status;
 337 } __packed;
 338
 339 #define MODULE_ID_WR_SHARED_MEM_EP                      0x07001000
 340
 341 struct apm_cmd_header {
 342         uint32_t payload_address_lsw;
 343         uint32_t payload_address_msw;
 344         uint32_t mem_map_handle;
 345         uint32_t payload_size;
 346 } __packed;
 347
 348 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
 349
 350 struct apm_module_param_data  {
 351         uint32_t module_instance_id;
 352         uint32_t param_id;
 353         uint32_t param_size;
 354         uint32_t error_code;
 355 } __packed;
 356
 357 #define APM_MODULE_PARAM_DATA_SIZE      sizeof(struct apm_module_param_data)
 358
 359 struct apm_module_param_shared_data  {
 360         uint32_t param_id;
 361         uint32_t param_size;
 362 } __packed;
 363
 364 struct apm_prop_data {
 365         uint32_t prop_id;
 366         uint32_t prop_size;
 367 } __packed;
 368
 369 /* Sub-Graph Properties */
 370 #define APM_PARAM_ID_SUB_GRAPH_CONFIG   0x08001001
 371
 372 struct apm_param_id_sub_graph_cfg {
 373         uint32_t num_sub_graphs;
 374 } __packed;
 375
 376 struct apm_sub_graph_cfg {
 377         uint32_t sub_graph_id;
 378         uint32_t num_sub_graph_prop;
 379 } __packed;
 380
 381 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE         0x0800100E
 382
 383 struct apm_sg_prop_id_perf_mode {
 384         uint32_t perf_mode;
 385 } __packed;
 386
 387 #define APM_SG_PROP_ID_PERF_MODE_SIZE   4
 388
 389 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
 390
 391 struct apm_sg_prop_id_direction {
 392         uint32_t direction;
 393 } __packed;
 394
 395 #define APM_SG_PROP_ID_DIR_SIZE         4
 396
 397 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID       0x08001010
 398 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK        0x1
 399 #define APM_SUB_GRAPH_SID_AUDIO_RECORD          0x2
 400 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL      0x3
 401
 402 struct apm_sg_prop_id_scenario_id {
 403         uint32_t scenario_id;
 404 } __packed;
 405
 406 #define APM_SG_PROP_ID_SID_SIZE                 4
 407 /* container api */
 408 #define APM_PARAM_ID_CONTAINER_CONFIG           0x08001000
 409
 410 struct apm_param_id_container_cfg {
 411         uint32_t num_containers;
 412 } __packed;
 413
 414 struct apm_container_cfg {
 415         uint32_t container_id;
 416         uint32_t num_prop;
 417 } __packed;
 418
 419 struct apm_cont_capability  {
 420         uint32_t capability_id;
 421 } __packed;
 422
 423 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST   0x08001011
 424 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE   8
 425
 426 #define APM_PROP_ID_INVALID                     0x0
 427 #define APM_CONTAINER_CAP_ID_PP                 0x1
 428 #define APM_CONTAINER_CAP_ID_PP                 0x1
 429
 430 struct apm_cont_prop_id_cap_list  {
 431         uint32_t num_capability_id;
 432 } __packed;
 433
 434 #define APM_CONTAINER_PROP_ID_GRAPH_POS         0x08001012
 435
 436 struct apm_cont_prop_id_graph_pos  {
 437         uint32_t graph_pos;
 438 } __packed;
 439
 440 #define APM_CONTAINER_PROP_ID_STACK_SIZE        0x08001013
 441
 442 struct apm_cont_prop_id_stack_size  {
 443         uint32_t stack_size;
 444 } __packed;
 445
 446 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN       0x08001014
 447
 448 struct apm_cont_prop_id_domain  {
 449         uint32_t proc_domain;
 450 } __packed;
 451
 452 #define CONFIG_I2S_WS_SRC_EXTERNAL              0x0
 453 #define CONFIG_I2S_WS_SRC_INTERNAL              0x1
 454
 455 #define PARAM_ID_I2S_INTF_CFG                   0x08001019
 456 struct param_id_i2s_intf_cfg {
 457         uint32_t lpaif_type;
 458         uint32_t intf_idx;
 459         uint16_t sd_line_idx;
 460         uint16_t ws_src;
 461 } __packed;
 462
 463 #define I2S_INTF_TYPE_PRIMARY           0
 464 #define I2S_INTF_TYPE_SECOINDARY        1
 465 #define I2S_INTF_TYPE_TERTINARY         2
 466 #define I2S_INTF_TYPE_QUATERNARY        3
 467 #define I2S_INTF_TYPE_QUINARY           4
 468 #define I2S_SD0                         1
 469 #define I2S_SD1                         2
 470 #define I2S_SD2                         3
 471 #define I2S_SD3                         4
 472
 473 #define PORT_ID_I2S_INPUT               2
 474 #define PORT_ID_I2S_OUPUT               1
 475 #define I2S_STACK_SIZE                  2048
 476
 477 #define PARAM_ID_DISPLAY_PORT_INTF_CFG          0x08001154
 478
 479 struct param_id_display_port_intf_cfg {
 480         uint32_t channel_allocation;
 481         /* Multi-Steam Transport index */
 482         uint32_t mst_idx;
 483         uint32_t dptx_idx;
 484 } __packed;
 485
 486 #define PARAM_ID_HW_EP_MF_CFG                   0x08001017
 487 struct param_id_hw_ep_mf {
 488         uint32_t sample_rate;
 489         uint16_t bit_width;
 490         uint16_t num_channels;
 491         uint32_t data_format;
 492 } __packed;
 493
 494 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR        0x08001018
 495
 496 struct param_id_fram_size_factor {
 497         uint32_t frame_size_factor;
 498 } __packed;
 499
 500 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID       0x080010CB
 501
 502 struct apm_cont_prop_id_parent_container  {
 503         uint32_t parent_container_id;
 504 } __packed;
 505
 506 #define APM_CONTAINER_PROP_ID_HEAP_ID                   0x08001174
 507 #define APM_CONT_HEAP_DEFAULT                           0x1
 508 #define APM_CONT_HEAP_LOW_POWER                         0x2
 509
 510 struct apm_cont_prop_id_headp_id  {
 511         uint32_t heap_id;
 512 } __packed;
 513
 514 struct apm_modules_list {
 515         uint32_t sub_graph_id;
 516         uint32_t container_id;
 517         uint32_t num_modules;
 518 } __packed;
 519
 520 struct apm_module_obj {
 521         uint32_t module_id;
 522         uint32_t instance_id;
 523 } __packed;
 524
 525 #define APM_MODULE_PROP_ID_PORT_INFO            0x08001015
 526 #define APM_MODULE_PROP_ID_PORT_INFO_SZ         8
 527 struct apm_module_prop_id_port_info {
 528         uint32_t max_ip_port;
 529         uint32_t max_op_port;
 530 } __packed;
 531
 532 #define DATA_LOGGING_MAX_INPUT_PORTS            0x1
 533 #define DATA_LOGGING_MAX_OUTPUT_PORTS           0x1
 534 #define DATA_LOGGING_STACK_SIZE                 2048
 535 #define PARAM_ID_DATA_LOGGING_CONFIG            0x08001031
 536
 537 struct data_logging_config {
 538         uint32_t log_code;
 539         uint32_t log_tap_point_id;
 540         uint32_t mode;
 541 } __packed;
 542
 543 #define PARAM_ID_SAL_OUTPUT_CFG                 0x08001016
 544 struct param_id_sal_output_config {
 545         uint32_t bits_per_sample;
 546 } __packed;
 547
 548 #define PARAM_ID_SAL_LIMITER_ENABLE             0x0800101E
 549 struct param_id_sal_limiter_enable {
 550         uint32_t enable_lim;
 551 } __packed;
 552
 553 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT        0x08001024
 554 #define PARAM_ID_EARLY_EOS_DELAY                0x0800114C
 555 #define EARLY_EOS_DELAY_MS                      150
 556
 557 struct param_id_mfc_media_format {
 558         uint32_t sample_rate;
 559         uint16_t bit_width;
 560         uint16_t num_channels;
 561         uint16_t channel_mapping[];
 562 } __packed;
 563
 564 struct param_id_gapless_early_eos_delay_t {
 565         uint32_t early_eos_delay_ms;
 566 } __packed;
 567
 568 struct media_format {
 569         uint32_t data_format;
 570         uint32_t fmt_id;
 571         uint32_t payload_size;
 572 } __packed;
 573
 574 struct payload_media_fmt_pcm {
 575         uint32_t sample_rate;
 576         uint16_t bit_width;
 577         uint16_t alignment;
 578         uint16_t bits_per_sample;
 579         uint16_t q_factor;
 580         uint16_t endianness;
 581         uint16_t num_channels;
 582         uint8_t channel_mapping[];
 583 } __packed;
 584
 585 #define PARAM_ID_MODULE_ENABLE                  0x08001026
 586 struct param_id_module_enable {
 587         uint32_t enable;
 588 } __packed;
 589
 590 #define PARAM_ID_CODEC_DMA_INTF_CFG             0x08001063
 591
 592 struct param_id_codec_dma_intf_cfg {
 593         /* 1 - RXTX
 594          * 2 - WSA
 595          * 3 - VA
 596          * 4 - AXI
 597          */
 598         uint32_t lpaif_type;
 599         /*
 600          *  RX0 | TX0 = 1
 601          *  RX1 | TX1 = 2
 602          *  RX2 | TX2 = 3... so on
 603          */
 604         uint32_t intf_index;
 605         uint32_t active_channels_mask;
 606 } __packed;
 607
 608 struct audio_hw_clk_cfg {
 609         uint32_t clock_id;
 610         uint32_t clock_freq;
 611         uint32_t clock_attri;
 612         uint32_t clock_root;
 613 } __packed;
 614
 615 struct audio_hw_clk_rel_cfg {
 616         uint32_t clock_id;
 617 } __packed;
 618
 619 #define PARAM_ID_HW_EP_POWER_MODE_CFG   0x8001176
 620 #define AR_HW_EP_POWER_MODE_0   0 /* default */
 621 #define AR_HW_EP_POWER_MODE_1   1 /* XO Shutdown allowed */
 622 #define AR_HW_EP_POWER_MODE_2   2 /* XO Shutdown not allowed */
 623
 624 struct param_id_hw_ep_power_mode_cfg {
 625         uint32_t power_mode;
 626 } __packed;
 627
 628 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN   0x08001233
 629 #define AR_HW_EP_DMA_DATA_ALIGN_MSB     0
 630 #define AR_HW_EP_DMA_DATA_ALIGN_LSB     1
 631 #define AR_PCM_MAX_NUM_CHANNEL          8
 632
 633 struct param_id_hw_ep_dma_data_align {
 634         uint32_t dma_data_align;
 635 } __packed;
 636
 637 #define PARAM_ID_VOL_CTRL_MASTER_GAIN   0x08001035
 638 #define VOL_CTRL_DEFAULT_GAIN           0x2000
 639
 640 struct param_id_vol_ctrl_master_gain {
 641         uint16_t master_gain;
 642         uint16_t reserved;
 643 } __packed;
 644
 645
 646 #define PARAM_ID_REMOVE_INITIAL_SILENCE         0x0800114B
 647 #define PARAM_ID_REMOVE_TRAILING_SILENCE        0x0800115D
 648
 649 #define PARAM_ID_REAL_MODULE_ID 0x0800100B
 650
 651 struct param_id_placeholder_real_module_id {
 652         uint32_t real_module_id;
 653 } __packed;
 654
 655 /* Graph */
 656 struct audioreach_connection {
 657         /* Connections */
 658         uint32_t src_mod_inst_id;
 659         uint32_t src_mod_op_port_id;
 660         uint32_t dst_mod_inst_id;
 661         uint32_t dst_mod_ip_port_id;
 662         struct list_head node;
 663 };
 664
 665 struct audioreach_graph_info {
 666         int id;
 667         uint32_t num_sub_graphs;
 668         struct list_head sg_list;
 669         /* DPCM connection from FE Graph to BE graph */
 670         uint32_t src_mod_inst_id;
 671         uint32_t src_mod_op_port_id;
 672         uint32_t dst_mod_inst_id;
 673         uint32_t dst_mod_ip_port_id;
 674 };
 675
 676 struct audioreach_sub_graph {
 677         uint32_t sub_graph_id;
 678         uint32_t perf_mode;
 679         uint32_t direction;
 680         uint32_t scenario_id;
 681         struct list_head node;
 682
 683         struct audioreach_graph_info *info;
 684         uint32_t num_containers;
 685         struct list_head container_list;
 686 };
 687
 688 struct audioreach_container {
 689         uint32_t container_id;
 690         uint32_t capability_id;
 691         uint32_t graph_pos;
 692         uint32_t stack_size;
 693         uint32_t proc_domain;
 694         struct list_head node;
 695
 696         uint32_t num_modules;
 697         struct list_head modules_list;
 698         struct audioreach_sub_graph *sub_graph;
 699 };
 700
 701 #define AR_MAX_MOD_LINKS        8
 702
 703 struct audioreach_module {
 704         uint32_t module_id;
 705         uint32_t instance_id;
 706
 707         uint32_t max_ip_port;
 708         uint32_t max_op_port;
 709
 710         uint32_t in_port;
 711         uint32_t out_port;
 712
 713         uint32_t num_connections;
 714         /* Connections */
 715         uint32_t src_mod_inst_id;
 716         uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS];
 717         uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS];
 718         uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS];
 719
 720         /* Format specifics */
 721         uint32_t ch_fmt;
 722         uint32_t rate;
 723         uint32_t bit_depth;
 724
 725         /* I2S module */
 726         uint32_t hw_interface_idx;
 727         uint32_t sd_line_idx;
 728         uint32_t ws_src;
 729         uint32_t frame_size_factor;
 730         uint32_t data_format;
 731         uint32_t hw_interface_type;
 732
 733         /* PCM module specific */
 734         uint32_t interleave_type;
 735
 736         /* GAIN/Vol Control Module */
 737         uint16_t gain;
 738
 739         /* Logging */
 740         uint32_t log_code;
 741         uint32_t log_tap_point_id;
 742         uint32_t log_mode;
 743
 744         /* bookkeeping */
 745         struct list_head node;
 746         struct audioreach_container *container;
 747         struct snd_soc_dapm_widget *widget;
 748 };
 749
 750 struct audioreach_module_config {
 751         int     direction;
 752         u32     sample_rate;
 753         u16     bit_width;
 754         u16     bits_per_sample;
 755
 756         u16     data_format;
 757         u16     num_channels;
 758         u16     dp_idx;
 759         u32     channel_allocation;
 760         u32     sd_line_mask;
 761         int     fmt;
 762         struct snd_codec codec;
 763         u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
 764 };
 765
 766 /* Packet Allocation routines */
 767 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
 768                                     token);
 769 void audioreach_set_default_channel_mapping(u8 *ch_map, int num_channels);
 770 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
 771                                uint32_t token, uint32_t src_port,
 772                                uint32_t dest_port);
 773 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
 774                                 uint32_t src_port);
 775 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
 776                            uint32_t token, uint32_t src_port,
 777                            uint32_t dest_port);
 778 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info
 779                                  *info);
 780 /* Topology specific */
 781 int audioreach_tplg_init(struct snd_soc_component *component);
 782
 783 /* Module specific */
 784 void audioreach_graph_free_buf(struct q6apm_graph *graph);
 785 int audioreach_map_memory_regions(struct q6apm_graph *graph,
 786                                   unsigned int dir, size_t period_sz,
 787                                   unsigned int periods,
 788                                   bool is_contiguous);
 789 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
 790                              struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
 791                              struct gpr_pkt *pkt, uint32_t rsp_opcode);
 792 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
 793                                    uint32_t rsp_opcode);
 794 int audioreach_set_media_format(struct q6apm_graph *graph,
 795                                 struct audioreach_module *module,
 796                                 struct audioreach_module_config *cfg);
 797 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
 798 int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
 799                                  struct audioreach_module *module, int vol);
 800 int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module,
 801                               uint32_t param_id, uint32_t param_val);
 802 int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg);
 803
 804 #endif /* __AUDIOREACH_H__ */