sound/soc/qcom/qdsp6/q6prm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef __Q6PRM_H__
   4 #define __Q6PRM_H__
   5
   6 /* Clock ID for Primary I2S IBIT */
   7 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT                          0x100
   8 /* Clock ID for Primary I2S EBIT */
   9 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT                          0x101
  10 /* Clock ID for Secondary I2S IBIT */
  11 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT                          0x102
  12 /* Clock ID for Secondary I2S EBIT */
  13 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT                          0x103
  14 /* Clock ID for Tertiary I2S IBIT */
  15 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT                          0x104
  16 /* Clock ID for Tertiary I2S EBIT */
  17 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT                          0x105
  18 /* Clock ID for Quartnery I2S IBIT */
  19 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT                         0x106
  20 /* Clock ID for Quartnery I2S EBIT */
  21 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT                         0x107
  22 /* Clock ID for Speaker I2S IBIT */
  23 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT                       0x108
  24 /* Clock ID for Speaker I2S EBIT */
  25 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT                       0x109
  26 /* Clock ID for Speaker I2S OSR */
  27 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR                        0x10A
  28
  29 /* Clock ID for QUINARY  I2S IBIT */
  30 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT                        0x10B
  31 /* Clock ID for QUINARY  I2S EBIT */
  32 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT                        0x10C
  33 /* Clock ID for SENARY  I2S IBIT */
  34 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT                        0x10D
  35 /* Clock ID for SENARY  I2S EBIT */
  36 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT                        0x10E
  37 /* Clock ID for INT0 I2S IBIT  */
  38 #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT                       0x10F
  39 /* Clock ID for INT1 I2S IBIT  */
  40 #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT                       0x110
  41 /* Clock ID for INT2 I2S IBIT  */
  42 #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT                       0x111
  43 /* Clock ID for INT3 I2S IBIT  */
  44 #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT                       0x112
  45 /* Clock ID for INT4 I2S IBIT  */
  46 #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT                       0x113
  47 /* Clock ID for INT5 I2S IBIT  */
  48 #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT                       0x114
  49 /* Clock ID for INT6 I2S IBIT  */
  50 #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT                       0x115
  51
  52 /* Clock ID for QUINARY MI2S OSR CLK  */
  53 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR                         0x116
  54
  55 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK                        0x305
  56 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK                    0x306
  57
  58 #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK                         0x307
  59 #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK                      0x308
  60
  61 #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK                         0x30c
  62 #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK                     0x30d
  63
  64 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK                         0x30e
  65 #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK                     0x30f
  66
  67 /* Clock ID for MCLK for WSA2 core */
  68 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310
  69 /* Clock ID for NPL MCLK for WSA2 core */
  70 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311
  71 /* Clock ID for RX Core TX MCLK */
  72 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312
  73 /* Clock ID for RX CORE TX 2X MCLK */
  74 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313
  75 /* Clock ID for WSA core TX MCLK */
  76 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314
  77 /* Clock ID for WSA core TX 2X MCLK */
  78 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315
  79 /* Clock ID for WSA2 core TX MCLK */
  80 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316
  81 /* Clock ID for WSA2 core TX 2X MCLK */
  82 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317
  83 /* Clock ID for RX CORE MCLK2 2X  MCLK */
  84 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
  85
  86 #define Q6PRM_LPASS_CLK_SRC_INTERNAL    1
  87 #define Q6PRM_LPASS_CLK_ROOT_DEFAULT    0
  88 #define Q6PRM_HW_CORE_ID_LPASS          1
  89 #define Q6PRM_HW_CORE_ID_DCODEC         2
  90
  91 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
  92                           int clk_root, unsigned int freq);
  93 int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
  94                              const char *client_name, uint32_t *client_handle);
  95 int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
  96                                uint32_t client_handle);
  97 #endif /* __Q6PRM_H__ */