sound/soc/stm/stm32_sai.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
   4  *
   5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   6  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/module.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pinctrl/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <sound/dmaengine_pcm.h>
  18 #include <sound/core.h>
  19
  20 #include "stm32_sai.h"
  21
  22 static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai);
  23
  24 static const struct stm32_sai_conf stm32_sai_conf_f4 = {
  25         .version = STM_SAI_STM32F4,
  26         .fifo_size = 8,
  27         .has_spdif_pdm = false,
  28         .get_sai_ck_parent = stm32_sai_get_parent_clk,
  29 };
  30
  31 /*
  32  * Default settings for STM32H7x socs and STM32MP1x.
  33  * These default settings will be overridden if the soc provides
  34  * support of hardware configuration registers.
  35  * - STM32H7: rely on default settings
  36  * - STM32MP1: retrieve settings from registers
  37  */
  38 static const struct stm32_sai_conf stm32_sai_conf_h7 = {
  39         .version = STM_SAI_STM32H7,
  40         .fifo_size = 8,
  41         .has_spdif_pdm = true,
  42         .get_sai_ck_parent = stm32_sai_get_parent_clk,
  43 };
  44
  45 /*
  46  * STM32MP2x:
  47  * - do not use SAI parent clock source selection
  48  * - do not use DMA burst mode
  49  */
  50 static const struct stm32_sai_conf stm32_sai_conf_mp25 = {
  51         .no_dma_burst = true,
  52 };
  53
  54 static const struct of_device_id stm32_sai_ids[] = {
  55         { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
  56         { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
  57         { .compatible = "st,stm32mp25-sai", .data = (void *)&stm32_sai_conf_mp25 },
  58         {}
  59 };
  60
  61 static int stm32_sai_pclk_disable(struct device *dev)
  62 {
  63         struct stm32_sai_data *sai = dev_get_drvdata(dev);
  64
  65         clk_disable_unprepare(sai->pclk);
  66
  67         return 0;
  68 }
  69
  70 static int stm32_sai_pclk_enable(struct device *dev)
  71 {
  72         struct stm32_sai_data *sai = dev_get_drvdata(dev);
  73         int ret;
  74
  75         ret = clk_prepare_enable(sai->pclk);
  76         if (ret) {
  77                 dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
  78                 return ret;
  79         }
  80
  81         return 0;
  82 }
  83
  84 static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
  85 {
  86         int ret;
  87
  88         /* Enable peripheral clock to allow GCR register access */
  89         ret = stm32_sai_pclk_enable(&sai->pdev->dev);
  90         if (ret)
  91                 return ret;
  92
  93         writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
  94
  95         stm32_sai_pclk_disable(&sai->pdev->dev);
  96
  97         return 0;
  98 }
  99
 100 static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
 101 {
 102         u32 prev_synco;
 103         int ret;
 104
 105         /* Enable peripheral clock to allow GCR register access */
 106         ret = stm32_sai_pclk_enable(&sai->pdev->dev);
 107         if (ret)
 108                 return ret;
 109
 110         dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
 111                 sai->pdev->dev.of_node,
 112                 synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
 113
 114         prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
 115         if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
 116                 dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
 117                         sai->pdev->dev.of_node,
 118                         prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
 119                 stm32_sai_pclk_disable(&sai->pdev->dev);
 120                 return -EINVAL;
 121         }
 122
 123         writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
 124
 125         stm32_sai_pclk_disable(&sai->pdev->dev);
 126
 127         return 0;
 128 }
 129
 130 static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
 131                               struct device_node *np_provider,
 132                               int synco, int synci)
 133 {
 134         struct platform_device *pdev = of_find_device_by_node(np_provider);
 135         struct stm32_sai_data *sai_provider;
 136         int ret;
 137
 138         if (!pdev) {
 139                 dev_err(&sai_client->pdev->dev,
 140                         "Device not found for node %pOFn\n", np_provider);
 141                 of_node_put(np_provider);
 142                 return -ENODEV;
 143         }
 144
 145         sai_provider = platform_get_drvdata(pdev);
 146         if (!sai_provider) {
 147                 dev_err(&sai_client->pdev->dev,
 148                         "SAI sync provider data not found\n");
 149                 ret = -EINVAL;
 150                 goto error;
 151         }
 152
 153         /* Configure sync client */
 154         ret = stm32_sai_sync_conf_client(sai_client, synci);
 155         if (ret < 0)
 156                 goto error;
 157
 158         /* Configure sync provider */
 159         ret = stm32_sai_sync_conf_provider(sai_provider, synco);
 160
 161 error:
 162         put_device(&pdev->dev);
 163         of_node_put(np_provider);
 164         return ret;
 165 }
 166
 167 static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai)
 168 {
 169         struct device *dev = &sai->pdev->dev;
 170
 171         sai->clk_x8k = devm_clk_get(dev, "x8k");
 172         if (IS_ERR(sai->clk_x8k)) {
 173                 if (PTR_ERR(sai->clk_x8k) != -EPROBE_DEFER)
 174                         dev_err(dev, "missing x8k parent clock: %ld\n",
 175                                 PTR_ERR(sai->clk_x8k));
 176                 return PTR_ERR(sai->clk_x8k);
 177         }
 178
 179         sai->clk_x11k = devm_clk_get(dev, "x11k");
 180         if (IS_ERR(sai->clk_x11k)) {
 181                 if (PTR_ERR(sai->clk_x11k) != -EPROBE_DEFER)
 182                         dev_err(dev, "missing x11k parent clock: %ld\n",
 183                                 PTR_ERR(sai->clk_x11k));
 184                 return PTR_ERR(sai->clk_x11k);
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int stm32_sai_probe(struct platform_device *pdev)
 191 {
 192         struct stm32_sai_data *sai;
 193         const struct stm32_sai_conf *conf;
 194         struct reset_control *rst;
 195         u32 val;
 196         int ret;
 197
 198         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
 199         if (!sai)
 200                 return -ENOMEM;
 201
 202         sai->pdev = pdev;
 203
 204         sai->base = devm_platform_ioremap_resource(pdev, 0);
 205         if (IS_ERR(sai->base))
 206                 return PTR_ERR(sai->base);
 207
 208         conf = device_get_match_data(&pdev->dev);
 209         if (conf)
 210                 memcpy(&sai->conf, (const struct stm32_sai_conf *)conf,
 211                        sizeof(struct stm32_sai_conf));
 212         else
 213                 return -EINVAL;
 214
 215         if (!STM_SAI_IS_F4(sai)) {
 216                 sai->pclk = devm_clk_get(&pdev->dev, "pclk");
 217                 if (IS_ERR(sai->pclk))
 218                         return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
 219                                              "missing bus clock pclk\n");
 220         }
 221
 222         if (sai->conf.get_sai_ck_parent) {
 223                 ret = sai->conf.get_sai_ck_parent(sai);
 224                 if (ret)
 225                         return ret;
 226         }
 227
 228         /* init irqs */
 229         sai->irq = platform_get_irq(pdev, 0);
 230         if (sai->irq < 0)
 231                 return sai->irq;
 232
 233         /* reset */
 234         rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
 235         if (IS_ERR(rst))
 236                 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
 237                                      "Reset controller error\n");
 238
 239         reset_control_assert(rst);
 240         udelay(2);
 241         reset_control_deassert(rst);
 242
 243         /* Enable peripheral clock to allow register access */
 244         ret = clk_prepare_enable(sai->pclk);
 245         if (ret) {
 246                 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
 247                 return ret;
 248         }
 249
 250         val = FIELD_GET(SAI_IDR_ID_MASK,
 251                         readl_relaxed(sai->base + STM_SAI_IDR));
 252         if (val == SAI_IPIDR_NUMBER) {
 253                 val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
 254                 sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
 255                 sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
 256                                                       val);
 257
 258                 val = readl_relaxed(sai->base + STM_SAI_VERR);
 259                 sai->conf.version = val;
 260
 261                 dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
 262                         FIELD_GET(SAI_VERR_MAJ_MASK, val),
 263                         FIELD_GET(SAI_VERR_MIN_MASK, val));
 264         }
 265         clk_disable_unprepare(sai->pclk);
 266
 267         sai->set_sync = &stm32_sai_set_sync;
 268         platform_set_drvdata(pdev, sai);
 269
 270         return devm_of_platform_populate(&pdev->dev);
 271 }
 272
 273 #ifdef CONFIG_PM_SLEEP
 274 /*
 275  * When pins are shared by two sai sub instances, pins have to be defined
 276  * in sai parent node. In this case, pins state is not managed by alsa fw.
 277  * These pins are managed in suspend/resume callbacks.
 278  */
 279 static int stm32_sai_suspend(struct device *dev)
 280 {
 281         struct stm32_sai_data *sai = dev_get_drvdata(dev);
 282         int ret;
 283
 284         ret = stm32_sai_pclk_enable(dev);
 285         if (ret)
 286                 return ret;
 287
 288         sai->gcr = readl_relaxed(sai->base);
 289         stm32_sai_pclk_disable(dev);
 290
 291         return pinctrl_pm_select_sleep_state(dev);
 292 }
 293
 294 static int stm32_sai_resume(struct device *dev)
 295 {
 296         struct stm32_sai_data *sai = dev_get_drvdata(dev);
 297         int ret;
 298
 299         ret = stm32_sai_pclk_enable(dev);
 300         if (ret)
 301                 return ret;
 302
 303         writel_relaxed(sai->gcr, sai->base);
 304         stm32_sai_pclk_disable(dev);
 305
 306         return pinctrl_pm_select_default_state(dev);
 307 }
 308 #endif /* CONFIG_PM_SLEEP */
 309
 310 static const struct dev_pm_ops stm32_sai_pm_ops = {
 311         SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
 312 };
 313
 314 MODULE_DEVICE_TABLE(of, stm32_sai_ids);
 315
 316 static struct platform_driver stm32_sai_driver = {
 317         .driver = {
 318                 .name = "st,stm32-sai",
 319                 .of_match_table = stm32_sai_ids,
 320                 .pm = &stm32_sai_pm_ops,
 321         },
 322         .probe = stm32_sai_probe,
 323 };
 324
 325 module_platform_driver(stm32_sai_driver);
 326
 327 MODULE_DESCRIPTION("STM32 Soc SAI Interface");
 328 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
 329 MODULE_ALIAS("platform:st,stm32-sai");
 330 MODULE_LICENSE("GPL v2");