drm/panthor: Don't add write fences to the shared BOs
[drm/drm-misc.git] / arch / mips / include / asm / regdef.h
blob236051364f78e2e7586a3fc2097e0a55de2de36e
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1985 MIPS Computer Systems, Inc.
7 * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
8 * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2011 Wind River Systems,
10 * written by Ralf Baechle <ralf@linux-mips.org>
12 #ifndef _ASM_REGDEF_H
13 #define _ASM_REGDEF_H
15 #include <asm/sgidefs.h>
17 #if _MIPS_SIM == _MIPS_SIM_ABI32
20 * General purpose register numbers for 32 bit ABI
22 #define GPR_ZERO 0 /* wired zero */
23 #define GPR_AT 1 /* assembler temp */
24 #define GPR_V0 2 /* return value */
25 #define GPR_V1 3
26 #define GPR_A0 4 /* argument registers */
27 #define GPR_A1 5
28 #define GPR_A2 6
29 #define GPR_A3 7
30 #define GPR_T0 8 /* caller saved */
31 #define GPR_T1 9
32 #define GPR_T2 10
33 #define GPR_T3 11
34 #define GPR_T4 12
35 #define GPR_TA0 12
36 #define GPR_T5 13
37 #define GPR_TA1 13
38 #define GPR_T6 14
39 #define GPR_TA2 14
40 #define GPR_T7 15
41 #define GPR_TA3 15
42 #define GPR_S0 16 /* callee saved */
43 #define GPR_S1 17
44 #define GPR_S2 18
45 #define GPR_S3 19
46 #define GPR_S4 20
47 #define GPR_S5 21
48 #define GPR_S6 22
49 #define GPR_S7 23
50 #define GPR_T8 24 /* caller saved */
51 #define GPR_T9 25
52 #define GPR_JP 25 /* PIC jump register */
53 #define GPR_K0 26 /* kernel scratch */
54 #define GPR_K1 27
55 #define GPR_GP 28 /* global pointer */
56 #define GPR_SP 29 /* stack pointer */
57 #define GPR_FP 30 /* frame pointer */
58 #define GPR_S8 30 /* same like fp! */
59 #define GPR_RA 31 /* return address */
61 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
63 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
65 #define GPR_ZERO 0 /* wired zero */
66 #define GPR_AT 1 /* assembler temp */
67 #define GPR_V0 2 /* return value - caller saved */
68 #define GPR_V1 3
69 #define GPR_A0 4 /* argument registers */
70 #define GPR_A1 5
71 #define GPR_A2 6
72 #define GPR_A3 7
73 #define GPR_A4 8 /* arg reg 64 bit; caller saved in 32 bit */
74 #define GPR_TA0 8
75 #define GPR_A5 9
76 #define GPR_TA1 9
77 #define GPR_A6 10
78 #define GPR_TA2 10
79 #define GPR_A7 11
80 #define GPR_TA3 11
81 #define GPR_T0 12 /* caller saved */
82 #define GPR_T1 13
83 #define GPR_T2 14
84 #define GPR_T3 15
85 #define GPR_S0 16 /* callee saved */
86 #define GPR_S1 17
87 #define GPR_S2 18
88 #define GPR_S3 19
89 #define GPR_S4 20
90 #define GPR_S5 21
91 #define GPR_S6 22
92 #define GPR_S7 23
93 #define GPR_T8 24 /* caller saved */
94 #define GPR_T9 25 /* callee address for PIC/temp */
95 #define GPR_JP 25 /* PIC jump register */
96 #define GPR_K0 26 /* kernel temporary */
97 #define GPR_K1 27
98 #define GPR_GP 28 /* global pointer - caller saved for PIC */
99 #define GPR_SP 29 /* stack pointer */
100 #define GPR_FP 30 /* frame pointer */
101 #define GPR_S8 30 /* callee saved */
102 #define GPR_RA 31 /* return address */
104 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
106 #ifdef __ASSEMBLY__
107 #if _MIPS_SIM == _MIPS_SIM_ABI32
110 * Symbolic register names for 32 bit ABI
112 #define zero $0 /* wired zero */
113 #define AT $1 /* assembler temp - uppercase because of ".set at" */
114 #define v0 $2 /* return value */
115 #define v1 $3
116 #define a0 $4 /* argument registers */
117 #define a1 $5
118 #define a2 $6
119 #define a3 $7
120 #define t0 $8 /* caller saved */
121 #define t1 $9
122 #define t2 $10
123 #define t3 $11
124 #define t4 $12
125 #define ta0 $12
126 #define t5 $13
127 #define ta1 $13
128 #define t6 $14
129 #define ta2 $14
130 #define t7 $15
131 #define ta3 $15
132 #define s0 $16 /* callee saved */
133 #define s1 $17
134 #define s2 $18
135 #define s3 $19
136 #define s4 $20
137 #define s5 $21
138 #define s6 $22
139 #define s7 $23
140 #define t8 $24 /* caller saved */
141 #define t9 $25
142 #define jp $25 /* PIC jump register */
143 #define k0 $26 /* kernel scratch */
144 #define k1 $27
145 #define gp $28 /* global pointer */
146 #define sp $29 /* stack pointer */
147 #define fp $30 /* frame pointer */
148 #define s8 $30 /* same like fp! */
149 #define ra $31 /* return address */
151 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
153 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
155 #define zero $0 /* wired zero */
156 #define AT $at /* assembler temp - uppercase because of ".set at" */
157 #define v0 $2 /* return value - caller saved */
158 #define v1 $3
159 #define a0 $4 /* argument registers */
160 #define a1 $5
161 #define a2 $6
162 #define a3 $7
163 #define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
164 #define ta0 $8
165 #define a5 $9
166 #define ta1 $9
167 #define a6 $10
168 #define ta2 $10
169 #define a7 $11
170 #define ta3 $11
171 #define t0 $12 /* caller saved */
172 #define t1 $13
173 #define t2 $14
174 #define t3 $15
175 #define s0 $16 /* callee saved */
176 #define s1 $17
177 #define s2 $18
178 #define s3 $19
179 #define s4 $20
180 #define s5 $21
181 #define s6 $22
182 #define s7 $23
183 #define t8 $24 /* caller saved */
184 #define t9 $25 /* callee address for PIC/temp */
185 #define jp $25 /* PIC jump register */
186 #define k0 $26 /* kernel temporary */
187 #define k1 $27
188 #define gp $28 /* global pointer - caller saved for PIC */
189 #define sp $29 /* stack pointer */
190 #define fp $30 /* frame pointer */
191 #define s8 $30 /* callee saved */
192 #define ra $31 /* return address */
194 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
195 #endif /* __ASSEMBLY__ */
197 #endif /* _ASM_REGDEF_H */