arch/mips/include/asm/sgi/heart.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * HEART chip definitions
   4  *
   5  * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
   6  *               2009 Johannes Dickgreber <tanzy@gmx.de>
   7  *               2007-2015 Joshua Kinard <kumba@gentoo.org>
   8  */
   9 #ifndef __ASM_SGI_HEART_H
  10 #define __ASM_SGI_HEART_H
  11
  12 #include <linux/types.h>
  13 #include <linux/time.h>
  14
  15 /*
  16  * There are 8 DIMM slots on an IP30 system
  17  * board, which are grouped into four banks
  18  */
  19 #define HEART_MEMORY_BANKS      4
  20
  21 /* HEART can support up to four CPUs */
  22 #define HEART_MAX_CPUS          4
  23
  24 #define HEART_XKPHYS_BASE       ((void *)(IO_BASE | 0x000000000ff00000ULL))
  25
  26 /**
  27  * struct ip30_heart_regs - struct that maps IP30 HEART registers.
  28  * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
  29  * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
  30  * @mem_refresh: HEART_MEM_REF - purpose unknown.
  31  * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
  32  * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
  33  * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
  34  * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control.
  35  * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown.
  36  * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown.
  37  * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown.
  38  * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown.
  39  * @status: HEART_STATUS - HEART status information.
  40  * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS.
  41  * @bus_err_misc: HEART_BERR_MISC - purpose unknown.
  42  * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err.
  43  * @mem_err_data: HEART_MEMERR_DATA - purpose unknown.
  44  * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs.
  45  * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider.
  46  * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control.
  47  * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
  48  * @undefined: Undefined/diag register, write to it triggers PIUR_ACC_ERR.
  49  * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
  50  * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register.
  51  * @set_isr: HEART_SET_ISR - set interrupt status register.
  52  * @clear_isr: HEART_CLR_ISR - clear interrupt status register.
  53  * @isr: HEART_ISR - interrupt status register (read-only).
  54  * @imsr: HEART_IMSR - purpose unknown.
  55  * @cause: HEART_CAUSE - HEART cause information.
  56  * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
  57  * @count: HEART_COUNT - 52-bit counter.
  58  * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
  59  * @compare: HEART_COMPARE - 24-bit compare.
  60  * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
  61  * @trigger: HEART_TRIGGER - purpose unknown.
  62  * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
  63  * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART.
  64  * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
  65  * @sync: HEART_SYNC - purpose unknown.
  66  *
  67  * HEART is the main system controller ASIC for IP30 system.  It incorporates
  68  * a memory controller, interrupt status/cause/set/clear management, basic
  69  * timer with count/compare, and other functionality.  For Linux, not all of
  70  * HEART's functions are fully understood.
  71  *
  72  * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg
  73  * register only reports correct values if queried in 32bits.  Hence the need
  74  * for a union.  Even though mem_cfg.l has 8 array slots, we only ever query
  75  * up to 4 of those.  IP30 has 8 DIMM slots arranged into 4 banks, w/ 2 DIMMs
  76  * per bank.  Each 32bit read accesses one of these banks.  Perhaps HEART was
  77  * designed to address up to 8 banks (16 DIMMs)?  We may never know.
  78  */
  79 struct ip30_heart_regs {                /* 0x0ff00000 */
  80         u64 mode;                       /* +  0x00000 */
  81         /* Memory */
  82         u64 sdram_mode;                 /* +  0x00008 */
  83         u64 mem_refresh;                /* +  0x00010 */
  84         u64 mem_req_arb;                /* +  0x00018 */
  85         union {
  86                 u64 q[HEART_MEMORY_BANKS];      /* readq() */
  87                 u32 l[HEART_MEMORY_BANKS * 2];  /* readl() */
  88         } mem_cfg;                      /* +  0x00020 */
  89         /* Flow control (gfx?) */
  90         u64 fc_mode;                    /* +  0x00040 */
  91         u64 fc_timer_limit;             /* +  0x00048 */
  92         u64 fc_addr[2];                 /* +  0x00050 */
  93         u64 fc_credit_cnt[2];           /* +  0x00060 */
  94         u64 fc_timer[2];                /* +  0x00070 */
  95         /* Status */
  96         u64 status;                     /* +  0x00080 */
  97         /* Bus error */
  98         u64 bus_err_addr;               /* +  0x00088 */
  99         u64 bus_err_misc;               /* +  0x00090 */
 100         /* Memory error */
 101         u64 mem_err_addr;               /* +  0x00098 */
 102         u64 mem_err_data;               /* +  0x000a0 */
 103         /* Misc */
 104         u64 piur_acc_err;               /* +  0x000a8 */
 105         u64 mlan_clock_div;             /* +  0x000b0 */
 106         u64 mlan_ctrl;                  /* +  0x000b8 */
 107         u64 __pad0[0x01e8];             /* +  0x000c0 + 0x0f40 */
 108         /* Undefined */
 109         u64 undefined;                  /* +  0x01000 */
 110         u64 __pad1[0x1dff];             /* +  0x01008 + 0xeff8 */
 111         /* Interrupts */
 112         u64 imr[HEART_MAX_CPUS];        /* +  0x10000 */
 113         u64 set_isr;                    /* +  0x10020 */
 114         u64 clear_isr;                  /* +  0x10028 */
 115         u64 isr;                        /* +  0x10030 */
 116         u64 imsr;                       /* +  0x10038 */
 117         u64 cause;                      /* +  0x10040 */
 118         u64 __pad2[0x1ff7];             /* +  0x10048 + 0xffb8 */
 119         /* Timer */
 120         u64 count;                      /* +  0x20000 */
 121         u64 __pad3[0x1fff];             /* +  0x20008 + 0xfff8 */
 122         u64 compare;                    /* +  0x30000 */
 123         u64 __pad4[0x1fff];             /* +  0x30008 + 0xfff8 */
 124         u64 trigger;                    /* +  0x40000 */
 125         u64 __pad5[0x1fff];             /* +  0x40008 + 0xfff8 */
 126         /* Misc */
 127         u64 cpuid;                      /* +  0x50000 */
 128         u64 __pad6[0x1fff];             /* +  0x50008 + 0xfff8 */
 129         u64 sync;                       /* +  0x60000 */
 130 };
 131
 132
 133 /* For timer-related bits. */
 134 #define HEART_NS_PER_CYCLE      80
 135 #define HEART_CYCLES_PER_SEC    (NSEC_PER_SEC / HEART_NS_PER_CYCLE)
 136
 137
 138 /*
 139  * XXX: Everything below this comment will either go away or be cleaned
 140  *      up to fit in better with Linux.  A lot of the bit definitions for
 141  *      HEART were derived from IRIX's sys/RACER/heart.h header file.
 142  */
 143
 144 /* HEART Masks */
 145 #define HEART_ATK_MASK          0x0007ffffffffffff      /* HEART attack mask */
 146 #define HEART_ACK_ALL_MASK      0xffffffffffffffff      /* Ack everything */
 147 #define HEART_CLR_ALL_MASK      0x0000000000000000      /* Clear all */
 148 #define HEART_BR_ERR_MASK       0x7ff8000000000000      /* BRIDGE error mask */
 149 #define HEART_CPU0_ERR_MASK     0x8ff8000000000000      /* CPU0 error mask */
 150 #define HEART_CPU1_ERR_MASK     0x97f8000000000000      /* CPU1 error mask */
 151 #define HEART_CPU2_ERR_MASK     0xa7f8000000000000      /* CPU2 error mask */
 152 #define HEART_CPU3_ERR_MASK     0xc7f8000000000000      /* CPU3 error mask */
 153 #define HEART_ERR_MASK          0x1ff                   /* HEART error mask */
 154 #define HEART_ERR_MASK_START    51                      /* HEART error start */
 155 #define HEART_ERR_MASK_END      63                      /* HEART error end */
 156
 157 /* Bits in the HEART_MODE register. */
 158 #define HM_PROC_DISABLE_SHFT            60
 159 #define HM_PROC_DISABLE_MSK             (0xfUL << HM_PROC_DISABLE_SHFT)
 160 #define HM_PROC_DISABLE(x)              (0x1UL << (x) + HM_PROC_DISABLE_SHFT)
 161 #define HM_MAX_PSR                      (0x7UL << 57)
 162 #define HM_MAX_IOSR                     (0x7UL << 54)
 163 #define HM_MAX_PEND_IOSR                (0x7UL << 51)
 164 #define HM_TRIG_SRC_SEL_MSK             (0x7UL << 48)
 165 #define HM_TRIG_HEART_EXC               (0x0UL << 48)
 166 #define HM_TRIG_REG_BIT                 (0x1UL << 48)
 167 #define HM_TRIG_SYSCLK                  (0x2UL << 48)
 168 #define HM_TRIG_MEMCLK_2X               (0x3UL << 48)
 169 #define HM_TRIG_MEMCLK                  (0x4UL << 48)
 170 #define HM_TRIG_IOCLK                   (0x5UL << 48)
 171 #define HM_PIU_TEST_MODE                (0xfUL << 40)
 172 #define HM_GP_FLAG_MSK                  (0xfUL << 36)
 173 #define HM_GP_FLAG(x)                   BIT((x) + 36)
 174 #define HM_MAX_PROC_HYST                (0xfUL << 32)
 175 #define HM_LLP_WRST_AFTER_RST           BIT(28)
 176 #define HM_LLP_LINK_RST                 BIT(27)
 177 #define HM_LLP_WARM_RST                 BIT(26)
 178 #define HM_COR_ECC_LCK                  BIT(25)
 179 #define HM_REDUCED_PWR                  BIT(24)
 180 #define HM_COLD_RST                     BIT(23)
 181 #define HM_SW_RST                       BIT(22)
 182 #define HM_MEM_FORCE_WR                 BIT(21)
 183 #define HM_DB_ERR_GEN                   BIT(20)
 184 #define HM_SB_ERR_GEN                   BIT(19)
 185 #define HM_CACHED_PIO_EN                BIT(18)
 186 #define HM_CACHED_PROM_EN               BIT(17)
 187 #define HM_PE_SYS_COR_ERE               BIT(16)
 188 #define HM_GLOBAL_ECC_EN                BIT(15)
 189 #define HM_IO_COH_EN                    BIT(14)
 190 #define HM_INT_EN                       BIT(13)
 191 #define HM_DATA_CHK_EN                  BIT(12)
 192 #define HM_REF_EN                       BIT(11)
 193 #define HM_BAD_SYSWR_ERE                BIT(10)
 194 #define HM_BAD_SYSRD_ERE                BIT(9)
 195 #define HM_SYSSTATE_ERE                 BIT(8)
 196 #define HM_SYSCMD_ERE                   BIT(7)
 197 #define HM_NCOR_SYS_ERE                 BIT(6)
 198 #define HM_COR_SYS_ERE                  BIT(5)
 199 #define HM_DATA_ELMNT_ERE               BIT(4)
 200 #define HM_MEM_ADDR_PROC_ERE            BIT(3)
 201 #define HM_MEM_ADDR_IO_ERE              BIT(2)
 202 #define HM_NCOR_MEM_ERE                 BIT(1)
 203 #define HM_COR_MEM_ERE                  BIT(0)
 204
 205 /* Bits in the HEART_MEM_REF register. */
 206 #define HEART_MEMREF_REFS(x)            ((0xfUL & (x)) << 16)
 207 #define HEART_MEMREF_PERIOD(x)          ((0xffffUL & (x)))
 208 #define HEART_MEMREF_REFS_VAL           HEART_MEMREF_REFS(8)
 209 #define HEART_MEMREF_PERIOD_VAL         HEART_MEMREF_PERIOD(0x4000)
 210 #define HEART_MEMREF_VAL                (HEART_MEMREF_REFS_VAL | \
 211                                          HEART_MEMREF_PERIOD_VAL)
 212
 213 /* Bits in the HEART_MEM_REQ_ARB register. */
 214 #define HEART_MEMARB_IODIS              (1  << 20)
 215 #define HEART_MEMARB_MAXPMWRQS          (15 << 16)
 216 #define HEART_MEMARB_MAXPMRRQS          (15 << 12)
 217 #define HEART_MEMARB_MAXPMRQS           (15 << 8)
 218 #define HEART_MEMARB_MAXRRRQS           (15 << 4)
 219 #define HEART_MEMARB_MAXGBRRQS          (15)
 220
 221 /* Bits in the HEART_MEMCFG<x> registers. */
 222 #define HEART_MEMCFG_VALID              0x80000000      /* Bank is valid */
 223 #define HEART_MEMCFG_DENSITY            0x01c00000      /* Mem density */
 224 #define HEART_MEMCFG_SIZE_MASK          0x003f0000      /* Mem size mask */
 225 #define HEART_MEMCFG_ADDR_MASK          0x000001ff      /* Base addr mask */
 226 #define HEART_MEMCFG_SIZE_SHIFT         16              /* Mem size shift */
 227 #define HEART_MEMCFG_DENSITY_SHIFT      22              /* Density Shift */
 228 #define HEART_MEMCFG_UNIT_SHIFT         25              /* Unit Shift, 32MB */
 229
 230 /* Bits in the HEART_STATUS register */
 231 #define HEART_STAT_HSTL_SDRV            BIT(14)
 232 #define HEART_STAT_FC_CR_OUT(x)         BIT((x) + 12)
 233 #define HEART_STAT_DIR_CNNCT            BIT(11)
 234 #define HEART_STAT_TRITON               BIT(10)
 235 #define HEART_STAT_R4K                  BIT(9)
 236 #define HEART_STAT_BIG_ENDIAN           BIT(8)
 237 #define HEART_STAT_PROC_SHFT            4
 238 #define HEART_STAT_PROC_MSK             (0xfUL << HEART_STAT_PROC_SHFT)
 239 #define HEART_STAT_PROC_ACTIVE(x)       (0x1UL << ((x) + HEART_STAT_PROC_SHFT))
 240 #define HEART_STAT_WIDGET_ID            0xf
 241
 242 /* Bits in the HEART_CAUSE register */
 243 #define HC_PE_SYS_COR_ERR_MSK           (0xfUL << 60)
 244 #define HC_PE_SYS_COR_ERR(x)            BIT((x) + 60)
 245 #define HC_PIOWDB_OFLOW                 BIT(44)
 246 #define HC_PIORWRB_OFLOW                BIT(43)
 247 #define HC_PIUR_ACC_ERR                 BIT(42)
 248 #define HC_BAD_SYSWR_ERR                BIT(41)
 249 #define HC_BAD_SYSRD_ERR                BIT(40)
 250 #define HC_SYSSTATE_ERR_MSK             (0xfUL << 36)
 251 #define HC_SYSSTATE_ERR(x)              BIT((x) + 36)
 252 #define HC_SYSCMD_ERR_MSK               (0xfUL << 32)
 253 #define HC_SYSCMD_ERR(x)                BIT((x) + 32)
 254 #define HC_NCOR_SYSAD_ERR_MSK           (0xfUL << 28)
 255 #define HC_NCOR_SYSAD_ERR(x)            BIT((x) + 28)
 256 #define HC_COR_SYSAD_ERR_MSK            (0xfUL << 24)
 257 #define HC_COR_SYSAD_ERR(x)             BIT((x) + 24)
 258 #define HC_DATA_ELMNT_ERR_MSK           (0xfUL << 20)
 259 #define HC_DATA_ELMNT_ERR(x)            BIT((x) + 20)
 260 #define HC_WIDGET_ERR                   BIT(16)
 261 #define HC_MEM_ADDR_ERR_PROC_MSK        (0xfUL << 4)
 262 #define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4)
 263 #define HC_MEM_ADDR_ERR_IO              BIT(2)
 264 #define HC_NCOR_MEM_ERR                 BIT(1)
 265 #define HC_COR_MEM_ERR                  BIT(0)
 266
 267 /*
 268  * HEART has 64 interrupt vectors available to it, subdivided into five
 269  * priority levels.  They are numbered 0 to 63.
 270  */
 271 #define HEART_NUM_IRQS                  64
 272
 273 /*
 274  * These are the five interrupt priority levels and their corresponding
 275  * CPU IPx interrupt pins.
 276  *
 277  * Level 4 - Error Interrupts.
 278  * Level 3 - HEART timer interrupt.
 279  * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
 280  * Level 1 - General device interrupts.
 281  * Level 0 - General device GFX flow control interrupts.
 282  */
 283 #define HEART_L4_INT_MASK               0xfff8000000000000ULL   /* IP6 */
 284 #define HEART_L3_INT_MASK               0x0004000000000000ULL   /* IP5 */
 285 #define HEART_L2_INT_MASK               0x0003ffff00000000ULL   /* IP4 */
 286 #define HEART_L1_INT_MASK               0x00000000ffff0000ULL   /* IP3 */
 287 #define HEART_L0_INT_MASK               0x000000000000ffffULL   /* IP2 */
 288
 289 /* HEART L0 Interrupts (Low Priority) */
 290 #define HEART_L0_INT_GENERIC             0
 291 #define HEART_L0_INT_FLOW_CTRL_HWTR_0    1
 292 #define HEART_L0_INT_FLOW_CTRL_HWTR_1    2
 293
 294 /* HEART L2 Interrupts (High Priority) */
 295 #define HEART_L2_INT_RESCHED_CPU_0      46
 296 #define HEART_L2_INT_RESCHED_CPU_1      47
 297 #define HEART_L2_INT_CALL_CPU_0         48
 298 #define HEART_L2_INT_CALL_CPU_1         49
 299
 300 /* HEART L3 Interrupts (Compare/Counter Timer) */
 301 #define HEART_L3_INT_TIMER              50
 302
 303 /* HEART L4 Interrupts (Errors) */
 304 #define HEART_L4_INT_XWID_ERR_9         51
 305 #define HEART_L4_INT_XWID_ERR_A         52
 306 #define HEART_L4_INT_XWID_ERR_B         53
 307 #define HEART_L4_INT_XWID_ERR_C         54
 308 #define HEART_L4_INT_XWID_ERR_D         55
 309 #define HEART_L4_INT_XWID_ERR_E         56
 310 #define HEART_L4_INT_XWID_ERR_F         57
 311 #define HEART_L4_INT_XWID_ERR_XBOW      58
 312 #define HEART_L4_INT_CPU_BUS_ERR_0      59
 313 #define HEART_L4_INT_CPU_BUS_ERR_1      60
 314 #define HEART_L4_INT_CPU_BUS_ERR_2      61
 315 #define HEART_L4_INT_CPU_BUS_ERR_3      62
 316 #define HEART_L4_INT_HEART_EXCP         63
 317
 318 extern struct ip30_heart_regs __iomem *heart_regs;
 319
 320 #define heart_read      ____raw_readq
 321 #define heart_write     ____raw_writeq
 322
 323 #endif /* __ASM_SGI_HEART_H */