arch/mips/include/uapi/asm/inst.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Format of an instruction in memory.
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (C) 1996, 2000 by Ralf Baechle
  10  * Copyright (C) 2006 by Thiemo Seufer
  11  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  12  * Copyright (C) 2014 Imagination Technologies Ltd.
  13  */
  14 #ifndef _UAPI_ASM_INST_H
  15 #define _UAPI_ASM_INST_H
  16
  17 #include <asm/bitfield.h>
  18
  19 /*
  20  * Major opcodes; before MIPS IV cop1x was called cop3.
  21  */
  22 enum major_op {
  23         spec_op, bcond_op, j_op, jal_op,
  24         beq_op, bne_op, blez_op, bgtz_op,
  25         addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
  26         andi_op, ori_op, xori_op, lui_op,
  27         cop0_op, cop1_op, cop2_op, cop1x_op,
  28         beql_op, bnel_op, blezl_op, bgtzl_op,
  29         daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
  30         spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
  31         lb_op, lh_op, lwl_op, lw_op,
  32         lbu_op, lhu_op, lwr_op, lwu_op,
  33         sb_op, sh_op, swl_op, sw_op,
  34         sdl_op, sdr_op, swr_op, cache_op,
  35         ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
  36         lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
  37         sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
  38         scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
  39 };
  40
  41 /*
  42  * func field of spec opcode.
  43  */
  44 enum spec_op {
  45         sll_op, movc_op, srl_op, sra_op,
  46         sllv_op, pmon_op, srlv_op, srav_op,
  47         jr_op, jalr_op, movz_op, movn_op,
  48         syscall_op, break_op, spim_op, sync_op,
  49         mfhi_op, mthi_op, mflo_op, mtlo_op,
  50         dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  51         mult_op, multu_op, div_op, divu_op,
  52         dmult_op, dmultu_op, ddiv_op, ddivu_op,
  53         add_op, addu_op, sub_op, subu_op,
  54         and_op, or_op, xor_op, nor_op,
  55         spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  56         dadd_op, daddu_op, dsub_op, dsubu_op,
  57         tge_op, tgeu_op, tlt_op, tltu_op,
  58         teq_op, seleqz_op, tne_op, selnez_op,
  59         dsll_op, spec5_unused_op, dsrl_op, dsra_op,
  60         dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op
  61 };
  62
  63 /*
  64  * func field of spec2 opcode.
  65  */
  66 enum spec2_op {
  67         madd_op, maddu_op, mul_op, spec2_3_unused_op,
  68         msub_op, msubu_op, /* more unused ops */
  69         clz_op = 0x20, clo_op,
  70         dclz_op = 0x24, dclo_op,
  71         sdbpp_op = 0x3f
  72 };
  73
  74 /*
  75  * func field of spec3 opcode.
  76  */
  77 enum spec3_op {
  78         ext_op, dextm_op, dextu_op, dext_op,
  79         ins_op, dinsm_op, dinsu_op, dins_op,
  80         yield_op  = 0x09, lx_op     = 0x0a,
  81         lwle_op   = 0x19, lwre_op   = 0x1a,
  82         cachee_op = 0x1b, sbe_op    = 0x1c,
  83         she_op    = 0x1d, sce_op    = 0x1e,
  84         swe_op    = 0x1f, bshfl_op  = 0x20,
  85         swle_op   = 0x21, swre_op   = 0x22,
  86         prefe_op  = 0x23, dbshfl_op = 0x24,
  87         cache6_op = 0x25, sc6_op    = 0x26,
  88         scd6_op   = 0x27, lbue_op   = 0x28,
  89         lhue_op   = 0x29, lbe_op    = 0x2c,
  90         lhe_op    = 0x2d, lle_op    = 0x2e,
  91         lwe_op    = 0x2f, pref6_op  = 0x35,
  92         ll6_op    = 0x36, lld6_op   = 0x37,
  93         rdhwr_op  = 0x3b
  94 };
  95
  96 /*
  97  * Bits 10-6 minor opcode for r6 spec mult/div encodings
  98  */
  99 enum mult_op {
 100         mult_mult_op = 0x0,
 101         mult_mul_op = 0x2,
 102         mult_muh_op = 0x3,
 103 };
 104 enum multu_op {
 105         multu_multu_op = 0x0,
 106         multu_mulu_op = 0x2,
 107         multu_muhu_op = 0x3,
 108 };
 109 enum div_op {
 110         div_div_op = 0x0,
 111         div_div6_op = 0x2,
 112         div_mod_op = 0x3,
 113 };
 114 enum divu_op {
 115         divu_divu_op = 0x0,
 116         divu_divu6_op = 0x2,
 117         divu_modu_op = 0x3,
 118 };
 119 enum dmult_op {
 120         dmult_dmult_op = 0x0,
 121         dmult_dmul_op = 0x2,
 122         dmult_dmuh_op = 0x3,
 123 };
 124 enum dmultu_op {
 125         dmultu_dmultu_op = 0x0,
 126         dmultu_dmulu_op = 0x2,
 127         dmultu_dmuhu_op = 0x3,
 128 };
 129 enum ddiv_op {
 130         ddiv_ddiv_op = 0x0,
 131         ddiv_ddiv6_op = 0x2,
 132         ddiv_dmod_op = 0x3,
 133 };
 134 enum ddivu_op {
 135         ddivu_ddivu_op = 0x0,
 136         ddivu_ddivu6_op = 0x2,
 137         ddivu_dmodu_op = 0x3,
 138 };
 139
 140 /*
 141  * rt field of bcond opcodes.
 142  */
 143 enum rt_op {
 144         bltz_op, bgez_op, bltzl_op, bgezl_op,
 145         spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
 146         tgei_op, tgeiu_op, tlti_op, tltiu_op,
 147         teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
 148         bltzal_op, bgezal_op, bltzall_op, bgezall_op,
 149         rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
 150         rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
 151         bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
 152 };
 153
 154 /*
 155  * rs field of cop opcodes.
 156  */
 157 enum cop_op {
 158         mfc_op        = 0x00, dmfc_op       = 0x01,
 159         cfc_op        = 0x02, mfhc0_op      = 0x02,
 160         mfhc_op       = 0x03, mtc_op        = 0x04,
 161         dmtc_op       = 0x05, ctc_op        = 0x06,
 162         mthc0_op      = 0x06, mthc_op       = 0x07,
 163         bc_op         = 0x08, bc1eqz_op     = 0x09,
 164         mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
 165         wrpgpr_op     = 0x0e, cop_op        = 0x10,
 166         copm_op       = 0x18
 167 };
 168
 169 /*
 170  * rt field of cop.bc_op opcodes
 171  */
 172 enum bcop_op {
 173         bcf_op, bct_op, bcfl_op, bctl_op
 174 };
 175
 176 /*
 177  * func field of cop0 coi opcodes.
 178  */
 179 enum cop0_coi_func {
 180         tlbr_op       = 0x01, tlbwi_op      = 0x02,
 181         tlbwr_op      = 0x06, tlbp_op       = 0x08,
 182         rfe_op        = 0x10, eret_op       = 0x18,
 183         wait_op       = 0x20, hypcall_op    = 0x28
 184 };
 185
 186 /*
 187  * func field of cop0 com opcodes.
 188  */
 189 enum cop0_com_func {
 190         tlbr1_op      = 0x01, tlbw_op       = 0x02,
 191         tlbp1_op      = 0x08, dctr_op       = 0x09,
 192         dctw_op       = 0x0a
 193 };
 194
 195 /*
 196  * fmt field of cop1 opcodes.
 197  */
 198 enum cop1_fmt {
 199         s_fmt, d_fmt, e_fmt, q_fmt,
 200         w_fmt, l_fmt
 201 };
 202
 203 /*
 204  * func field of cop1 instructions using d, s or w format.
 205  */
 206 enum cop1_sdw_func {
 207         fadd_op      =  0x00, fsub_op      =  0x01,
 208         fmul_op      =  0x02, fdiv_op      =  0x03,
 209         fsqrt_op     =  0x04, fabs_op      =  0x05,
 210         fmov_op      =  0x06, fneg_op      =  0x07,
 211         froundl_op   =  0x08, ftruncl_op   =  0x09,
 212         fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 213         fround_op    =  0x0c, ftrunc_op    =  0x0d,
 214         fceil_op     =  0x0e, ffloor_op    =  0x0f,
 215         fsel_op      =  0x10,
 216         fmovc_op     =  0x11, fmovz_op     =  0x12,
 217         fmovn_op     =  0x13, fseleqz_op   =  0x14,
 218         frecip_op    =  0x15, frsqrt_op    =  0x16,
 219         fselnez_op   =  0x17, fmaddf_op    =  0x18,
 220         fmsubf_op    =  0x19, frint_op     =  0x1a,
 221         fclass_op    =  0x1b, fmin_op      =  0x1c,
 222         fmina_op     =  0x1d, fmax_op      =  0x1e,
 223         fmaxa_op     =  0x1f, fcvts_op     =  0x20,
 224         fcvtd_op     =  0x21, fcvte_op     =  0x22,
 225         fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 226         fcmp_op      =  0x30
 227 };
 228
 229 /*
 230  * func field of cop1x opcodes (MIPS IV).
 231  */
 232 enum cop1x_func {
 233         lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 234         swxc1_op     =  0x08, sdxc1_op     =  0x09,
 235         pfetch_op    =  0x0f, madd_s_op    =  0x20,
 236         madd_d_op    =  0x21, madd_e_op    =  0x22,
 237         msub_s_op    =  0x28, msub_d_op    =  0x29,
 238         msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 239         nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 240         nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 241         nmsub_e_op   =  0x3a
 242 };
 243
 244 /*
 245  * func field for mad opcodes (MIPS IV).
 246  */
 247 enum mad_func {
 248         madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 249         nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 250 };
 251
 252 /*
 253  * func field for page table walker (Loongson-3).
 254  */
 255 enum ptw_func {
 256         lwdir_op = 0x00,
 257         lwpte_op = 0x01,
 258         lddir_op = 0x02,
 259         ldpte_op = 0x03,
 260 };
 261
 262 /*
 263  * func field for special3 lx opcodes (Cavium Octeon).
 264  */
 265 enum lx_func {
 266         lwx_op  = 0x00,
 267         lhx_op  = 0x04,
 268         lbux_op = 0x06,
 269         ldx_op  = 0x08,
 270         lwux_op = 0x10,
 271         lhux_op = 0x14,
 272         lbx_op  = 0x16,
 273 };
 274
 275 /*
 276  * func field for special2 MXU opcodes (Ingenic XBurst MXU).
 277  */
 278 enum mxu_func {
 279         /* TODO, other MXU funcs */
 280         mxu_lx_op = 0x28,
 281 };
 282
 283 /*
 284  * op field for special2 MXU LX opcodes (Ingenic XBurst MXU).
 285  */
 286 enum lx_ingenic_func {
 287         mxu_lxb_op,
 288         mxu_lxh_op,
 289         /* reserved */
 290         mxu_lxw_op = 3,
 291         mxu_lxbu_op,
 292         mxu_lxhu_op,
 293         /* more reserved */
 294 };
 295
 296 /*
 297  * BSHFL opcodes
 298  */
 299 enum bshfl_func {
 300         wsbh_op = 0x2,
 301         seb_op  = 0x10,
 302         seh_op  = 0x18,
 303 };
 304
 305 /*
 306  * DBSHFL opcodes
 307  */
 308 enum dbshfl_func {
 309         dsbh_op = 0x2,
 310         dshd_op = 0x5,
 311 };
 312
 313 /*
 314  * MSA minor opcodes.
 315  */
 316 enum msa_func {
 317         msa_elm_op = 0x19,
 318 };
 319
 320 /*
 321  * MSA ELM opcodes.
 322  */
 323 enum msa_elm {
 324         msa_ctc_op = 0x3e,
 325         msa_cfc_op = 0x7e,
 326 };
 327
 328 /*
 329  * func field for MSA MI10 format.
 330  */
 331 enum msa_mi10_func {
 332         msa_ld_op = 8,
 333         msa_st_op = 9,
 334 };
 335
 336 /*
 337  * MSA 2 bit format fields.
 338  */
 339 enum msa_2b_fmt {
 340         msa_fmt_b = 0,
 341         msa_fmt_h = 1,
 342         msa_fmt_w = 2,
 343         msa_fmt_d = 3,
 344 };
 345
 346 /*
 347  * (microMIPS) Major opcodes.
 348  */
 349 enum mm_major_op {
 350         mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 351         mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 352         mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 353         mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 354         mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 355         mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
 356         mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 357         mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 358         mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 359         mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 360         mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 361         mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 362         mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 363         mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 364         mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 365         mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 366 };
 367
 368 /*
 369  * (microMIPS) POOL32I minor opcodes.
 370  */
 371 enum mm_32i_minor_op {
 372         mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 373         mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 374         mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 375         mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 376         mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 377         mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 378         mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 379         mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 380         mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 381 };
 382
 383 /*
 384  * (microMIPS) POOL32A minor opcodes.
 385  */
 386 enum mm_32a_minor_op {
 387         mm_sll32_op = 0x000,
 388         mm_ins_op = 0x00c,
 389         mm_sllv32_op = 0x010,
 390         mm_ext_op = 0x02c,
 391         mm_pool32axf_op = 0x03c,
 392         mm_srl32_op = 0x040,
 393         mm_srlv32_op = 0x050,
 394         mm_sra_op = 0x080,
 395         mm_srav_op = 0x090,
 396         mm_rotr_op = 0x0c0,
 397         mm_lwxs_op = 0x118,
 398         mm_addu32_op = 0x150,
 399         mm_subu32_op = 0x1d0,
 400         mm_wsbh_op = 0x1ec,
 401         mm_mul_op = 0x210,
 402         mm_and_op = 0x250,
 403         mm_or32_op = 0x290,
 404         mm_xor32_op = 0x310,
 405         mm_slt_op = 0x350,
 406         mm_sltu_op = 0x390,
 407 };
 408
 409 /*
 410  * (microMIPS) POOL32B functions.
 411  */
 412 enum mm_32b_func {
 413         mm_lwc2_func = 0x0,
 414         mm_lwp_func = 0x1,
 415         mm_ldc2_func = 0x2,
 416         mm_ldp_func = 0x4,
 417         mm_lwm32_func = 0x5,
 418         mm_cache_func = 0x6,
 419         mm_ldm_func = 0x7,
 420         mm_swc2_func = 0x8,
 421         mm_swp_func = 0x9,
 422         mm_sdc2_func = 0xa,
 423         mm_sdp_func = 0xc,
 424         mm_swm32_func = 0xd,
 425         mm_sdm_func = 0xf,
 426 };
 427
 428 /*
 429  * (microMIPS) POOL32C functions.
 430  */
 431 enum mm_32c_func {
 432         mm_pref_func = 0x2,
 433         mm_ll_func = 0x3,
 434         mm_swr_func = 0x9,
 435         mm_sc_func = 0xb,
 436         mm_lwu_func = 0xe,
 437 };
 438
 439 /*
 440  * (microMIPS) POOL32AXF minor opcodes.
 441  */
 442 enum mm_32axf_minor_op {
 443         mm_mfc0_op = 0x003,
 444         mm_mtc0_op = 0x00b,
 445         mm_tlbp_op = 0x00d,
 446         mm_mfhi32_op = 0x035,
 447         mm_jalr_op = 0x03c,
 448         mm_tlbr_op = 0x04d,
 449         mm_mflo32_op = 0x075,
 450         mm_jalrhb_op = 0x07c,
 451         mm_tlbwi_op = 0x08d,
 452         mm_mthi32_op = 0x0b5,
 453         mm_tlbwr_op = 0x0cd,
 454         mm_mtlo32_op = 0x0f5,
 455         mm_di_op = 0x11d,
 456         mm_jalrs_op = 0x13c,
 457         mm_jalrshb_op = 0x17c,
 458         mm_sync_op = 0x1ad,
 459         mm_syscall_op = 0x22d,
 460         mm_wait_op = 0x24d,
 461         mm_eret_op = 0x3cd,
 462         mm_divu_op = 0x5dc,
 463 };
 464
 465 /*
 466  * (microMIPS) POOL32F minor opcodes.
 467  */
 468 enum mm_32f_minor_op {
 469         mm_32f_00_op = 0x00,
 470         mm_32f_01_op = 0x01,
 471         mm_32f_02_op = 0x02,
 472         mm_32f_10_op = 0x08,
 473         mm_32f_11_op = 0x09,
 474         mm_32f_12_op = 0x0a,
 475         mm_32f_20_op = 0x10,
 476         mm_32f_30_op = 0x18,
 477         mm_32f_40_op = 0x20,
 478         mm_32f_41_op = 0x21,
 479         mm_32f_42_op = 0x22,
 480         mm_32f_50_op = 0x28,
 481         mm_32f_51_op = 0x29,
 482         mm_32f_52_op = 0x2a,
 483         mm_32f_60_op = 0x30,
 484         mm_32f_70_op = 0x38,
 485         mm_32f_73_op = 0x3b,
 486         mm_32f_74_op = 0x3c,
 487 };
 488
 489 /*
 490  * (microMIPS) POOL32F secondary minor opcodes.
 491  */
 492 enum mm_32f_10_minor_op {
 493         mm_lwxc1_op = 0x1,
 494         mm_swxc1_op,
 495         mm_ldxc1_op,
 496         mm_sdxc1_op,
 497         mm_luxc1_op,
 498         mm_suxc1_op,
 499 };
 500
 501 enum mm_32f_func {
 502         mm_lwxc1_func = 0x048,
 503         mm_swxc1_func = 0x088,
 504         mm_ldxc1_func = 0x0c8,
 505         mm_sdxc1_func = 0x108,
 506 };
 507
 508 /*
 509  * (microMIPS) POOL32F secondary minor opcodes.
 510  */
 511 enum mm_32f_40_minor_op {
 512         mm_fmovf_op,
 513         mm_fmovt_op,
 514 };
 515
 516 /*
 517  * (microMIPS) POOL32F secondary minor opcodes.
 518  */
 519 enum mm_32f_60_minor_op {
 520         mm_fadd_op,
 521         mm_fsub_op,
 522         mm_fmul_op,
 523         mm_fdiv_op,
 524 };
 525
 526 /*
 527  * (microMIPS) POOL32F secondary minor opcodes.
 528  */
 529 enum mm_32f_70_minor_op {
 530         mm_fmovn_op,
 531         mm_fmovz_op,
 532 };
 533
 534 /*
 535  * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 536  */
 537 enum mm_32f_73_minor_op {
 538         mm_fmov0_op = 0x01,
 539         mm_fcvtl_op = 0x04,
 540         mm_movf0_op = 0x05,
 541         mm_frsqrt_op = 0x08,
 542         mm_ffloorl_op = 0x0c,
 543         mm_fabs0_op = 0x0d,
 544         mm_fcvtw_op = 0x24,
 545         mm_movt0_op = 0x25,
 546         mm_fsqrt_op = 0x28,
 547         mm_ffloorw_op = 0x2c,
 548         mm_fneg0_op = 0x2d,
 549         mm_cfc1_op = 0x40,
 550         mm_frecip_op = 0x48,
 551         mm_fceill_op = 0x4c,
 552         mm_fcvtd0_op = 0x4d,
 553         mm_ctc1_op = 0x60,
 554         mm_fceilw_op = 0x6c,
 555         mm_fcvts0_op = 0x6d,
 556         mm_mfc1_op = 0x80,
 557         mm_fmov1_op = 0x81,
 558         mm_movf1_op = 0x85,
 559         mm_ftruncl_op = 0x8c,
 560         mm_fabs1_op = 0x8d,
 561         mm_mtc1_op = 0xa0,
 562         mm_movt1_op = 0xa5,
 563         mm_ftruncw_op = 0xac,
 564         mm_fneg1_op = 0xad,
 565         mm_mfhc1_op = 0xc0,
 566         mm_froundl_op = 0xcc,
 567         mm_fcvtd1_op = 0xcd,
 568         mm_mthc1_op = 0xe0,
 569         mm_froundw_op = 0xec,
 570         mm_fcvts1_op = 0xed,
 571 };
 572
 573 /*
 574  * (microMIPS) POOL32S minor opcodes.
 575  */
 576 enum mm_32s_minor_op {
 577         mm_32s_elm_op = 0x16,
 578 };
 579
 580 /*
 581  * (microMIPS) POOL16C minor opcodes.
 582  */
 583 enum mm_16c_minor_op {
 584         mm_lwm16_op = 0x04,
 585         mm_swm16_op = 0x05,
 586         mm_jr16_op = 0x0c,
 587         mm_jrc_op = 0x0d,
 588         mm_jalr16_op = 0x0e,
 589         mm_jalrs16_op = 0x0f,
 590         mm_jraddiusp_op = 0x18,
 591 };
 592
 593 /*
 594  * (microMIPS) POOL16D minor opcodes.
 595  */
 596 enum mm_16d_minor_op {
 597         mm_addius5_func,
 598         mm_addiusp_func,
 599 };
 600
 601 /*
 602  * (MIPS16e) opcodes.
 603  */
 604 enum MIPS16e_ops {
 605         MIPS16e_jal_op = 003,
 606         MIPS16e_ld_op = 007,
 607         MIPS16e_i8_op = 014,
 608         MIPS16e_sd_op = 017,
 609         MIPS16e_lb_op = 020,
 610         MIPS16e_lh_op = 021,
 611         MIPS16e_lwsp_op = 022,
 612         MIPS16e_lw_op = 023,
 613         MIPS16e_lbu_op = 024,
 614         MIPS16e_lhu_op = 025,
 615         MIPS16e_lwpc_op = 026,
 616         MIPS16e_lwu_op = 027,
 617         MIPS16e_sb_op = 030,
 618         MIPS16e_sh_op = 031,
 619         MIPS16e_swsp_op = 032,
 620         MIPS16e_sw_op = 033,
 621         MIPS16e_rr_op = 035,
 622         MIPS16e_extend_op = 036,
 623         MIPS16e_i64_op = 037,
 624 };
 625
 626 enum MIPS16e_i64_func {
 627         MIPS16e_ldsp_func,
 628         MIPS16e_sdsp_func,
 629         MIPS16e_sdrasp_func,
 630         MIPS16e_dadjsp_func,
 631         MIPS16e_ldpc_func,
 632 };
 633
 634 enum MIPS16e_rr_func {
 635         MIPS16e_jr_func,
 636 };
 637
 638 enum MIPS6e_i8_func {
 639         MIPS16e_swrasp_func = 02,
 640 };
 641
 642 /*
 643  * (microMIPS) NOP instruction.
 644  */
 645 #define MM_NOP16        0x0c00
 646
 647 struct j_format {
 648         __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 649         __BITFIELD_FIELD(unsigned int target : 26,
 650         ;))
 651 };
 652
 653 struct i_format {                       /* signed immediate format */
 654         __BITFIELD_FIELD(unsigned int opcode : 6,
 655         __BITFIELD_FIELD(unsigned int rs : 5,
 656         __BITFIELD_FIELD(unsigned int rt : 5,
 657         __BITFIELD_FIELD(signed int simmediate : 16,
 658         ;))))
 659 };
 660
 661 struct u_format {                       /* unsigned immediate format */
 662         __BITFIELD_FIELD(unsigned int opcode : 6,
 663         __BITFIELD_FIELD(unsigned int rs : 5,
 664         __BITFIELD_FIELD(unsigned int rt : 5,
 665         __BITFIELD_FIELD(unsigned int uimmediate : 16,
 666         ;))))
 667 };
 668
 669 struct c_format {                       /* Cache (>= R6000) format */
 670         __BITFIELD_FIELD(unsigned int opcode : 6,
 671         __BITFIELD_FIELD(unsigned int rs : 5,
 672         __BITFIELD_FIELD(unsigned int c_op : 3,
 673         __BITFIELD_FIELD(unsigned int cache : 2,
 674         __BITFIELD_FIELD(unsigned int simmediate : 16,
 675         ;)))))
 676 };
 677
 678 struct r_format {                       /* Register format */
 679         __BITFIELD_FIELD(unsigned int opcode : 6,
 680         __BITFIELD_FIELD(unsigned int rs : 5,
 681         __BITFIELD_FIELD(unsigned int rt : 5,
 682         __BITFIELD_FIELD(unsigned int rd : 5,
 683         __BITFIELD_FIELD(unsigned int re : 5,
 684         __BITFIELD_FIELD(unsigned int func : 6,
 685         ;))))))
 686 };
 687
 688 struct c0r_format {                     /* C0 register format */
 689         __BITFIELD_FIELD(unsigned int opcode : 6,
 690         __BITFIELD_FIELD(unsigned int rs : 5,
 691         __BITFIELD_FIELD(unsigned int rt : 5,
 692         __BITFIELD_FIELD(unsigned int rd : 5,
 693         __BITFIELD_FIELD(unsigned int z: 8,
 694         __BITFIELD_FIELD(unsigned int sel : 3,
 695         ;))))))
 696 };
 697
 698 struct mfmc0_format {                   /* MFMC0 register format */
 699         __BITFIELD_FIELD(unsigned int opcode : 6,
 700         __BITFIELD_FIELD(unsigned int rs : 5,
 701         __BITFIELD_FIELD(unsigned int rt : 5,
 702         __BITFIELD_FIELD(unsigned int rd : 5,
 703         __BITFIELD_FIELD(unsigned int re : 5,
 704         __BITFIELD_FIELD(unsigned int sc : 1,
 705         __BITFIELD_FIELD(unsigned int : 2,
 706         __BITFIELD_FIELD(unsigned int sel : 3,
 707         ;))))))))
 708 };
 709
 710 struct co_format {                      /* C0 CO format */
 711         __BITFIELD_FIELD(unsigned int opcode : 6,
 712         __BITFIELD_FIELD(unsigned int co : 1,
 713         __BITFIELD_FIELD(unsigned int code : 19,
 714         __BITFIELD_FIELD(unsigned int func : 6,
 715         ;))))
 716 };
 717
 718 struct p_format {               /* Performance counter format (R10000) */
 719         __BITFIELD_FIELD(unsigned int opcode : 6,
 720         __BITFIELD_FIELD(unsigned int rs : 5,
 721         __BITFIELD_FIELD(unsigned int rt : 5,
 722         __BITFIELD_FIELD(unsigned int rd : 5,
 723         __BITFIELD_FIELD(unsigned int re : 5,
 724         __BITFIELD_FIELD(unsigned int func : 6,
 725         ;))))))
 726 };
 727
 728 struct f_format {                       /* FPU register format */
 729         __BITFIELD_FIELD(unsigned int opcode : 6,
 730         __BITFIELD_FIELD(unsigned int : 1,
 731         __BITFIELD_FIELD(unsigned int fmt : 4,
 732         __BITFIELD_FIELD(unsigned int rt : 5,
 733         __BITFIELD_FIELD(unsigned int rd : 5,
 734         __BITFIELD_FIELD(unsigned int re : 5,
 735         __BITFIELD_FIELD(unsigned int func : 6,
 736         ;)))))))
 737 };
 738
 739 struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 740         __BITFIELD_FIELD(unsigned int opcode : 6,
 741         __BITFIELD_FIELD(unsigned int fr : 5,
 742         __BITFIELD_FIELD(unsigned int ft : 5,
 743         __BITFIELD_FIELD(unsigned int fs : 5,
 744         __BITFIELD_FIELD(unsigned int fd : 5,
 745         __BITFIELD_FIELD(unsigned int func : 4,
 746         __BITFIELD_FIELD(unsigned int fmt : 2,
 747         ;)))))))
 748 };
 749
 750 struct b_format {                       /* BREAK and SYSCALL */
 751         __BITFIELD_FIELD(unsigned int opcode : 6,
 752         __BITFIELD_FIELD(unsigned int code : 20,
 753         __BITFIELD_FIELD(unsigned int func : 6,
 754         ;)))
 755 };
 756
 757 struct ps_format {                      /* MIPS-3D / paired single format */
 758         __BITFIELD_FIELD(unsigned int opcode : 6,
 759         __BITFIELD_FIELD(unsigned int rs : 5,
 760         __BITFIELD_FIELD(unsigned int ft : 5,
 761         __BITFIELD_FIELD(unsigned int fs : 5,
 762         __BITFIELD_FIELD(unsigned int fd : 5,
 763         __BITFIELD_FIELD(unsigned int func : 6,
 764         ;))))))
 765 };
 766
 767 struct v_format {                               /* MDMX vector format */
 768         __BITFIELD_FIELD(unsigned int opcode : 6,
 769         __BITFIELD_FIELD(unsigned int sel : 4,
 770         __BITFIELD_FIELD(unsigned int fmt : 1,
 771         __BITFIELD_FIELD(unsigned int vt : 5,
 772         __BITFIELD_FIELD(unsigned int vs : 5,
 773         __BITFIELD_FIELD(unsigned int vd : 5,
 774         __BITFIELD_FIELD(unsigned int func : 6,
 775         ;)))))))
 776 };
 777
 778 struct msa_mi10_format {                /* MSA MI10 */
 779         __BITFIELD_FIELD(unsigned int opcode : 6,
 780         __BITFIELD_FIELD(signed int s10 : 10,
 781         __BITFIELD_FIELD(unsigned int rs : 5,
 782         __BITFIELD_FIELD(unsigned int wd : 5,
 783         __BITFIELD_FIELD(unsigned int func : 4,
 784         __BITFIELD_FIELD(unsigned int df : 2,
 785         ;))))))
 786 };
 787
 788 struct dsp_format {             /* SPEC3 DSP format instructions */
 789         __BITFIELD_FIELD(unsigned int opcode : 6,
 790         __BITFIELD_FIELD(unsigned int base : 5,
 791         __BITFIELD_FIELD(unsigned int index : 5,
 792         __BITFIELD_FIELD(unsigned int rd : 5,
 793         __BITFIELD_FIELD(unsigned int op : 5,
 794         __BITFIELD_FIELD(unsigned int func : 6,
 795         ;))))))
 796 };
 797
 798 struct mxu_lx_format {          /* SPEC2 MXU LX format instructions */
 799         __BITFIELD_FIELD(unsigned int opcode : 6,
 800         __BITFIELD_FIELD(unsigned int rs : 5,
 801         __BITFIELD_FIELD(unsigned int rt : 5,
 802         __BITFIELD_FIELD(unsigned int rd : 5,
 803         __BITFIELD_FIELD(unsigned int strd : 2,
 804         __BITFIELD_FIELD(unsigned int op : 3,
 805         __BITFIELD_FIELD(unsigned int func : 6,
 806         ;)))))))
 807 };
 808
 809 struct spec3_format {   /* SPEC3 */
 810         __BITFIELD_FIELD(unsigned int opcode:6,
 811         __BITFIELD_FIELD(unsigned int rs:5,
 812         __BITFIELD_FIELD(unsigned int rt:5,
 813         __BITFIELD_FIELD(signed int simmediate:9,
 814         __BITFIELD_FIELD(unsigned int func:7,
 815         ;)))))
 816 };
 817
 818 /*
 819  * microMIPS instruction formats (32-bit length)
 820  *
 821  * NOTE:
 822  *      Parenthesis denote whether the format is a microMIPS instruction or
 823  *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 824  */
 825 struct fb_format {              /* FPU branch format (MIPS32) */
 826         __BITFIELD_FIELD(unsigned int opcode : 6,
 827         __BITFIELD_FIELD(unsigned int bc : 5,
 828         __BITFIELD_FIELD(unsigned int cc : 3,
 829         __BITFIELD_FIELD(unsigned int flag : 2,
 830         __BITFIELD_FIELD(signed int simmediate : 16,
 831         ;)))))
 832 };
 833
 834 struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 835         __BITFIELD_FIELD(unsigned int opcode : 6,
 836         __BITFIELD_FIELD(unsigned int fmt : 5,
 837         __BITFIELD_FIELD(unsigned int ft : 5,
 838         __BITFIELD_FIELD(unsigned int fs : 5,
 839         __BITFIELD_FIELD(unsigned int fd : 5,
 840         __BITFIELD_FIELD(unsigned int func : 6,
 841         ;))))))
 842 };
 843
 844 struct mm_fp0_format {          /* FPU multiply and add format (microMIPS) */
 845         __BITFIELD_FIELD(unsigned int opcode : 6,
 846         __BITFIELD_FIELD(unsigned int ft : 5,
 847         __BITFIELD_FIELD(unsigned int fs : 5,
 848         __BITFIELD_FIELD(unsigned int fd : 5,
 849         __BITFIELD_FIELD(unsigned int fmt : 3,
 850         __BITFIELD_FIELD(unsigned int op : 2,
 851         __BITFIELD_FIELD(unsigned int func : 6,
 852         ;)))))))
 853 };
 854
 855 struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 856         __BITFIELD_FIELD(unsigned int opcode : 6,
 857         __BITFIELD_FIELD(unsigned int op : 5,
 858         __BITFIELD_FIELD(unsigned int rt : 5,
 859         __BITFIELD_FIELD(unsigned int fs : 5,
 860         __BITFIELD_FIELD(unsigned int fd : 5,
 861         __BITFIELD_FIELD(unsigned int func : 6,
 862         ;))))))
 863 };
 864
 865 struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 866         __BITFIELD_FIELD(unsigned int opcode : 6,
 867         __BITFIELD_FIELD(unsigned int rt : 5,
 868         __BITFIELD_FIELD(unsigned int fs : 5,
 869         __BITFIELD_FIELD(unsigned int fmt : 2,
 870         __BITFIELD_FIELD(unsigned int op : 8,
 871         __BITFIELD_FIELD(unsigned int func : 6,
 872         ;))))))
 873 };
 874
 875 struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 876         __BITFIELD_FIELD(unsigned int opcode : 6,
 877         __BITFIELD_FIELD(unsigned int fd : 5,
 878         __BITFIELD_FIELD(unsigned int fs : 5,
 879         __BITFIELD_FIELD(unsigned int cc : 3,
 880         __BITFIELD_FIELD(unsigned int zero : 2,
 881         __BITFIELD_FIELD(unsigned int fmt : 2,
 882         __BITFIELD_FIELD(unsigned int op : 3,
 883         __BITFIELD_FIELD(unsigned int func : 6,
 884         ;))))))))
 885 };
 886
 887 struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 888         __BITFIELD_FIELD(unsigned int opcode : 6,
 889         __BITFIELD_FIELD(unsigned int rt : 5,
 890         __BITFIELD_FIELD(unsigned int fs : 5,
 891         __BITFIELD_FIELD(unsigned int fmt : 3,
 892         __BITFIELD_FIELD(unsigned int op : 7,
 893         __BITFIELD_FIELD(unsigned int func : 6,
 894         ;))))))
 895 };
 896
 897 struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 898         __BITFIELD_FIELD(unsigned int opcode : 6,
 899         __BITFIELD_FIELD(unsigned int rt : 5,
 900         __BITFIELD_FIELD(unsigned int fs : 5,
 901         __BITFIELD_FIELD(unsigned int cc : 3,
 902         __BITFIELD_FIELD(unsigned int fmt : 3,
 903         __BITFIELD_FIELD(unsigned int cond : 4,
 904         __BITFIELD_FIELD(unsigned int func : 6,
 905         ;)))))))
 906 };
 907
 908 struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 909         __BITFIELD_FIELD(unsigned int opcode : 6,
 910         __BITFIELD_FIELD(unsigned int index : 5,
 911         __BITFIELD_FIELD(unsigned int base : 5,
 912         __BITFIELD_FIELD(unsigned int fd : 5,
 913         __BITFIELD_FIELD(unsigned int op : 5,
 914         __BITFIELD_FIELD(unsigned int func : 6,
 915         ;))))))
 916 };
 917
 918 struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 919         __BITFIELD_FIELD(unsigned int opcode : 6,
 920         __BITFIELD_FIELD(unsigned int fr : 5,
 921         __BITFIELD_FIELD(unsigned int ft : 5,
 922         __BITFIELD_FIELD(unsigned int fs : 5,
 923         __BITFIELD_FIELD(unsigned int fd : 5,
 924         __BITFIELD_FIELD(unsigned int func : 6,
 925         ;))))))
 926 };
 927
 928 struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 929         __BITFIELD_FIELD(unsigned int opcode : 6,
 930         __BITFIELD_FIELD(unsigned int ft : 5,
 931         __BITFIELD_FIELD(unsigned int fs : 5,
 932         __BITFIELD_FIELD(unsigned int fd : 5,
 933         __BITFIELD_FIELD(unsigned int fr : 5,
 934         __BITFIELD_FIELD(unsigned int func : 6,
 935         ;))))))
 936 };
 937
 938 struct mm_i_format {            /* Immediate format (microMIPS) */
 939         __BITFIELD_FIELD(unsigned int opcode : 6,
 940         __BITFIELD_FIELD(unsigned int rt : 5,
 941         __BITFIELD_FIELD(unsigned int rs : 5,
 942         __BITFIELD_FIELD(signed int simmediate : 16,
 943         ;))))
 944 };
 945
 946 struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 947         __BITFIELD_FIELD(unsigned int opcode : 6,
 948         __BITFIELD_FIELD(unsigned int rd : 5,
 949         __BITFIELD_FIELD(unsigned int base : 5,
 950         __BITFIELD_FIELD(unsigned int func : 4,
 951         __BITFIELD_FIELD(signed int simmediate : 12,
 952         ;)))))
 953 };
 954
 955 struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 956         __BITFIELD_FIELD(unsigned int opcode : 6,
 957         __BITFIELD_FIELD(unsigned int index : 5,
 958         __BITFIELD_FIELD(unsigned int base : 5,
 959         __BITFIELD_FIELD(unsigned int rd : 5,
 960         __BITFIELD_FIELD(unsigned int func : 11,
 961         ;)))))
 962 };
 963
 964 struct mm_a_format {            /* ADDIUPC format (microMIPS) */
 965         __BITFIELD_FIELD(unsigned int opcode : 6,
 966         __BITFIELD_FIELD(unsigned int rs : 3,
 967         __BITFIELD_FIELD(signed int simmediate : 23,
 968         ;)))
 969 };
 970
 971 /*
 972  * microMIPS instruction formats (16-bit length)
 973  */
 974 struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 975         __BITFIELD_FIELD(unsigned int opcode : 6,
 976         __BITFIELD_FIELD(signed int simmediate : 10,
 977         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 978         ;)))
 979 };
 980
 981 struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 982         __BITFIELD_FIELD(unsigned int opcode : 6,
 983         __BITFIELD_FIELD(unsigned int rs : 3,
 984         __BITFIELD_FIELD(signed int simmediate : 7,
 985         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 986         ;))))
 987 };
 988
 989 struct mm16_m_format {          /* Multi-word load/store format */
 990         __BITFIELD_FIELD(unsigned int opcode : 6,
 991         __BITFIELD_FIELD(unsigned int func : 4,
 992         __BITFIELD_FIELD(unsigned int rlist : 2,
 993         __BITFIELD_FIELD(unsigned int imm : 4,
 994         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 995         ;)))))
 996 };
 997
 998 struct mm16_rb_format {         /* Signed immediate format */
 999         __BITFIELD_FIELD(unsigned int opcode : 6,
1000         __BITFIELD_FIELD(unsigned int rt : 3,
1001         __BITFIELD_FIELD(unsigned int base : 3,
1002         __BITFIELD_FIELD(signed int simmediate : 4,
1003         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
1004         ;)))))
1005 };
1006
1007 struct mm16_r3_format {         /* Load from global pointer format */
1008         __BITFIELD_FIELD(unsigned int opcode : 6,
1009         __BITFIELD_FIELD(unsigned int rt : 3,
1010         __BITFIELD_FIELD(signed int simmediate : 7,
1011         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
1012         ;))))
1013 };
1014
1015 struct mm16_r5_format {         /* Load/store from stack pointer format */
1016         __BITFIELD_FIELD(unsigned int opcode : 6,
1017         __BITFIELD_FIELD(unsigned int rt : 5,
1018         __BITFIELD_FIELD(unsigned int imm : 5,
1019         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
1020         ;))))
1021 };
1022
1023 /*
1024  * Loongson-3 overridden COP2 instruction formats (32-bit length)
1025  */
1026 struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */
1027         __BITFIELD_FIELD(unsigned int opcode : 6,
1028         __BITFIELD_FIELD(unsigned int base : 5,
1029         __BITFIELD_FIELD(unsigned int rt : 5,
1030         __BITFIELD_FIELD(unsigned int fr : 1,
1031         __BITFIELD_FIELD(unsigned int offset : 9,
1032         __BITFIELD_FIELD(unsigned int ls : 1,
1033         __BITFIELD_FIELD(unsigned int rq : 5,
1034         ;)))))))
1035 };
1036
1037 struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */
1038         __BITFIELD_FIELD(unsigned int opcode : 6,
1039         __BITFIELD_FIELD(unsigned int base : 5,
1040         __BITFIELD_FIELD(unsigned int rt : 5,
1041         __BITFIELD_FIELD(unsigned int index : 5,
1042         __BITFIELD_FIELD(unsigned int offset : 8,
1043         __BITFIELD_FIELD(unsigned int opcode1 : 3,
1044         ;))))))
1045 };
1046
1047 struct loongson3_lscsr_format { /* Loongson-3 CPUCFG&CSR read/write format */
1048         __BITFIELD_FIELD(unsigned int opcode : 6,
1049         __BITFIELD_FIELD(unsigned int rs : 5,
1050         __BITFIELD_FIELD(unsigned int fr : 5,
1051         __BITFIELD_FIELD(unsigned int rd : 5,
1052         __BITFIELD_FIELD(unsigned int fd : 5,
1053         __BITFIELD_FIELD(unsigned int func : 6,
1054         ;))))))
1055 };
1056
1057 /*
1058  * MIPS16e instruction formats (16-bit length)
1059  */
1060 struct m16e_rr {
1061         __BITFIELD_FIELD(unsigned int opcode : 5,
1062         __BITFIELD_FIELD(unsigned int rx : 3,
1063         __BITFIELD_FIELD(unsigned int nd : 1,
1064         __BITFIELD_FIELD(unsigned int l : 1,
1065         __BITFIELD_FIELD(unsigned int ra : 1,
1066         __BITFIELD_FIELD(unsigned int func : 5,
1067         ;))))))
1068 };
1069
1070 struct m16e_jal {
1071         __BITFIELD_FIELD(unsigned int opcode : 5,
1072         __BITFIELD_FIELD(unsigned int x : 1,
1073         __BITFIELD_FIELD(unsigned int imm20_16 : 5,
1074         __BITFIELD_FIELD(signed int imm25_21 : 5,
1075         ;))))
1076 };
1077
1078 struct m16e_i64 {
1079         __BITFIELD_FIELD(unsigned int opcode : 5,
1080         __BITFIELD_FIELD(unsigned int func : 3,
1081         __BITFIELD_FIELD(unsigned int imm : 8,
1082         ;)))
1083 };
1084
1085 struct m16e_ri64 {
1086         __BITFIELD_FIELD(unsigned int opcode : 5,
1087         __BITFIELD_FIELD(unsigned int func : 3,
1088         __BITFIELD_FIELD(unsigned int ry : 3,
1089         __BITFIELD_FIELD(unsigned int imm : 5,
1090         ;))))
1091 };
1092
1093 struct m16e_ri {
1094         __BITFIELD_FIELD(unsigned int opcode : 5,
1095         __BITFIELD_FIELD(unsigned int rx : 3,
1096         __BITFIELD_FIELD(unsigned int imm : 8,
1097         ;)))
1098 };
1099
1100 struct m16e_rri {
1101         __BITFIELD_FIELD(unsigned int opcode : 5,
1102         __BITFIELD_FIELD(unsigned int rx : 3,
1103         __BITFIELD_FIELD(unsigned int ry : 3,
1104         __BITFIELD_FIELD(unsigned int imm : 5,
1105         ;))))
1106 };
1107
1108 struct m16e_i8 {
1109         __BITFIELD_FIELD(unsigned int opcode : 5,
1110         __BITFIELD_FIELD(unsigned int func : 3,
1111         __BITFIELD_FIELD(unsigned int imm : 8,
1112         ;)))
1113 };
1114
1115 union mips_instruction {
1116         unsigned int word;
1117         unsigned short halfword[2];
1118         unsigned char byte[4];
1119         struct j_format j_format;
1120         struct i_format i_format;
1121         struct u_format u_format;
1122         struct c_format c_format;
1123         struct r_format r_format;
1124         struct c0r_format c0r_format;
1125         struct mfmc0_format mfmc0_format;
1126         struct co_format co_format;
1127         struct p_format p_format;
1128         struct f_format f_format;
1129         struct ma_format ma_format;
1130         struct msa_mi10_format msa_mi10_format;
1131         struct b_format b_format;
1132         struct ps_format ps_format;
1133         struct v_format v_format;
1134         struct dsp_format dsp_format;
1135         struct spec3_format spec3_format;
1136         struct fb_format fb_format;
1137         struct fp0_format fp0_format;
1138         struct mm_fp0_format mm_fp0_format;
1139         struct fp1_format fp1_format;
1140         struct mm_fp1_format mm_fp1_format;
1141         struct mm_fp2_format mm_fp2_format;
1142         struct mm_fp3_format mm_fp3_format;
1143         struct mm_fp4_format mm_fp4_format;
1144         struct mm_fp5_format mm_fp5_format;
1145         struct fp6_format fp6_format;
1146         struct mm_fp6_format mm_fp6_format;
1147         struct mm_i_format mm_i_format;
1148         struct mm_m_format mm_m_format;
1149         struct mm_x_format mm_x_format;
1150         struct mm_a_format mm_a_format;
1151         struct mm_b0_format mm_b0_format;
1152         struct mm_b1_format mm_b1_format;
1153         struct mm16_m_format mm16_m_format ;
1154         struct mm16_rb_format mm16_rb_format;
1155         struct mm16_r3_format mm16_r3_format;
1156         struct mm16_r5_format mm16_r5_format;
1157         struct loongson3_lswc2_format loongson3_lswc2_format;
1158         struct loongson3_lsdc2_format loongson3_lsdc2_format;
1159         struct loongson3_lscsr_format loongson3_lscsr_format;
1160         struct mxu_lx_format mxu_lx_format;
1161 };
1162
1163 union mips16e_instruction {
1164         unsigned int full : 16;
1165         struct m16e_rr rr;
1166         struct m16e_jal jal;
1167         struct m16e_i64 i64;
1168         struct m16e_ri64 ri64;
1169         struct m16e_ri ri;
1170         struct m16e_rri rri;
1171         struct m16e_i8 i8;
1172 };
1173
1174 #endif /* _UAPI_ASM_INST_H */