arch/riscv/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com>
   4  * Copyright (C) 2012 Regents of the University of California
   5  */
   6
   7 #ifndef _ASM_RISCV_CACHE_H
   8 #define _ASM_RISCV_CACHE_H
   9
  10 #define L1_CACHE_SHIFT          6
  11
  12 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  13
  14 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
  15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
  16 #define ARCH_KMALLOC_MINALIGN   (8)
  17 #endif
  18
  19 /*
  20  * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
  21  * the flat loader aligns it accordingly.
  22  */
  23 #ifndef CONFIG_MMU
  24 #define ARCH_SLAB_MINALIGN      16
  25 #endif
  26
  27 #ifndef __ASSEMBLY__
  28
  29 extern int dma_cache_alignment;
  30 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
  31 #define dma_get_cache_alignment dma_get_cache_alignment
  32 static inline int dma_get_cache_alignment(void)
  33 {
  34         return dma_cache_alignment;
  35 }
  36 #endif
  37
  38 #endif  /* __ASSEMBLY__ */
  39
  40 #endif /* _ASM_RISCV_CACHE_H */