arch/riscv/include/asm/errata_list.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2021 Sifive.
   4  */
   5 #ifndef ASM_ERRATA_LIST_H
   6 #define ASM_ERRATA_LIST_H
   7
   8 #include <asm/alternative.h>
   9 #include <asm/csr.h>
  10 #include <asm/insn-def.h>
  11 #include <asm/hwcap.h>
  12 #include <asm/vendorid_list.h>
  13
  14 #ifdef CONFIG_ERRATA_ANDES
  15 #define ERRATA_ANDES_NO_IOCP 0
  16 #define ERRATA_ANDES_NUMBER 1
  17 #endif
  18
  19 #ifdef CONFIG_ERRATA_SIFIVE
  20 #define ERRATA_SIFIVE_CIP_453 0
  21 #define ERRATA_SIFIVE_CIP_1200 1
  22 #define ERRATA_SIFIVE_NUMBER 2
  23 #endif
  24
  25 #ifdef CONFIG_ERRATA_THEAD
  26 #define ERRATA_THEAD_MAE 0
  27 #define ERRATA_THEAD_PMU 1
  28 #define ERRATA_THEAD_NUMBER 2
  29 #endif
  30
  31 #ifdef __ASSEMBLY__
  32
  33 #define ALT_INSN_FAULT(x)                                               \
  34 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault),                  \
  35             __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp),       \
  36             SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453,                    \
  37             CONFIG_ERRATA_SIFIVE_CIP_453)
  38
  39 #define ALT_PAGE_FAULT(x)                                               \
  40 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault),                       \
  41             __stringify(RISCV_PTR sifive_cip_453_page_fault_trp),       \
  42             SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453,                    \
  43             CONFIG_ERRATA_SIFIVE_CIP_453)
  44 #else /* !__ASSEMBLY__ */
  45
  46 #define ALT_SFENCE_VMA_ASID(asid)                                       \
  47 asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID,    \
  48                 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)  \
  49                 : : "r" (asid) : "memory")
  50
  51 #define ALT_SFENCE_VMA_ADDR(addr)                                       \
  52 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,        \
  53                 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)  \
  54                 : : "r" (addr) : "memory")
  55
  56 #define ALT_SFENCE_VMA_ADDR_ASID(addr, asid)                            \
  57 asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID,    \
  58                 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)  \
  59                 : : "r" (addr), "r" (asid) : "memory")
  60
  61 /*
  62  * _val is marked as "will be overwritten", so need to set it to 0
  63  * in the default case.
  64  */
  65 #define ALT_SVPBMT_SHIFT 61
  66 #define ALT_THEAD_MAE_SHIFT 59
  67 #define ALT_SVPBMT(_val, prot)                                          \
  68 asm(ALTERNATIVE_2("li %0, 0\t\nnop",                                    \
  69                   "li %0, %1\t\nslli %0,%0,%3", 0,                      \
  70                         RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,  \
  71                   "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,        \
  72                         ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)      \
  73                 : "=r"(_val)                                            \
  74                 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),               \
  75                   "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT),             \
  76                   "I"(ALT_SVPBMT_SHIFT),                                \
  77                   "I"(ALT_THEAD_MAE_SHIFT))
  78
  79 #ifdef CONFIG_ERRATA_THEAD_MAE
  80 /*
  81  * IO/NOCACHE memory types are handled together with svpbmt,
  82  * so on T-Head chips, check if no other memory type is set,
  83  * and set the non-0 PMA type if applicable.
  84  */
  85 #define ALT_THEAD_PMA(_val)                                             \
  86 asm volatile(ALTERNATIVE(                                               \
  87         __nops(7),                                                      \
  88         "li      t3, %1\n\t"                                            \
  89         "slli    t3, t3, %3\n\t"                                        \
  90         "and     t3, %0, t3\n\t"                                        \
  91         "bne     t3, zero, 2f\n\t"                                      \
  92         "li      t3, %2\n\t"                                            \
  93         "slli    t3, t3, %3\n\t"                                        \
  94         "or      %0, %0, t3\n\t"                                        \
  95         "2:",  THEAD_VENDOR_ID,                                         \
  96                 ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)              \
  97         : "+r"(_val)                                                    \
  98         : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT),               \
  99           "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT),                  \
 100           "I"(ALT_THEAD_MAE_SHIFT)                                      \
 101         : "t3")
 102 #else
 103 #define ALT_THEAD_PMA(_val)
 104 #endif
 105
 106 #define ALT_CMO_OP(_op, _start, _size, _cachesize)                      \
 107 asm volatile(ALTERNATIVE(                                               \
 108         __nops(5),                                                      \
 109         "mv a0, %1\n\t"                                                 \
 110         "j 2f\n\t"                                                      \
 111         "3:\n\t"                                                        \
 112         CBO_##_op(a0)                                                   \
 113         "add a0, a0, %0\n\t"                                            \
 114         "2:\n\t"                                                        \
 115         "bltu a0, %2, 3b\n\t",                                          \
 116         0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM)               \
 117         : : "r"(_cachesize),                                            \
 118             "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)),       \
 119             "r"((unsigned long)(_start) + (_size))                      \
 120         : "a0")
 121
 122 #define THEAD_C9XX_RV_IRQ_PMU                   17
 123 #define THEAD_C9XX_CSR_SCOUNTEROF               0x5c5
 124
 125 #endif /* __ASSEMBLY__ */
 126
 127 #endif