arch/riscv/include/uapi/asm/hwprobe.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright 2023 Rivos, Inc
   4  */
   5
   6 #ifndef _UAPI_ASM_HWPROBE_H
   7 #define _UAPI_ASM_HWPROBE_H
   8
   9 #include <linux/types.h>
  10
  11 /*
  12  * Interface for probing hardware capabilities from userspace, see
  13  * Documentation/arch/riscv/hwprobe.rst for more information.
  14  */
  15 struct riscv_hwprobe {
  16         __s64 key;
  17         __u64 value;
  18 };
  19
  20 #define RISCV_HWPROBE_KEY_MVENDORID     0
  21 #define RISCV_HWPROBE_KEY_MARCHID       1
  22 #define RISCV_HWPROBE_KEY_MIMPID        2
  23 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
  24 #define         RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
  25 #define RISCV_HWPROBE_KEY_IMA_EXT_0     4
  26 #define         RISCV_HWPROBE_IMA_FD            (1 << 0)
  27 #define         RISCV_HWPROBE_IMA_C             (1 << 1)
  28 #define         RISCV_HWPROBE_IMA_V             (1 << 2)
  29 #define         RISCV_HWPROBE_EXT_ZBA           (1 << 3)
  30 #define         RISCV_HWPROBE_EXT_ZBB           (1 << 4)
  31 #define         RISCV_HWPROBE_EXT_ZBS           (1 << 5)
  32 #define         RISCV_HWPROBE_EXT_ZICBOZ        (1 << 6)
  33 #define         RISCV_HWPROBE_EXT_ZBC           (1 << 7)
  34 #define         RISCV_HWPROBE_EXT_ZBKB          (1 << 8)
  35 #define         RISCV_HWPROBE_EXT_ZBKC          (1 << 9)
  36 #define         RISCV_HWPROBE_EXT_ZBKX          (1 << 10)
  37 #define         RISCV_HWPROBE_EXT_ZKND          (1 << 11)
  38 #define         RISCV_HWPROBE_EXT_ZKNE          (1 << 12)
  39 #define         RISCV_HWPROBE_EXT_ZKNH          (1 << 13)
  40 #define         RISCV_HWPROBE_EXT_ZKSED         (1 << 14)
  41 #define         RISCV_HWPROBE_EXT_ZKSH          (1 << 15)
  42 #define         RISCV_HWPROBE_EXT_ZKT           (1 << 16)
  43 #define         RISCV_HWPROBE_EXT_ZVBB          (1 << 17)
  44 #define         RISCV_HWPROBE_EXT_ZVBC          (1 << 18)
  45 #define         RISCV_HWPROBE_EXT_ZVKB          (1 << 19)
  46 #define         RISCV_HWPROBE_EXT_ZVKG          (1 << 20)
  47 #define         RISCV_HWPROBE_EXT_ZVKNED        (1 << 21)
  48 #define         RISCV_HWPROBE_EXT_ZVKNHA        (1 << 22)
  49 #define         RISCV_HWPROBE_EXT_ZVKNHB        (1 << 23)
  50 #define         RISCV_HWPROBE_EXT_ZVKSED        (1 << 24)
  51 #define         RISCV_HWPROBE_EXT_ZVKSH         (1 << 25)
  52 #define         RISCV_HWPROBE_EXT_ZVKT          (1 << 26)
  53 #define         RISCV_HWPROBE_EXT_ZFH           (1 << 27)
  54 #define         RISCV_HWPROBE_EXT_ZFHMIN        (1 << 28)
  55 #define         RISCV_HWPROBE_EXT_ZIHINTNTL     (1 << 29)
  56 #define         RISCV_HWPROBE_EXT_ZVFH          (1 << 30)
  57 #define         RISCV_HWPROBE_EXT_ZVFHMIN       (1ULL << 31)
  58 #define         RISCV_HWPROBE_EXT_ZFA           (1ULL << 32)
  59 #define         RISCV_HWPROBE_EXT_ZTSO          (1ULL << 33)
  60 #define         RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
  61 #define         RISCV_HWPROBE_EXT_ZICOND        (1ULL << 35)
  62 #define         RISCV_HWPROBE_EXT_ZIHINTPAUSE   (1ULL << 36)
  63 #define         RISCV_HWPROBE_EXT_ZVE32X        (1ULL << 37)
  64 #define         RISCV_HWPROBE_EXT_ZVE32F        (1ULL << 38)
  65 #define         RISCV_HWPROBE_EXT_ZVE64X        (1ULL << 39)
  66 #define         RISCV_HWPROBE_EXT_ZVE64F        (1ULL << 40)
  67 #define         RISCV_HWPROBE_EXT_ZVE64D        (1ULL << 41)
  68 #define         RISCV_HWPROBE_EXT_ZIMOP         (1ULL << 42)
  69 #define         RISCV_HWPROBE_EXT_ZCA           (1ULL << 43)
  70 #define         RISCV_HWPROBE_EXT_ZCB           (1ULL << 44)
  71 #define         RISCV_HWPROBE_EXT_ZCD           (1ULL << 45)
  72 #define         RISCV_HWPROBE_EXT_ZCF           (1ULL << 46)
  73 #define         RISCV_HWPROBE_EXT_ZCMOP         (1ULL << 47)
  74 #define         RISCV_HWPROBE_EXT_ZAWRS         (1ULL << 48)
  75 #define RISCV_HWPROBE_KEY_CPUPERF_0     5
  76 #define         RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
  77 #define         RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
  78 #define         RISCV_HWPROBE_MISALIGNED_SLOW           (2 << 0)
  79 #define         RISCV_HWPROBE_MISALIGNED_FAST           (3 << 0)
  80 #define         RISCV_HWPROBE_MISALIGNED_UNSUPPORTED    (4 << 0)
  81 #define         RISCV_HWPROBE_MISALIGNED_MASK           (7 << 0)
  82 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE     6
  83 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS  7
  84 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
  85 #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF        9
  86 #define         RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN         0
  87 #define         RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED        1
  88 #define         RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW            2
  89 #define         RISCV_HWPROBE_MISALIGNED_SCALAR_FAST            3
  90 #define         RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED     4
  91 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
  92
  93 /* Flags */
  94 #define RISCV_HWPROBE_WHICH_CPUS        (1 << 0)
  95
  96 #endif