arch/x86/include/uapi/asm/amd_hsmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2
   3 #ifndef _UAPI_ASM_X86_AMD_HSMP_H_
   4 #define _UAPI_ASM_X86_AMD_HSMP_H_
   5
   6 #include <linux/types.h>
   7
   8 #pragma pack(4)
   9
  10 #define HSMP_MAX_MSG_LEN 8
  11
  12 /*
  13  * HSMP Messages supported
  14  */
  15 enum hsmp_message_ids {
  16         HSMP_TEST = 1,                  /* 01h Increments input value by 1 */
  17         HSMP_GET_SMU_VER,               /* 02h SMU FW version */
  18         HSMP_GET_PROTO_VER,             /* 03h HSMP interface version */
  19         HSMP_GET_SOCKET_POWER,          /* 04h average package power consumption */
  20         HSMP_SET_SOCKET_POWER_LIMIT,    /* 05h Set the socket power limit */
  21         HSMP_GET_SOCKET_POWER_LIMIT,    /* 06h Get current socket power limit */
  22         HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */
  23         HSMP_SET_BOOST_LIMIT,           /* 08h Set a core maximum frequency limit */
  24         HSMP_SET_BOOST_LIMIT_SOCKET,    /* 09h Set socket maximum frequency level */
  25         HSMP_GET_BOOST_LIMIT,           /* 0Ah Get current frequency limit */
  26         HSMP_GET_PROC_HOT,              /* 0Bh Get PROCHOT status */
  27         HSMP_SET_XGMI_LINK_WIDTH,       /* 0Ch Set max and min width of xGMI Link */
  28         HSMP_SET_DF_PSTATE,             /* 0Dh Alter APEnable/Disable messages behavior */
  29         HSMP_SET_AUTO_DF_PSTATE,        /* 0Eh Enable DF P-State Performance Boost algorithm */
  30         HSMP_GET_FCLK_MCLK,             /* 0Fh Get FCLK and MEMCLK for current socket */
  31         HSMP_GET_CCLK_THROTTLE_LIMIT,   /* 10h Get CCLK frequency limit in socket */
  32         HSMP_GET_C0_PERCENT,            /* 11h Get average C0 residency in socket */
  33         HSMP_SET_NBIO_DPM_LEVEL,        /* 12h Set max/min LCLK DPM Level for a given NBIO */
  34         HSMP_GET_NBIO_DPM_LEVEL,        /* 13h Get LCLK DPM level min and max for a given NBIO */
  35         HSMP_GET_DDR_BANDWIDTH,         /* 14h Get theoretical maximum and current DDR Bandwidth */
  36         HSMP_GET_TEMP_MONITOR,          /* 15h Get socket temperature */
  37         HSMP_GET_DIMM_TEMP_RANGE,       /* 16h Get per-DIMM temperature range and refresh rate */
  38         HSMP_GET_DIMM_POWER,            /* 17h Get per-DIMM power consumption */
  39         HSMP_GET_DIMM_THERMAL,          /* 18h Get per-DIMM thermal sensors */
  40         HSMP_GET_SOCKET_FREQ_LIMIT,     /* 19h Get current active frequency per socket */
  41         HSMP_GET_CCLK_CORE_LIMIT,       /* 1Ah Get CCLK frequency limit per core */
  42         HSMP_GET_RAILS_SVI,             /* 1Bh Get SVI-based Telemetry for all rails */
  43         HSMP_GET_SOCKET_FMAX_FMIN,      /* 1Ch Get Fmax and Fmin per socket */
  44         HSMP_GET_IOLINK_BANDWITH,       /* 1Dh Get current bandwidth on IO Link */
  45         HSMP_GET_XGMI_BANDWITH,         /* 1Eh Get current bandwidth on xGMI Link */
  46         HSMP_SET_GMI3_WIDTH,            /* 1Fh Set max and min GMI3 Link width */
  47         HSMP_SET_PCI_RATE,              /* 20h Control link rate on PCIe devices */
  48         HSMP_SET_POWER_MODE,            /* 21h Select power efficiency profile policy */
  49         HSMP_SET_PSTATE_MAX_MIN,        /* 22h Set the max and min DF P-State  */
  50         HSMP_GET_METRIC_TABLE_VER,      /* 23h Get metrics table version */
  51         HSMP_GET_METRIC_TABLE,          /* 24h Get metrics table */
  52         HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */
  53         HSMP_MSG_ID_MAX,
  54 };
  55
  56 struct hsmp_message {
  57         __u32   msg_id;                 /* Message ID */
  58         __u16   num_args;               /* Number of input argument words in message */
  59         __u16   response_sz;            /* Number of expected output/response words */
  60         __u32   args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */
  61         __u16   sock_ind;               /* socket number */
  62 };
  63
  64 enum hsmp_msg_type {
  65         HSMP_RSVD = -1,
  66         HSMP_SET  = 0,
  67         HSMP_GET  = 1,
  68 };
  69
  70 enum hsmp_proto_versions {
  71         HSMP_PROTO_VER2 = 2,
  72         HSMP_PROTO_VER3,
  73         HSMP_PROTO_VER4,
  74         HSMP_PROTO_VER5,
  75         HSMP_PROTO_VER6
  76 };
  77
  78 struct hsmp_msg_desc {
  79         int num_args;
  80         int response_sz;
  81         enum hsmp_msg_type type;
  82 };
  83
  84 /*
  85  * User may use these comments as reference, please find the
  86  * supported list of messages and message definition in the
  87  * HSMP chapter of respective family/model PPR.
  88  *
  89  * Not supported messages would return -ENOMSG.
  90  */
  91 static const struct hsmp_msg_desc hsmp_msg_desc_table[] = {
  92         /* RESERVED */
  93         {0, 0, HSMP_RSVD},
  94
  95         /*
  96          * HSMP_TEST, num_args = 1, response_sz = 1
  97          * input:  args[0] = xx
  98          * output: args[0] = xx + 1
  99          */
 100         {1, 1, HSMP_GET},
 101
 102         /*
 103          * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1
 104          * output: args[0] = smu fw ver
 105          */
 106         {0, 1, HSMP_GET},
 107
 108         /*
 109          * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1
 110          * output: args[0] = proto version
 111          */
 112         {0, 1, HSMP_GET},
 113
 114         /*
 115          * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1
 116          * output: args[0] = socket power in mWatts
 117          */
 118         {0, 1, HSMP_GET},
 119
 120         /*
 121          * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0
 122          * input: args[0] = power limit value in mWatts
 123          */
 124         {1, 0, HSMP_SET},
 125
 126         /*
 127          * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1
 128          * output: args[0] = socket power limit value in mWatts
 129          */
 130         {0, 1, HSMP_GET},
 131
 132         /*
 133          * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1
 134          * output: args[0] = maximuam socket power limit in mWatts
 135          */
 136         {0, 1, HSMP_GET},
 137
 138         /*
 139          * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0
 140          * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0]
 141          */
 142         {1, 0, HSMP_SET},
 143
 144         /*
 145          * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0
 146          * input: args[0] = boost limit value in MHz
 147          */
 148         {1, 0, HSMP_SET},
 149
 150         /*
 151          * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1
 152          * input: args[0] = apic id
 153          * output: args[0] = boost limit value in MHz
 154          */
 155         {1, 1, HSMP_GET},
 156
 157         /*
 158          * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1
 159          * output: args[0] = proc hot status
 160          */
 161         {0, 1, HSMP_GET},
 162
 163         /*
 164          * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0
 165          * input: args[0] = min link width[15:8] + max link width[7:0]
 166          */
 167         {1, 0, HSMP_SET},
 168
 169         /*
 170          * HSMP_SET_DF_PSTATE, num_args = 1, response_sz = 0
 171          * input: args[0] = df pstate[7:0]
 172          */
 173         {1, 0, HSMP_SET},
 174
 175         /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */
 176         {0, 0, HSMP_SET},
 177
 178         /*
 179          * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2
 180          * output: args[0] = fclk in MHz, args[1] = mclk in MHz
 181          */
 182         {0, 2, HSMP_GET},
 183
 184         /*
 185          * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1
 186          * output: args[0] = core clock in MHz
 187          */
 188         {0, 1, HSMP_GET},
 189
 190         /*
 191          * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1
 192          * output: args[0] = average c0 residency
 193          */
 194         {0, 1, HSMP_GET},
 195
 196         /*
 197          * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0
 198          * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0]
 199          */
 200         {1, 0, HSMP_SET},
 201
 202         /*
 203          * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1
 204          * input: args[0] = nbioid[23:16]
 205          * output: args[0] = max dpm level[15:8] + min dpm level[7:0]
 206          */
 207         {1, 1, HSMP_GET},
 208
 209         /*
 210          * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1
 211          * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] +
 212          * bw in percentage[7:0]
 213          */
 214         {0, 1, HSMP_GET},
 215
 216         /*
 217          * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1
 218          * output: args[0] = temperature in degree celsius. [15:8] integer part +
 219          * [7:5] fractional part
 220          */
 221         {0, 1, HSMP_GET},
 222
 223         /*
 224          * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1
 225          * input: args[0] = DIMM address[7:0]
 226          * output: args[0] = refresh rate[3] + temperature range[2:0]
 227          */
 228         {1, 1, HSMP_GET},
 229
 230         /*
 231          * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1
 232          * input: args[0] = DIMM address[7:0]
 233          * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] +
 234          * DIMM address[7:0]
 235          */
 236         {1, 1, HSMP_GET},
 237
 238         /*
 239          * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1
 240          * input: args[0] = DIMM address[7:0]
 241          * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] +
 242          * DIMM address[7:0]
 243          */
 244         {1, 1, HSMP_GET},
 245
 246         /*
 247          * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1
 248          * output: args[0] = frequency in MHz[31:16] + frequency source[15:0]
 249          */
 250         {0, 1, HSMP_GET},
 251
 252         /*
 253          * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1
 254          * input: args[0] = apic id [31:0]
 255          * output: args[0] = frequency in MHz[31:0]
 256          */
 257         {1, 1, HSMP_GET},
 258
 259         /*
 260          * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1
 261          * output: args[0] = power in mW[31:0]
 262          */
 263         {0, 1, HSMP_GET},
 264
 265         /*
 266          * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1
 267          * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0]
 268          */
 269         {0, 1, HSMP_GET},
 270
 271         /*
 272          * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1
 273          * input: args[0] = link id[15:8] + bw type[2:0]
 274          * output: args[0] = io bandwidth in Mbps[31:0]
 275          */
 276         {1, 1, HSMP_GET},
 277
 278         /*
 279          * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1
 280          * input: args[0] = link id[15:8] + bw type[2:0]
 281          * output: args[0] = xgmi bandwidth in Mbps[31:0]
 282          */
 283         {1, 1, HSMP_GET},
 284
 285         /*
 286          * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0
 287          * input: args[0] = min link width[15:8] + max link width[7:0]
 288          */
 289         {1, 0, HSMP_SET},
 290
 291         /*
 292          * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1
 293          * input: args[0] = link rate control value
 294          * output: args[0] = previous link rate control value
 295          */
 296         {1, 1, HSMP_SET},
 297
 298         /*
 299          * HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0
 300          * input: args[0] = power efficiency mode[2:0]
 301          */
 302         {1, 0, HSMP_SET},
 303
 304         /*
 305          * HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0
 306          * input: args[0] = min df pstate[15:8] + max df pstate[7:0]
 307          */
 308         {1, 0, HSMP_SET},
 309
 310         /*
 311          * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1
 312          * output: args[0] = metrics table version
 313          */
 314         {0, 1, HSMP_GET},
 315
 316         /*
 317          * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0
 318          */
 319         {0, 0, HSMP_GET},
 320
 321         /*
 322          * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 2
 323          * output: args[0] = lower 32 bits of the address
 324          * output: args[1] = upper 32 bits of the address
 325          */
 326         {0, 2, HSMP_GET},
 327 };
 328
 329 /* Metrics table (supported only with proto version 6) */
 330 struct hsmp_metric_table {
 331         __u32 accumulation_counter;
 332
 333         /* TEMPERATURE */
 334         __u32 max_socket_temperature;
 335         __u32 max_vr_temperature;
 336         __u32 max_hbm_temperature;
 337         __u64 max_socket_temperature_acc;
 338         __u64 max_vr_temperature_acc;
 339         __u64 max_hbm_temperature_acc;
 340
 341         /* POWER */
 342         __u32 socket_power_limit;
 343         __u32 max_socket_power_limit;
 344         __u32 socket_power;
 345
 346         /* ENERGY */
 347         __u64 timestamp;
 348         __u64 socket_energy_acc;
 349         __u64 ccd_energy_acc;
 350         __u64 xcd_energy_acc;
 351         __u64 aid_energy_acc;
 352         __u64 hbm_energy_acc;
 353
 354         /* FREQUENCY */
 355         __u32 cclk_frequency_limit;
 356         __u32 gfxclk_frequency_limit;
 357         __u32 fclk_frequency;
 358         __u32 uclk_frequency;
 359         __u32 socclk_frequency[4];
 360         __u32 vclk_frequency[4];
 361         __u32 dclk_frequency[4];
 362         __u32 lclk_frequency[4];
 363         __u64 gfxclk_frequency_acc[8];
 364         __u64 cclk_frequency_acc[96];
 365
 366         /* FREQUENCY RANGE */
 367         __u32 max_cclk_frequency;
 368         __u32 min_cclk_frequency;
 369         __u32 max_gfxclk_frequency;
 370         __u32 min_gfxclk_frequency;
 371         __u32 fclk_frequency_table[4];
 372         __u32 uclk_frequency_table[4];
 373         __u32 socclk_frequency_table[4];
 374         __u32 vclk_frequency_table[4];
 375         __u32 dclk_frequency_table[4];
 376         __u32 lclk_frequency_table[4];
 377         __u32 max_lclk_dpm_range;
 378         __u32 min_lclk_dpm_range;
 379
 380         /* XGMI */
 381         __u32 xgmi_width;
 382         __u32 xgmi_bitrate;
 383         __u64 xgmi_read_bandwidth_acc[8];
 384         __u64 xgmi_write_bandwidth_acc[8];
 385
 386         /* ACTIVITY */
 387         __u32 socket_c0_residency;
 388         __u32 socket_gfx_busy;
 389         __u32 dram_bandwidth_utilization;
 390         __u64 socket_c0_residency_acc;
 391         __u64 socket_gfx_busy_acc;
 392         __u64 dram_bandwidth_acc;
 393         __u32 max_dram_bandwidth;
 394         __u64 dram_bandwidth_utilization_acc;
 395         __u64 pcie_bandwidth_acc[4];
 396
 397         /* THROTTLERS */
 398         __u32 prochot_residency_acc;
 399         __u32 ppt_residency_acc;
 400         __u32 socket_thm_residency_acc;
 401         __u32 vr_thm_residency_acc;
 402         __u32 hbm_thm_residency_acc;
 403         __u32 spare;
 404
 405         /* New items at the end to maintain driver compatibility */
 406         __u32 gfxclk_frequency[8];
 407 };
 408
 409 /* Reset to default packing */
 410 #pragma pack()
 411
 412 /* Define unique ioctl command for hsmp msgs using generic _IOWR */
 413 #define HSMP_BASE_IOCTL_NR      0xF8
 414 #define HSMP_IOCTL_CMD          _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message)
 415
 416 #endif /*_ASM_X86_AMD_HSMP_H_*/