drm/panthor: Don't add write fences to the shared BOs
[drm/drm-misc.git] / arch / x86 / kvm / vmx / capabilities.h
blobcb6588238f4667fa13902d2efc3fe29749fce71d
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_CAPS_H
3 #define __KVM_X86_VMX_CAPS_H
5 #include <asm/vmx.h>
7 #include "../lapic.h"
8 #include "../x86.h"
9 #include "../pmu.h"
10 #include "../cpuid.h"
12 extern bool __read_mostly enable_vpid;
13 extern bool __read_mostly flexpriority_enabled;
14 extern bool __read_mostly enable_ept;
15 extern bool __read_mostly enable_unrestricted_guest;
16 extern bool __read_mostly enable_ept_ad_bits;
17 extern bool __read_mostly enable_pml;
18 extern bool __read_mostly enable_ipiv;
19 extern int __read_mostly pt_mode;
21 #define PT_MODE_SYSTEM 0
22 #define PT_MODE_HOST_GUEST 1
24 #define PMU_CAP_FW_WRITES (1ULL << 13)
25 #define PMU_CAP_LBR_FMT 0x3f
27 struct nested_vmx_msrs {
29 * We only store the "true" versions of the VMX capability MSRs. We
30 * generate the "non-true" versions by setting the must-be-1 bits
31 * according to the SDM.
33 u32 procbased_ctls_low;
34 u32 procbased_ctls_high;
35 u32 secondary_ctls_low;
36 u32 secondary_ctls_high;
37 u32 pinbased_ctls_low;
38 u32 pinbased_ctls_high;
39 u32 exit_ctls_low;
40 u32 exit_ctls_high;
41 u32 entry_ctls_low;
42 u32 entry_ctls_high;
43 u32 misc_low;
44 u32 misc_high;
45 u32 ept_caps;
46 u32 vpid_caps;
47 u64 basic;
48 u64 cr0_fixed0;
49 u64 cr0_fixed1;
50 u64 cr4_fixed0;
51 u64 cr4_fixed1;
52 u64 vmcs_enum;
53 u64 vmfunc_controls;
56 struct vmcs_config {
57 u64 basic;
58 u32 pin_based_exec_ctrl;
59 u32 cpu_based_exec_ctrl;
60 u32 cpu_based_2nd_exec_ctrl;
61 u64 cpu_based_3rd_exec_ctrl;
62 u32 vmexit_ctrl;
63 u32 vmentry_ctrl;
64 u64 misc;
65 struct nested_vmx_msrs nested;
67 extern struct vmcs_config vmcs_config __ro_after_init;
69 struct vmx_capability {
70 u32 ept;
71 u32 vpid;
73 extern struct vmx_capability vmx_capability __ro_after_init;
75 static inline bool cpu_has_vmx_basic_inout(void)
77 return vmcs_config.basic & VMX_BASIC_INOUT;
80 static inline bool cpu_has_virtual_nmis(void)
82 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS &&
83 vmcs_config.cpu_based_exec_ctrl & CPU_BASED_NMI_WINDOW_EXITING;
86 static inline bool cpu_has_vmx_preemption_timer(void)
88 return vmcs_config.pin_based_exec_ctrl &
89 PIN_BASED_VMX_PREEMPTION_TIMER;
92 static inline bool cpu_has_vmx_posted_intr(void)
94 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
97 static inline bool cpu_has_load_ia32_efer(void)
99 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER;
102 static inline bool cpu_has_load_perf_global_ctrl(void)
104 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
107 static inline bool cpu_has_vmx_mpx(void)
109 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS;
112 static inline bool cpu_has_vmx_tpr_shadow(void)
114 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
117 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
119 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
122 static inline bool cpu_has_vmx_msr_bitmap(void)
124 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
127 static inline bool cpu_has_secondary_exec_ctrls(void)
129 return vmcs_config.cpu_based_exec_ctrl &
130 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
133 static inline bool cpu_has_tertiary_exec_ctrls(void)
135 return vmcs_config.cpu_based_exec_ctrl &
136 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS;
139 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
141 return vmcs_config.cpu_based_2nd_exec_ctrl &
142 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
145 static inline bool cpu_has_vmx_ept(void)
147 return vmcs_config.cpu_based_2nd_exec_ctrl &
148 SECONDARY_EXEC_ENABLE_EPT;
151 static inline bool vmx_umip_emulated(void)
153 return !boot_cpu_has(X86_FEATURE_UMIP) &&
154 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_DESC);
157 static inline bool cpu_has_vmx_rdtscp(void)
159 return vmcs_config.cpu_based_2nd_exec_ctrl &
160 SECONDARY_EXEC_ENABLE_RDTSCP;
163 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
165 return vmcs_config.cpu_based_2nd_exec_ctrl &
166 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
169 static inline bool cpu_has_vmx_vpid(void)
171 return vmcs_config.cpu_based_2nd_exec_ctrl &
172 SECONDARY_EXEC_ENABLE_VPID;
175 static inline bool cpu_has_vmx_wbinvd_exit(void)
177 return vmcs_config.cpu_based_2nd_exec_ctrl &
178 SECONDARY_EXEC_WBINVD_EXITING;
181 static inline bool cpu_has_vmx_unrestricted_guest(void)
183 return vmcs_config.cpu_based_2nd_exec_ctrl &
184 SECONDARY_EXEC_UNRESTRICTED_GUEST;
187 static inline bool cpu_has_vmx_apic_register_virt(void)
189 return vmcs_config.cpu_based_2nd_exec_ctrl &
190 SECONDARY_EXEC_APIC_REGISTER_VIRT;
193 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
195 return vmcs_config.cpu_based_2nd_exec_ctrl &
196 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
199 static inline bool cpu_has_vmx_ple(void)
201 return vmcs_config.cpu_based_2nd_exec_ctrl &
202 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
205 static inline bool cpu_has_vmx_rdrand(void)
207 return vmcs_config.cpu_based_2nd_exec_ctrl &
208 SECONDARY_EXEC_RDRAND_EXITING;
211 static inline bool cpu_has_vmx_invpcid(void)
213 return vmcs_config.cpu_based_2nd_exec_ctrl &
214 SECONDARY_EXEC_ENABLE_INVPCID;
217 static inline bool cpu_has_vmx_vmfunc(void)
219 return vmcs_config.cpu_based_2nd_exec_ctrl &
220 SECONDARY_EXEC_ENABLE_VMFUNC;
223 static inline bool cpu_has_vmx_shadow_vmcs(void)
225 /* check if the cpu supports writing r/o exit information fields */
226 if (!(vmcs_config.misc & VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
227 return false;
229 return vmcs_config.cpu_based_2nd_exec_ctrl &
230 SECONDARY_EXEC_SHADOW_VMCS;
233 static inline bool cpu_has_vmx_encls_vmexit(void)
235 return vmcs_config.cpu_based_2nd_exec_ctrl &
236 SECONDARY_EXEC_ENCLS_EXITING;
239 static inline bool cpu_has_vmx_rdseed(void)
241 return vmcs_config.cpu_based_2nd_exec_ctrl &
242 SECONDARY_EXEC_RDSEED_EXITING;
245 static inline bool cpu_has_vmx_pml(void)
247 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
250 static inline bool cpu_has_vmx_xsaves(void)
252 return vmcs_config.cpu_based_2nd_exec_ctrl &
253 SECONDARY_EXEC_ENABLE_XSAVES;
256 static inline bool cpu_has_vmx_waitpkg(void)
258 return vmcs_config.cpu_based_2nd_exec_ctrl &
259 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
262 static inline bool cpu_has_vmx_tsc_scaling(void)
264 return vmcs_config.cpu_based_2nd_exec_ctrl &
265 SECONDARY_EXEC_TSC_SCALING;
268 static inline bool cpu_has_vmx_bus_lock_detection(void)
270 return vmcs_config.cpu_based_2nd_exec_ctrl &
271 SECONDARY_EXEC_BUS_LOCK_DETECTION;
274 static inline bool cpu_has_vmx_apicv(void)
276 return cpu_has_vmx_apic_register_virt() &&
277 cpu_has_vmx_virtual_intr_delivery() &&
278 cpu_has_vmx_posted_intr();
281 static inline bool cpu_has_vmx_ipiv(void)
283 return vmcs_config.cpu_based_3rd_exec_ctrl & TERTIARY_EXEC_IPI_VIRT;
286 static inline bool cpu_has_vmx_flexpriority(void)
288 return cpu_has_vmx_tpr_shadow() &&
289 cpu_has_vmx_virtualize_apic_accesses();
292 static inline bool cpu_has_vmx_ept_execute_only(void)
294 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
297 static inline bool cpu_has_vmx_ept_4levels(void)
299 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
302 static inline bool cpu_has_vmx_ept_5levels(void)
304 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
307 static inline bool cpu_has_vmx_ept_mt_wb(void)
309 return vmx_capability.ept & VMX_EPTP_WB_BIT;
312 static inline bool cpu_has_vmx_ept_2m_page(void)
314 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
317 static inline bool cpu_has_vmx_ept_1g_page(void)
319 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
322 static inline int ept_caps_to_lpage_level(u32 ept_caps)
324 if (ept_caps & VMX_EPT_1GB_PAGE_BIT)
325 return PG_LEVEL_1G;
326 if (ept_caps & VMX_EPT_2MB_PAGE_BIT)
327 return PG_LEVEL_2M;
328 return PG_LEVEL_4K;
331 static inline bool cpu_has_vmx_ept_ad_bits(void)
333 return vmx_capability.ept & VMX_EPT_AD_BIT;
336 static inline bool cpu_has_vmx_invept_context(void)
338 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
341 static inline bool cpu_has_vmx_invept_global(void)
343 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
346 static inline bool cpu_has_vmx_invvpid(void)
348 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
351 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
353 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
356 static inline bool cpu_has_vmx_invvpid_single(void)
358 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
361 static inline bool cpu_has_vmx_invvpid_global(void)
363 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
366 static inline bool cpu_has_vmx_intel_pt(void)
368 return (vmcs_config.misc & VMX_MISC_INTEL_PT) &&
369 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) &&
370 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL);
374 * Processor Trace can operate in one of three modes:
375 * a. system-wide: trace both host/guest and output to host buffer
376 * b. host-only: only trace host and output to host buffer
377 * c. host-guest: trace host and guest simultaneously and output to their
378 * respective buffer
380 * KVM currently only supports (a) and (c).
382 static inline bool vmx_pt_mode_is_system(void)
384 return pt_mode == PT_MODE_SYSTEM;
386 static inline bool vmx_pt_mode_is_host_guest(void)
388 return pt_mode == PT_MODE_HOST_GUEST;
391 static inline bool vmx_pebs_supported(void)
393 return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept;
396 static inline bool cpu_has_notify_vmexit(void)
398 return vmcs_config.cpu_based_2nd_exec_ctrl &
399 SECONDARY_EXEC_NOTIFY_VM_EXITING;
402 #endif /* __KVM_X86_VMX_CAPS_H */