drivers/usb/chipidea/ci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * ci.h - common structures, functions, and macros of the ChipIdea driver
   4  *
   5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   6  *
   7  * Author: David Lopo
   8  */
   9
  10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  11 #define __DRIVERS_USB_CHIPIDEA_CI_H
  12
  13 #include <linux/list.h>
  14 #include <linux/irqreturn.h>
  15 #include <linux/usb.h>
  16 #include <linux/usb/gadget.h>
  17 #include <linux/usb/otg-fsm.h>
  18 #include <linux/usb/otg.h>
  19 #include <linux/usb/role.h>
  20 #include <linux/ulpi/interface.h>
  21
  22 /******************************************************************************
  23  * DEFINE
  24  *****************************************************************************/
  25 #define TD_PAGE_COUNT      5
  26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  27 #define ENDPT_MAX          32
  28 #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
  29
  30 /******************************************************************************
  31  * REGISTERS
  32  *****************************************************************************/
  33 /* Identification Registers */
  34 #define ID_ID                           0x0
  35 #define ID_HWGENERAL                    0x4
  36 #define ID_HWHOST                       0x8
  37 #define ID_HWDEVICE                     0xc
  38 #define ID_HWTXBUF                      0x10
  39 #define ID_HWRXBUF                      0x14
  40 #define ID_SBUSCFG                      0x90
  41
  42 /* register indices */
  43 enum ci_hw_regs {
  44         CAP_CAPLENGTH,
  45         CAP_HCCPARAMS,
  46         CAP_DCCPARAMS,
  47         CAP_TESTMODE,
  48         CAP_LAST = CAP_TESTMODE,
  49         OP_USBCMD,
  50         OP_USBSTS,
  51         OP_USBINTR,
  52         OP_FRINDEX,
  53         OP_DEVICEADDR,
  54         OP_ENDPTLISTADDR,
  55         OP_TTCTRL,
  56         OP_BURSTSIZE,
  57         OP_ULPI_VIEWPORT,
  58         OP_PORTSC,
  59         OP_DEVLC,
  60         OP_OTGSC,
  61         OP_USBMODE,
  62         OP_ENDPTSETUPSTAT,
  63         OP_ENDPTPRIME,
  64         OP_ENDPTFLUSH,
  65         OP_ENDPTSTAT,
  66         OP_ENDPTCOMPLETE,
  67         OP_ENDPTCTRL,
  68         /* endptctrl1..15 follow */
  69         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  70 };
  71
  72 /******************************************************************************
  73  * STRUCTURES
  74  *****************************************************************************/
  75 /**
  76  * struct ci_hw_ep - endpoint representation
  77  * @ep: endpoint structure for gadget drivers
  78  * @dir: endpoint direction (TX/RX)
  79  * @num: endpoint number
  80  * @type: endpoint type
  81  * @name: string description of the endpoint
  82  * @qh: queue head for this endpoint
  83  * @wedge: is the endpoint wedged
  84  * @ci: pointer to the controller
  85  * @lock: pointer to controller's spinlock
  86  * @td_pool: pointer to controller's TD pool
  87  */
  88 struct ci_hw_ep {
  89         struct usb_ep                           ep;
  90         u8                                      dir;
  91         u8                                      num;
  92         u8                                      type;
  93         char                                    name[16];
  94         struct {
  95                 struct list_head        queue;
  96                 struct ci_hw_qh         *ptr;
  97                 dma_addr_t              dma;
  98         }                                       qh;
  99         int                                     wedge;
 100
 101         /* global resources */
 102         struct ci_hdrc                          *ci;
 103         spinlock_t                              *lock;
 104         struct dma_pool                         *td_pool;
 105         struct td_node                          *pending_td;
 106 };
 107
 108 enum ci_role {
 109         CI_ROLE_HOST = 0,
 110         CI_ROLE_GADGET,
 111         CI_ROLE_END,
 112 };
 113
 114 enum ci_revision {
 115         CI_REVISION_1X = 10,    /* Revision 1.x */
 116         CI_REVISION_20 = 20, /* Revision 2.0 */
 117         CI_REVISION_21, /* Revision 2.1 */
 118         CI_REVISION_22, /* Revision 2.2 */
 119         CI_REVISION_23, /* Revision 2.3 */
 120         CI_REVISION_24, /* Revision 2.4 */
 121         CI_REVISION_25, /* Revision 2.5 */
 122         CI_REVISION_25_PLUS, /* Revision above than 2.5 */
 123         CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
 124 };
 125
 126 /**
 127  * struct ci_role_driver - host/gadget role driver
 128  * @start: start this role
 129  * @stop: stop this role
 130  * @suspend: system suspend handler for this role
 131  * @resume: system resume handler for this role
 132  * @irq: irq handler for this role
 133  * @name: role name string (host/gadget)
 134  */
 135 struct ci_role_driver {
 136         int             (*start)(struct ci_hdrc *);
 137         void            (*stop)(struct ci_hdrc *);
 138         void            (*suspend)(struct ci_hdrc *ci);
 139         void            (*resume)(struct ci_hdrc *ci, bool power_lost);
 140         irqreturn_t     (*irq)(struct ci_hdrc *);
 141         const char      *name;
 142 };
 143
 144 /**
 145  * struct hw_bank - hardware register mapping representation
 146  * @lpm: set if the device is LPM capable
 147  * @phys: physical address of the controller's registers
 148  * @abs: absolute address of the beginning of register window
 149  * @cap: capability registers
 150  * @op: operational registers
 151  * @size: size of the register window
 152  * @regmap: register lookup table
 153  */
 154 struct hw_bank {
 155         unsigned        lpm;
 156         resource_size_t phys;
 157         void __iomem    *abs;
 158         void __iomem    *cap;
 159         void __iomem    *op;
 160         size_t          size;
 161         void __iomem    *regmap[OP_LAST + 1];
 162 };
 163
 164 /**
 165  * struct ci_hdrc - chipidea device representation
 166  * @dev: pointer to parent device
 167  * @lock: access synchronization
 168  * @hw_bank: hardware register mapping
 169  * @irq: IRQ number
 170  * @roles: array of supported roles for this controller
 171  * @role: current role
 172  * @is_otg: if the device is otg-capable
 173  * @fsm: otg finite state machine
 174  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 175  * @hr_timeouts: time out list for active otg fsm timers
 176  * @enabled_otg_timer_bits: bits of enabled otg timers
 177  * @next_otg_timer: next nearest enabled timer to be expired
 178  * @work: work for role changing
 179  * @power_lost_work: work for power lost handling
 180  * @wq: workqueue thread
 181  * @qh_pool: allocation pool for queue heads
 182  * @td_pool: allocation pool for transfer descriptors
 183  * @gadget: device side representation for peripheral controller
 184  * @driver: gadget driver
 185  * @resume_state: save the state of gadget suspend from
 186  * @hw_ep_max: total number of endpoints supported by hardware
 187  * @ci_hw_ep: array of endpoints
 188  * @ep0_dir: ep0 direction
 189  * @ep0out: pointer to ep0 OUT endpoint
 190  * @ep0in: pointer to ep0 IN endpoint
 191  * @status: ep0 status request
 192  * @setaddr: if we should set the address on status completion
 193  * @address: usb address received from the host
 194  * @remote_wakeup: host-enabled remote wakeup
 195  * @suspended: suspended by host
 196  * @test_mode: the selected test mode
 197  * @platdata: platform specific information supplied by parent device
 198  * @vbus_active: is VBUS active
 199  * @ulpi: pointer to ULPI device, if any
 200  * @ulpi_ops: ULPI read/write ops for this device
 201  * @phy: pointer to PHY, if any
 202  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 203  * @hcd: pointer to usb_hcd for ehci host driver
 204  * @id_event: indicates there is an id event, and handled at ci_otg_work
 205  * @b_sess_valid_event: indicates there is a vbus event, and handled
 206  * at ci_otg_work
 207  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 208  * @supports_runtime_pm: if runtime pm is supported
 209  * @in_lpm: if the core in low power mode
 210  * @wakeup_int: if wakeup interrupt occur
 211  * @rev: The revision number for controller
 212  * @mutex: protect code from concorrent running when doing role switch
 213  */
 214 struct ci_hdrc {
 215         struct device                   *dev;
 216         spinlock_t                      lock;
 217         struct hw_bank                  hw_bank;
 218         int                             irq;
 219         struct ci_role_driver           *roles[CI_ROLE_END];
 220         enum ci_role                    role;
 221         bool                            is_otg;
 222         struct usb_otg                  otg;
 223         struct otg_fsm                  fsm;
 224         struct hrtimer                  otg_fsm_hrtimer;
 225         ktime_t                         hr_timeouts[NUM_OTG_FSM_TIMERS];
 226         unsigned                        enabled_otg_timer_bits;
 227         enum otg_fsm_timer              next_otg_timer;
 228         struct usb_role_switch          *role_switch;
 229         struct work_struct              work;
 230         struct work_struct              power_lost_work;
 231         struct workqueue_struct         *wq;
 232
 233         struct dma_pool                 *qh_pool;
 234         struct dma_pool                 *td_pool;
 235
 236         struct usb_gadget               gadget;
 237         struct usb_gadget_driver        *driver;
 238         enum usb_device_state           resume_state;
 239         unsigned                        hw_ep_max;
 240         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 241         u32                             ep0_dir;
 242         struct ci_hw_ep                 *ep0out, *ep0in;
 243
 244         struct usb_request              *status;
 245         bool                            setaddr;
 246         u8                              address;
 247         u8                              remote_wakeup;
 248         u8                              suspended;
 249         u8                              test_mode;
 250
 251         struct ci_hdrc_platform_data    *platdata;
 252         int                             vbus_active;
 253         struct ulpi                     *ulpi;
 254         struct ulpi_ops                 ulpi_ops;
 255         struct phy                      *phy;
 256         /* old usb_phy interface */
 257         struct usb_phy                  *usb_phy;
 258         struct usb_hcd                  *hcd;
 259         bool                            id_event;
 260         bool                            b_sess_valid_event;
 261         bool                            imx28_write_fix;
 262         bool                            has_portsc_pec_bug;
 263         bool                            supports_runtime_pm;
 264         bool                            in_lpm;
 265         bool                            wakeup_int;
 266         enum ci_revision                rev;
 267         struct mutex                    mutex;
 268 };
 269
 270 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 271 {
 272         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 273         return ci->roles[ci->role];
 274 }
 275
 276 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 277 {
 278         int ret;
 279
 280         if (role >= CI_ROLE_END)
 281                 return -EINVAL;
 282
 283         if (!ci->roles[role])
 284                 return -ENXIO;
 285
 286         ret = ci->roles[role]->start(ci);
 287         if (ret)
 288                 return ret;
 289
 290         ci->role = role;
 291
 292         if (ci->usb_phy) {
 293                 if (role == CI_ROLE_HOST)
 294                         usb_phy_set_event(ci->usb_phy, USB_EVENT_ID);
 295                 else
 296                         /* in device mode but vbus is invalid*/
 297                         usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
 298         }
 299
 300         return ret;
 301 }
 302
 303 static inline void ci_role_stop(struct ci_hdrc *ci)
 304 {
 305         enum ci_role role = ci->role;
 306
 307         if (role == CI_ROLE_END)
 308                 return;
 309
 310         ci->role = CI_ROLE_END;
 311
 312         ci->roles[role]->stop(ci);
 313
 314         if (ci->usb_phy)
 315                 usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
 316 }
 317
 318 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
 319 {
 320         if (ci->role == CI_ROLE_HOST)
 321                 return USB_ROLE_HOST;
 322         else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
 323                 return USB_ROLE_DEVICE;
 324         else
 325                 return USB_ROLE_NONE;
 326 }
 327
 328 static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
 329 {
 330         if (role == USB_ROLE_HOST)
 331                 return CI_ROLE_HOST;
 332         else if (role == USB_ROLE_DEVICE)
 333                 return CI_ROLE_GADGET;
 334         else
 335                 return CI_ROLE_END;
 336 }
 337
 338 /**
 339  * hw_read_id_reg: reads from a identification register
 340  * @ci: the controller
 341  * @offset: offset from the beginning of identification registers region
 342  * @mask: bitfield mask
 343  *
 344  * This function returns register contents
 345  */
 346 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
 347 {
 348         return ioread32(ci->hw_bank.abs + offset) & mask;
 349 }
 350
 351 /**
 352  * hw_write_id_reg: writes to a identification register
 353  * @ci: the controller
 354  * @offset: offset from the beginning of identification registers region
 355  * @mask: bitfield mask
 356  * @data: new value
 357  */
 358 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
 359                             u32 mask, u32 data)
 360 {
 361         if (~mask)
 362                 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
 363                         | (data & mask);
 364
 365         iowrite32(data, ci->hw_bank.abs + offset);
 366 }
 367
 368 /**
 369  * hw_read: reads from a hw register
 370  * @ci: the controller
 371  * @reg:  register index
 372  * @mask: bitfield mask
 373  *
 374  * This function returns register contents
 375  */
 376 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 377 {
 378         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 379 }
 380
 381 #ifdef CONFIG_SOC_IMX28
 382 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 383 {
 384         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 385 }
 386 #else
 387 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 388 {
 389 }
 390 #endif
 391
 392 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 393                 void __iomem *addr)
 394 {
 395         if (ci->imx28_write_fix)
 396                 imx28_ci_writel(val, addr);
 397         else
 398                 iowrite32(val, addr);
 399 }
 400
 401 /**
 402  * hw_write: writes to a hw register
 403  * @ci: the controller
 404  * @reg:  register index
 405  * @mask: bitfield mask
 406  * @data: new value
 407  */
 408 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 409                             u32 mask, u32 data)
 410 {
 411         if (~mask)
 412                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 413                         | (data & mask);
 414
 415         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 416 }
 417
 418 /**
 419  * hw_test_and_clear: tests & clears a hw register
 420  * @ci: the controller
 421  * @reg:  register index
 422  * @mask: bitfield mask
 423  *
 424  * This function returns register contents
 425  */
 426 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 427                                     u32 mask)
 428 {
 429         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 430
 431         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 432         return val;
 433 }
 434
 435 /**
 436  * hw_test_and_write: tests & writes a hw register
 437  * @ci: the controller
 438  * @reg:  register index
 439  * @mask: bitfield mask
 440  * @data: new value
 441  *
 442  * This function returns register contents
 443  */
 444 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 445                                     u32 mask, u32 data)
 446 {
 447         u32 val = hw_read(ci, reg, ~0);
 448
 449         hw_write(ci, reg, mask, data);
 450         return (val & mask) >> __ffs(mask);
 451 }
 452
 453 /**
 454  * ci_otg_is_fsm_mode: runtime check if otg controller
 455  * is in otg fsm mode.
 456  *
 457  * @ci: chipidea device
 458  */
 459 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
 460 {
 461 #ifdef CONFIG_USB_OTG_FSM
 462         struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
 463
 464         return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
 465                 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
 466                 otg_caps->hnp_support || otg_caps->adp_support);
 467 #else
 468         return false;
 469 #endif
 470 }
 471
 472 int ci_ulpi_init(struct ci_hdrc *ci);
 473 void ci_ulpi_exit(struct ci_hdrc *ci);
 474 int ci_ulpi_resume(struct ci_hdrc *ci);
 475
 476 u32 hw_read_intr_enable(struct ci_hdrc *ci);
 477
 478 u32 hw_read_intr_status(struct ci_hdrc *ci);
 479
 480 int hw_device_reset(struct ci_hdrc *ci);
 481
 482 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 483
 484 u8 hw_port_test_get(struct ci_hdrc *ci);
 485
 486 void hw_phymode_configure(struct ci_hdrc *ci);
 487
 488 void ci_platform_configure(struct ci_hdrc *ci);
 489
 490 void dbg_create_files(struct ci_hdrc *ci);
 491
 492 void dbg_remove_files(struct ci_hdrc *ci);
 493 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */