1 // SPDX-License-Identifier: GPL-2.0
3 * drd.c - DesignWare USB3 DRD Controller Dual-role support
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Roger Quadros <rogerq@ti.com>
10 #include <linux/extcon.h>
11 #include <linux/of_platform.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
19 static void dwc3_otg_disable_events(struct dwc3
*dwc
, u32 disable_mask
)
21 u32 reg
= dwc3_readl(dwc
->regs
, DWC3_OEVTEN
);
23 reg
&= ~(disable_mask
);
24 dwc3_writel(dwc
->regs
, DWC3_OEVTEN
, reg
);
27 static void dwc3_otg_enable_events(struct dwc3
*dwc
, u32 enable_mask
)
29 u32 reg
= dwc3_readl(dwc
->regs
, DWC3_OEVTEN
);
32 dwc3_writel(dwc
->regs
, DWC3_OEVTEN
, reg
);
35 static void dwc3_otg_clear_events(struct dwc3
*dwc
)
37 u32 reg
= dwc3_readl(dwc
->regs
, DWC3_OEVT
);
39 dwc3_writel(dwc
->regs
, DWC3_OEVTEN
, reg
);
42 #define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \
43 DWC3_OEVTEN_DEVRUNSTPSETEN | DWC3_OEVTEN_HIBENTRYEN | \
44 DWC3_OEVTEN_CONIDSTSCHNGEN | DWC3_OEVTEN_HRRCONFNOTIFEN | \
45 DWC3_OEVTEN_HRRINITNOTIFEN | DWC3_OEVTEN_ADEVIDLEEN | \
46 DWC3_OEVTEN_ADEVBHOSTENDEN | DWC3_OEVTEN_ADEVHOSTEN | \
47 DWC3_OEVTEN_ADEVHNPCHNGEN | DWC3_OEVTEN_ADEVSRPDETEN | \
48 DWC3_OEVTEN_ADEVSESSENDDETEN | DWC3_OEVTEN_BDEVBHOSTENDEN | \
49 DWC3_OEVTEN_BDEVHNPCHNGEN | DWC3_OEVTEN_BDEVSESSVLDDETEN | \
50 DWC3_OEVTEN_BDEVVBUSCHNGEN)
52 static irqreturn_t
dwc3_otg_thread_irq(int irq
, void *_dwc
)
54 struct dwc3
*dwc
= _dwc
;
56 spin_lock(&dwc
->lock
);
57 if (dwc
->otg_restart_host
) {
58 dwc3_otg_host_init(dwc
);
59 dwc
->otg_restart_host
= false;
62 spin_unlock(&dwc
->lock
);
64 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_OTG
);
69 static irqreturn_t
dwc3_otg_irq(int irq
, void *_dwc
)
72 struct dwc3
*dwc
= _dwc
;
73 irqreturn_t ret
= IRQ_NONE
;
75 reg
= dwc3_readl(dwc
->regs
, DWC3_OEVT
);
77 /* ignore non OTG events, we can't disable them in OEVTEN */
78 if (!(reg
& DWC3_OTG_ALL_EVENTS
)) {
79 dwc3_writel(dwc
->regs
, DWC3_OEVT
, reg
);
83 if (dwc
->current_otg_role
== DWC3_OTG_ROLE_HOST
&&
84 !(reg
& DWC3_OEVT_DEVICEMODE
))
85 dwc
->otg_restart_host
= true;
86 dwc3_writel(dwc
->regs
, DWC3_OEVT
, reg
);
87 ret
= IRQ_WAKE_THREAD
;
93 static void dwc3_otgregs_init(struct dwc3
*dwc
)
98 * Prevent host/device reset from resetting OTG core.
99 * If we don't do this then xhci_reset (USBCMD.HCRST) will reset
100 * the signal outputs sent to the PHY, the OTG FSM logic of the
101 * core and also the resets to the VBUS filters inside the core.
103 reg
= dwc3_readl(dwc
->regs
, DWC3_OCFG
);
104 reg
|= DWC3_OCFG_SFTRSTMASK
;
105 dwc3_writel(dwc
->regs
, DWC3_OCFG
, reg
);
107 /* Disable hibernation for simplicity */
108 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
109 reg
&= ~DWC3_GCTL_GBLHIBERNATIONEN
;
110 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
113 * Initialize OTG registers as per
114 * Figure 11-4 OTG Driver Overall Programming Flow
116 /* OCFG.SRPCap = 0, OCFG.HNPCap = 0 */
117 reg
= dwc3_readl(dwc
->regs
, DWC3_OCFG
);
118 reg
&= ~(DWC3_OCFG_SRPCAP
| DWC3_OCFG_HNPCAP
);
119 dwc3_writel(dwc
->regs
, DWC3_OCFG
, reg
);
121 dwc3_otg_clear_events(dwc
);
123 dwc3_otg_disable_events(dwc
, DWC3_OTG_ALL_EVENTS
);
124 /* OEVTEN.ConIDStsChngEn = 1. Instead we enable all events */
125 dwc3_otg_enable_events(dwc
, DWC3_OTG_ALL_EVENTS
);
127 * OCTL.PeriMode = 1, OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0,
130 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
131 reg
|= DWC3_OCTL_PERIMODE
;
132 reg
&= ~(DWC3_OCTL_DEVSETHNPEN
| DWC3_OCTL_HSTSETHNPEN
|
134 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
137 static int dwc3_otg_get_irq(struct dwc3
*dwc
)
139 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
142 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "otg");
146 if (irq
== -EPROBE_DEFER
)
149 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "dwc_usb3");
153 if (irq
== -EPROBE_DEFER
)
156 irq
= platform_get_irq(dwc3_pdev
, 0);
167 void dwc3_otg_init(struct dwc3
*dwc
)
172 * As per Figure 11-4 OTG Driver Overall Programming Flow,
173 * block "Initialize GCTL for OTG operation".
175 /* GCTL.PrtCapDir=2'b11 */
176 dwc3_set_prtcap(dwc
, DWC3_GCTL_PRTCAP_OTG
);
177 /* GUSB2PHYCFG0.SusPHY=0 */
178 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
179 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
180 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
182 /* Initialize OTG registers */
183 dwc3_otgregs_init(dwc
);
186 void dwc3_otg_exit(struct dwc3
*dwc
)
188 /* disable all OTG IRQs */
189 dwc3_otg_disable_events(dwc
, DWC3_OTG_ALL_EVENTS
);
190 /* clear all events */
191 dwc3_otg_clear_events(dwc
);
194 /* should be called before Host controller driver is started */
195 void dwc3_otg_host_init(struct dwc3
*dwc
)
199 /* As per Figure 11-10 A-Device Flow Diagram */
200 /* OCFG.HNPCap = 0, OCFG.SRPCap = 0. Already 0 */
203 * OCTL.PeriMode=0, OCTL.TermSelDLPulse = 0,
204 * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
206 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
207 reg
&= ~(DWC3_OCTL_PERIMODE
| DWC3_OCTL_TERMSELIDPULSE
|
208 DWC3_OCTL_DEVSETHNPEN
| DWC3_OCTL_HSTSETHNPEN
);
209 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
212 * OCFG.DisPrtPwrCutoff = 0/1
214 reg
= dwc3_readl(dwc
->regs
, DWC3_OCFG
);
215 reg
&= ~DWC3_OCFG_DISPWRCUTTOFF
;
216 dwc3_writel(dwc
->regs
, DWC3_OCFG
, reg
);
219 * OCFG.SRPCap = 1, OCFG.HNPCap = GHWPARAMS6.HNP_CAP
220 * We don't want SRP/HNP for simple dual-role so leave
225 * OEVTEN.OTGADevHostEvntEn = 1
226 * OEVTEN.OTGADevSessEndDetEvntEn = 1
227 * We don't want HNP/role-swap so leave these disabled.
230 /* GUSB2PHYCFG.ULPIAutoRes = 1/0, GUSB2PHYCFG.SusPHY = 1 */
231 if (!dwc
->dis_u2_susphy_quirk
) {
232 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
233 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
234 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
237 /* Set Port Power to enable VBUS: OCTL.PrtPwrCtl = 1 */
238 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
239 reg
|= DWC3_OCTL_PRTPWRCTL
;
240 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
243 /* should be called after Host controller driver is stopped */
244 static void dwc3_otg_host_exit(struct dwc3
*dwc
)
249 * Exit from A-device flow as per
250 * Figure 11-4 OTG Driver Overall Programming Flow
254 * OEVTEN.OTGADevBHostEndEvntEn=0, OEVTEN.OTGADevHNPChngEvntEn=0
255 * OEVTEN.OTGADevSessEndDetEvntEn=0,
256 * OEVTEN.OTGADevHostEvntEn = 0
257 * But we don't disable any OTG events
260 /* OCTL.HstSetHNPEn = 0, OCTL.PrtPwrCtl=0 */
261 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
262 reg
&= ~(DWC3_OCTL_HSTSETHNPEN
| DWC3_OCTL_PRTPWRCTL
);
263 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
266 /* should be called before the gadget controller driver is started */
267 static void dwc3_otg_device_init(struct dwc3
*dwc
)
271 /* As per Figure 11-20 B-Device Flow Diagram */
274 * OCFG.HNPCap = GHWPARAMS6.HNP_CAP, OCFG.SRPCap = 1
275 * but we keep them 0 for simple dual-role operation.
277 reg
= dwc3_readl(dwc
->regs
, DWC3_OCFG
);
278 /* OCFG.OTGSftRstMsk = 0/1 */
279 reg
|= DWC3_OCFG_SFTRSTMASK
;
280 dwc3_writel(dwc
->regs
, DWC3_OCFG
, reg
);
283 * OCTL.TermSelDLPulse = 0/1, OCTL.HNPReq = 0
284 * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
286 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
287 reg
|= DWC3_OCTL_PERIMODE
;
288 reg
&= ~(DWC3_OCTL_TERMSELIDPULSE
| DWC3_OCTL_HNPREQ
|
289 DWC3_OCTL_DEVSETHNPEN
| DWC3_OCTL_HSTSETHNPEN
);
290 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
291 /* OEVTEN.OTGBDevSesVldDetEvntEn = 1 */
292 dwc3_otg_enable_events(dwc
, DWC3_OEVTEN_BDEVSESSVLDDETEN
);
293 /* GUSB2PHYCFG.ULPIAutoRes = 0, GUSB2PHYCFG0.SusPHY = 1 */
294 if (!dwc
->dis_u2_susphy_quirk
) {
295 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
296 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
297 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
299 /* GCTL.GblHibernationEn = 0. Already 0. */
302 /* should be called after the gadget controller driver is stopped */
303 static void dwc3_otg_device_exit(struct dwc3
*dwc
)
308 * Exit from B-device flow as per
309 * Figure 11-4 OTG Driver Overall Programming Flow
313 * OEVTEN.OTGBDevHNPChngEvntEn = 0
314 * OEVTEN.OTGBDevVBusChngEvntEn = 0
315 * OEVTEN.OTGBDevBHostEndEvntEn = 0
317 dwc3_otg_disable_events(dwc
, DWC3_OEVTEN_BDEVHNPCHNGEN
|
318 DWC3_OEVTEN_BDEVVBUSCHNGEN
|
319 DWC3_OEVTEN_BDEVBHOSTENDEN
);
321 /* OCTL.DevSetHNPEn = 0, OCTL.HNPReq = 0, OCTL.PeriMode=1 */
322 reg
= dwc3_readl(dwc
->regs
, DWC3_OCTL
);
323 reg
&= ~(DWC3_OCTL_DEVSETHNPEN
| DWC3_OCTL_HNPREQ
);
324 reg
|= DWC3_OCTL_PERIMODE
;
325 dwc3_writel(dwc
->regs
, DWC3_OCTL
, reg
);
328 void dwc3_otg_update(struct dwc3
*dwc
, bool ignore_idstatus
)
336 if (dwc
->dr_mode
!= USB_DR_MODE_OTG
)
339 /* don't do anything if debug user changed role to not OTG */
340 if (dwc
->current_dr_role
!= DWC3_GCTL_PRTCAP_OTG
)
343 if (!ignore_idstatus
) {
344 reg
= dwc3_readl(dwc
->regs
, DWC3_OSTS
);
345 id
= !!(reg
& DWC3_OSTS_CONIDSTS
);
347 dwc
->desired_otg_role
= id
? DWC3_OTG_ROLE_DEVICE
:
351 if (dwc
->desired_otg_role
== dwc
->current_otg_role
)
354 switch (dwc
->current_otg_role
) {
355 case DWC3_OTG_ROLE_HOST
:
357 spin_lock_irqsave(&dwc
->lock
, flags
);
358 dwc3_otg_host_exit(dwc
);
359 spin_unlock_irqrestore(&dwc
->lock
, flags
);
361 case DWC3_OTG_ROLE_DEVICE
:
362 dwc3_gadget_exit(dwc
);
363 spin_lock_irqsave(&dwc
->lock
, flags
);
364 dwc3_event_buffers_cleanup(dwc
);
365 dwc3_otg_device_exit(dwc
);
366 spin_unlock_irqrestore(&dwc
->lock
, flags
);
372 spin_lock_irqsave(&dwc
->lock
, flags
);
374 dwc
->current_otg_role
= dwc
->desired_otg_role
;
376 spin_unlock_irqrestore(&dwc
->lock
, flags
);
378 switch (dwc
->desired_otg_role
) {
379 case DWC3_OTG_ROLE_HOST
:
380 spin_lock_irqsave(&dwc
->lock
, flags
);
381 dwc3_otgregs_init(dwc
);
382 dwc3_otg_host_init(dwc
);
383 spin_unlock_irqrestore(&dwc
->lock
, flags
);
384 ret
= dwc3_host_init(dwc
);
386 dev_err(dwc
->dev
, "failed to initialize host\n");
389 otg_set_vbus(dwc
->usb2_phy
->otg
, true);
390 for (i
= 0; i
< dwc
->num_usb2_ports
; i
++) {
391 if (dwc
->usb2_generic_phy
[i
]) {
392 phy_set_mode(dwc
->usb2_generic_phy
[i
],
398 case DWC3_OTG_ROLE_DEVICE
:
399 spin_lock_irqsave(&dwc
->lock
, flags
);
400 dwc3_otgregs_init(dwc
);
401 dwc3_otg_device_init(dwc
);
402 dwc3_event_buffers_setup(dwc
);
403 spin_unlock_irqrestore(&dwc
->lock
, flags
);
406 otg_set_vbus(dwc
->usb2_phy
->otg
, false);
407 if (dwc
->usb2_generic_phy
[0])
408 phy_set_mode(dwc
->usb2_generic_phy
[0], PHY_MODE_USB_DEVICE
);
409 ret
= dwc3_gadget_init(dwc
);
411 dev_err(dwc
->dev
, "failed to initialize peripheral\n");
418 static void dwc3_drd_update(struct dwc3
*dwc
)
423 id
= extcon_get_state(dwc
->edev
, EXTCON_USB_HOST
);
426 dwc3_set_mode(dwc
, id
?
427 DWC3_GCTL_PRTCAP_HOST
:
428 DWC3_GCTL_PRTCAP_DEVICE
);
432 static int dwc3_drd_notifier(struct notifier_block
*nb
,
433 unsigned long event
, void *ptr
)
435 struct dwc3
*dwc
= container_of(nb
, struct dwc3
, edev_nb
);
437 dwc3_set_mode(dwc
, event
?
438 DWC3_GCTL_PRTCAP_HOST
:
439 DWC3_GCTL_PRTCAP_DEVICE
);
444 #if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
445 #define ROLE_SWITCH 1
446 static int dwc3_usb_role_switch_set(struct usb_role_switch
*sw
,
449 struct dwc3
*dwc
= usb_role_switch_get_drvdata(sw
);
454 mode
= DWC3_GCTL_PRTCAP_HOST
;
456 case USB_ROLE_DEVICE
:
457 mode
= DWC3_GCTL_PRTCAP_DEVICE
;
460 if (dwc
->role_switch_default_mode
== USB_DR_MODE_HOST
)
461 mode
= DWC3_GCTL_PRTCAP_HOST
;
463 mode
= DWC3_GCTL_PRTCAP_DEVICE
;
467 dwc3_set_mode(dwc
, mode
);
471 static enum usb_role
dwc3_usb_role_switch_get(struct usb_role_switch
*sw
)
473 struct dwc3
*dwc
= usb_role_switch_get_drvdata(sw
);
477 spin_lock_irqsave(&dwc
->lock
, flags
);
478 switch (dwc
->current_dr_role
) {
479 case DWC3_GCTL_PRTCAP_HOST
:
480 role
= USB_ROLE_HOST
;
482 case DWC3_GCTL_PRTCAP_DEVICE
:
483 role
= USB_ROLE_DEVICE
;
485 case DWC3_GCTL_PRTCAP_OTG
:
486 role
= dwc
->current_otg_role
;
489 if (dwc
->role_switch_default_mode
== USB_DR_MODE_HOST
)
490 role
= USB_ROLE_HOST
;
492 role
= USB_ROLE_DEVICE
;
495 spin_unlock_irqrestore(&dwc
->lock
, flags
);
499 static int dwc3_setup_role_switch(struct dwc3
*dwc
)
501 struct usb_role_switch_desc dwc3_role_switch
= {NULL
};
504 dwc
->role_switch_default_mode
= usb_get_role_switch_default_mode(dwc
->dev
);
505 if (dwc
->role_switch_default_mode
== USB_DR_MODE_HOST
) {
506 mode
= DWC3_GCTL_PRTCAP_HOST
;
508 dwc
->role_switch_default_mode
= USB_DR_MODE_PERIPHERAL
;
509 mode
= DWC3_GCTL_PRTCAP_DEVICE
;
511 dwc3_set_mode(dwc
, mode
);
513 dwc3_role_switch
.fwnode
= dev_fwnode(dwc
->dev
);
514 dwc3_role_switch
.set
= dwc3_usb_role_switch_set
;
515 dwc3_role_switch
.get
= dwc3_usb_role_switch_get
;
516 dwc3_role_switch
.driver_data
= dwc
;
517 dwc
->role_sw
= usb_role_switch_register(dwc
->dev
, &dwc3_role_switch
);
518 if (IS_ERR(dwc
->role_sw
))
519 return PTR_ERR(dwc
->role_sw
);
521 if (dwc
->dev
->of_node
) {
522 /* populate connector entry */
523 int ret
= devm_of_platform_populate(dwc
->dev
);
526 usb_role_switch_unregister(dwc
->role_sw
);
528 dev_err(dwc
->dev
, "DWC3 platform devices creation failed: %i\n", ret
);
536 #define ROLE_SWITCH 0
537 #define dwc3_setup_role_switch(x) 0
540 int dwc3_drd_init(struct dwc3
*dwc
)
545 device_property_read_bool(dwc
->dev
, "usb-role-switch"))
546 return dwc3_setup_role_switch(dwc
);
549 dwc
->edev_nb
.notifier_call
= dwc3_drd_notifier
;
550 ret
= extcon_register_notifier(dwc
->edev
, EXTCON_USB_HOST
,
553 dev_err(dwc
->dev
, "couldn't register cable notifier\n");
557 dwc3_drd_update(dwc
);
559 dwc3_set_prtcap(dwc
, DWC3_GCTL_PRTCAP_OTG
);
561 /* use OTG block to get ID event */
562 irq
= dwc3_otg_get_irq(dwc
);
568 /* disable all OTG IRQs */
569 dwc3_otg_disable_events(dwc
, DWC3_OTG_ALL_EVENTS
);
570 /* clear all events */
571 dwc3_otg_clear_events(dwc
);
573 ret
= request_threaded_irq(dwc
->otg_irq
, dwc3_otg_irq
,
575 IRQF_SHARED
, "dwc3-otg", dwc
);
577 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
584 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_OTG
);
590 void dwc3_drd_exit(struct dwc3
*dwc
)
595 usb_role_switch_unregister(dwc
->role_sw
);
598 extcon_unregister_notifier(dwc
->edev
, EXTCON_USB_HOST
,
601 cancel_work_sync(&dwc
->drd_work
);
603 /* debug user might have changed role, clean based on current role */
604 switch (dwc
->current_dr_role
) {
605 case DWC3_GCTL_PRTCAP_HOST
:
608 case DWC3_GCTL_PRTCAP_DEVICE
:
609 dwc3_gadget_exit(dwc
);
610 dwc3_event_buffers_cleanup(dwc
);
612 case DWC3_GCTL_PRTCAP_OTG
:
614 spin_lock_irqsave(&dwc
->lock
, flags
);
615 dwc
->desired_otg_role
= DWC3_OTG_ROLE_IDLE
;
616 spin_unlock_irqrestore(&dwc
->lock
, flags
);
617 dwc3_otg_update(dwc
, 1);
624 free_irq(dwc
->otg_irq
, dwc
);