drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
  34                                  struct usb_ctrlrequest *ctrl);
  35
  36 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  37                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  38 {
  39         struct dwc3_trb                 *trb;
  40         struct dwc3                     *dwc;
  41
  42         dwc = dep->dwc;
  43         trb = &dwc->ep0_trb[dep->trb_enqueue];
  44
  45         if (chain)
  46                 dep->trb_enqueue++;
  47
  48         trb->bpl = lower_32_bits(buf_dma);
  49         trb->bph = upper_32_bits(buf_dma);
  50         trb->size = len;
  51         trb->ctrl = type;
  52
  53         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  54                         | DWC3_TRB_CTRL_ISP_IMI);
  55
  56         if (chain)
  57                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  58         else
  59                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  60                                 | DWC3_TRB_CTRL_LST);
  61
  62         trace_dwc3_prepare_trb(dep, trb);
  63 }
  64
  65 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  66 {
  67         struct dwc3_gadget_ep_cmd_params params;
  68         struct dwc3                     *dwc;
  69         int                             ret;
  70
  71         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  72                 return 0;
  73
  74         dwc = dep->dwc;
  75
  76         memset(&params, 0, sizeof(params));
  77         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  78         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  79
  80         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  81         if (ret < 0)
  82                 return ret;
  83
  84         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  85
  86         return 0;
  87 }
  88
  89 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  90                 struct dwc3_request *req)
  91 {
  92         struct dwc3             *dwc = dep->dwc;
  93
  94         req->request.actual     = 0;
  95         req->request.status     = -EINPROGRESS;
  96         req->epnum              = dep->number;
  97
  98         list_add_tail(&req->list, &dep->pending_list);
  99
 100         /*
 101          * Gadget driver might not be quick enough to queue a request
 102          * before we get a Transfer Not Ready event on this endpoint.
 103          *
 104          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 105          * flag is set, it's telling us that as soon as Gadget queues the
 106          * required request, we should kick the transfer here because the
 107          * IRQ we were waiting for is long gone.
 108          */
 109         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 110                 unsigned int direction;
 111
 112                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 113
 114                 if (dwc->ep0state != EP0_DATA_PHASE) {
 115                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 116                         return 0;
 117                 }
 118
 119                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 120
 121                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 122                                 DWC3_EP0_DIR_IN);
 123
 124                 return 0;
 125         }
 126
 127         /*
 128          * In case gadget driver asked us to delay the STATUS phase,
 129          * handle it here.
 130          */
 131         if (dwc->delayed_status) {
 132                 unsigned int direction;
 133
 134                 direction = !dwc->ep0_expect_in;
 135                 dwc->delayed_status = false;
 136                 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 137
 138                 if (dwc->ep0state == EP0_STATUS_PHASE)
 139                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 140
 141                 return 0;
 142         }
 143
 144         /*
 145          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 146          *
 147          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 148          * come before issueing Start Transfer command, but if we do, we will
 149          * miss situations where the host starts another SETUP phase instead of
 150          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 151          * Layer Compliance Suite.
 152          *
 153          * The problem surfaces due to the fact that in case of back-to-back
 154          * SETUP packets there will be no XferNotReady(DATA) generated and we
 155          * will be stuck waiting for XferNotReady(DATA) forever.
 156          *
 157          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 158          * it tells us to start Data Phase right away. It also mentions that if
 159          * we receive a SETUP phase instead of the DATA phase, core will issue
 160          * XferComplete for the DATA phase, before actually initiating it in
 161          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 162          * can only be used to print some debugging logs, as the core expects
 163          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 164          * just so it completes right away, without transferring anything and,
 165          * only then, we can go back to the SETUP phase.
 166          *
 167          * Because of this scenario, SNPS decided to change the programming
 168          * model of control transfers and support on-demand transfers only for
 169          * the STATUS phase. To fix the issue we have now, we will always wait
 170          * for gadget driver to queue the DATA phase's struct usb_request, then
 171          * start it right away.
 172          *
 173          * If we're actually in a 2-stage transfer, we will wait for
 174          * XferNotReady(STATUS).
 175          */
 176         if (dwc->three_stage_setup) {
 177                 unsigned int direction;
 178
 179                 direction = dwc->ep0_expect_in;
 180                 dwc->ep0state = EP0_DATA_PHASE;
 181
 182                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 183
 184                 dep->flags &= ~DWC3_EP0_DIR_IN;
 185         }
 186
 187         return 0;
 188 }
 189
 190 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 191                 gfp_t gfp_flags)
 192 {
 193         struct dwc3_request             *req = to_dwc3_request(request);
 194         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 195         struct dwc3                     *dwc = dep->dwc;
 196
 197         unsigned long                   flags;
 198
 199         int                             ret;
 200
 201         spin_lock_irqsave(&dwc->lock, flags);
 202         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
 203                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 204                                 dep->name);
 205                 ret = -ESHUTDOWN;
 206                 goto out;
 207         }
 208
 209         /* we share one TRB for ep0/1 */
 210         if (!list_empty(&dep->pending_list)) {
 211                 ret = -EBUSY;
 212                 goto out;
 213         }
 214
 215         ret = __dwc3_gadget_ep0_queue(dep, req);
 216
 217 out:
 218         spin_unlock_irqrestore(&dwc->lock, flags);
 219
 220         return ret;
 221 }
 222
 223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 224 {
 225         struct dwc3_ep          *dep;
 226
 227         /* reinitialize physical ep1 */
 228         dep = dwc->eps[1];
 229         dep->flags &= DWC3_EP_RESOURCE_ALLOCATED;
 230         dep->flags |= DWC3_EP_ENABLED;
 231
 232         /* stall is always issued on EP0 */
 233         dep = dwc->eps[0];
 234         __dwc3_gadget_ep_set_halt(dep, 1, false);
 235         dep->flags &= DWC3_EP_RESOURCE_ALLOCATED;
 236         dep->flags |= DWC3_EP_ENABLED;
 237         dwc->delayed_status = false;
 238
 239         if (!list_empty(&dep->pending_list)) {
 240                 struct dwc3_request     *req;
 241
 242                 req = next_request(&dep->pending_list);
 243                 if (!dwc->connected)
 244                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 245                 else
 246                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
 247         }
 248
 249         dwc->eps[0]->trb_enqueue = 0;
 250         dwc->eps[1]->trb_enqueue = 0;
 251         dwc->ep0state = EP0_SETUP_PHASE;
 252         dwc3_ep0_out_start(dwc);
 253 }
 254
 255 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 256 {
 257         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 258         struct dwc3                     *dwc = dep->dwc;
 259
 260         dwc3_ep0_stall_and_restart(dwc);
 261
 262         return 0;
 263 }
 264
 265 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 266 {
 267         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 268         struct dwc3                     *dwc = dep->dwc;
 269         unsigned long                   flags;
 270         int                             ret;
 271
 272         spin_lock_irqsave(&dwc->lock, flags);
 273         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 274         spin_unlock_irqrestore(&dwc->lock, flags);
 275
 276         return ret;
 277 }
 278
 279 void dwc3_ep0_out_start(struct dwc3 *dwc)
 280 {
 281         struct dwc3_ep                  *dep;
 282         int                             ret;
 283         int                             i;
 284
 285         complete(&dwc->ep0_in_setup);
 286
 287         dep = dwc->eps[0];
 288         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 289                         DWC3_TRBCTL_CONTROL_SETUP, false);
 290         ret = dwc3_ep0_start_trans(dep);
 291         WARN_ON(ret < 0);
 292         for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
 293                 struct dwc3_ep *dwc3_ep;
 294
 295                 dwc3_ep = dwc->eps[i];
 296                 if (!dwc3_ep)
 297                         continue;
 298
 299                 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
 300                         continue;
 301
 302                 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
 303                 if (dwc->connected)
 304                         dwc3_stop_active_transfer(dwc3_ep, true, true);
 305                 else
 306                         dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
 307         }
 308 }
 309
 310 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 311 {
 312         struct dwc3_ep          *dep;
 313         u32                     windex = le16_to_cpu(wIndex_le);
 314         u32                     epnum;
 315
 316         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 317         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 318                 epnum |= 1;
 319
 320         dep = dwc->eps[epnum];
 321         if (dep == NULL)
 322                 return NULL;
 323
 324         if (dep->flags & DWC3_EP_ENABLED)
 325                 return dep;
 326
 327         return NULL;
 328 }
 329
 330 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 331 {
 332 }
 333 /*
 334  * ch 9.4.5
 335  */
 336 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 337                 struct usb_ctrlrequest *ctrl)
 338 {
 339         struct dwc3_ep          *dep;
 340         u32                     recip;
 341         u32                     value;
 342         u32                     reg;
 343         u16                     usb_status = 0;
 344         __le16                  *response_pkt;
 345
 346         /* We don't support PTM_STATUS */
 347         value = le16_to_cpu(ctrl->wValue);
 348         if (value != 0)
 349                 return -EINVAL;
 350
 351         recip = ctrl->bRequestType & USB_RECIP_MASK;
 352         switch (recip) {
 353         case USB_RECIP_DEVICE:
 354                 /*
 355                  * LTM will be set once we know how to set this in HW.
 356                  */
 357                 usb_status |= dwc->gadget->is_selfpowered;
 358
 359                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 360                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 361                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 362                         if (reg & DWC3_DCTL_INITU1ENA)
 363                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 364                         if (reg & DWC3_DCTL_INITU2ENA)
 365                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 366                 } else {
 367                         usb_status |= dwc->gadget->wakeup_armed <<
 368                                         USB_DEVICE_REMOTE_WAKEUP;
 369                 }
 370
 371                 break;
 372
 373         case USB_RECIP_INTERFACE:
 374                 /*
 375                  * Function Remote Wake Capable D0
 376                  * Function Remote Wakeup       D1
 377                  */
 378                 return dwc3_ep0_delegate_req(dwc, ctrl);
 379
 380         case USB_RECIP_ENDPOINT:
 381                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 382                 if (!dep)
 383                         return -EINVAL;
 384
 385                 if (dep->flags & DWC3_EP_STALL)
 386                         usb_status = 1 << USB_ENDPOINT_HALT;
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391
 392         response_pkt = (__le16 *) dwc->setup_buf;
 393         *response_pkt = cpu_to_le16(usb_status);
 394
 395         dep = dwc->eps[0];
 396         dwc->ep0_usb_req.dep = dep;
 397         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 398         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 399         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 400
 401         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 402 }
 403
 404 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 405                 int set)
 406 {
 407         u32 reg;
 408
 409         if (state != USB_STATE_CONFIGURED)
 410                 return -EINVAL;
 411         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 412                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 413                 return -EINVAL;
 414         if (set && dwc->dis_u1_entry_quirk)
 415                 return -EINVAL;
 416
 417         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 418         if (set)
 419                 reg |= DWC3_DCTL_INITU1ENA;
 420         else
 421                 reg &= ~DWC3_DCTL_INITU1ENA;
 422         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 423
 424         return 0;
 425 }
 426
 427 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 428                 int set)
 429 {
 430         u32 reg;
 431
 432
 433         if (state != USB_STATE_CONFIGURED)
 434                 return -EINVAL;
 435         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 436                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 437                 return -EINVAL;
 438         if (set && dwc->dis_u2_entry_quirk)
 439                 return -EINVAL;
 440
 441         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 442         if (set)
 443                 reg |= DWC3_DCTL_INITU2ENA;
 444         else
 445                 reg &= ~DWC3_DCTL_INITU2ENA;
 446         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 447
 448         return 0;
 449 }
 450
 451 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 452                 u32 wIndex, int set)
 453 {
 454         if ((wIndex & 0xff) != 0)
 455                 return -EINVAL;
 456         if (!set)
 457                 return -EINVAL;
 458
 459         switch (wIndex >> 8) {
 460         case USB_TEST_J:
 461         case USB_TEST_K:
 462         case USB_TEST_SE0_NAK:
 463         case USB_TEST_PACKET:
 464         case USB_TEST_FORCE_ENABLE:
 465                 dwc->test_mode_nr = wIndex >> 8;
 466                 dwc->test_mode = true;
 467                 break;
 468         default:
 469                 return -EINVAL;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 476                 struct usb_ctrlrequest *ctrl, int set)
 477 {
 478         enum usb_device_state   state;
 479         u32                     wValue;
 480         u32                     wIndex;
 481         int                     ret = 0;
 482
 483         wValue = le16_to_cpu(ctrl->wValue);
 484         wIndex = le16_to_cpu(ctrl->wIndex);
 485         state = dwc->gadget->state;
 486
 487         switch (wValue) {
 488         case USB_DEVICE_REMOTE_WAKEUP:
 489                 if (dwc->wakeup_configured)
 490                         dwc->gadget->wakeup_armed = set;
 491                 else
 492                         ret = -EINVAL;
 493                 break;
 494         /*
 495          * 9.4.1 says only for SS, in AddressState only for
 496          * default control pipe
 497          */
 498         case USB_DEVICE_U1_ENABLE:
 499                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 500                 break;
 501         case USB_DEVICE_U2_ENABLE:
 502                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 503                 break;
 504         case USB_DEVICE_LTM_ENABLE:
 505                 ret = -EINVAL;
 506                 break;
 507         case USB_DEVICE_TEST_MODE:
 508                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 509                 break;
 510         default:
 511                 ret = -EINVAL;
 512         }
 513
 514         return ret;
 515 }
 516
 517 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 518                 struct usb_ctrlrequest *ctrl, int set)
 519 {
 520         u32                     wValue;
 521         int                     ret = 0;
 522
 523         wValue = le16_to_cpu(ctrl->wValue);
 524
 525         switch (wValue) {
 526         case USB_INTRF_FUNC_SUSPEND:
 527                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 528                 break;
 529         default:
 530                 ret = -EINVAL;
 531         }
 532
 533         return ret;
 534 }
 535
 536 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 537                 struct usb_ctrlrequest *ctrl, int set)
 538 {
 539         struct dwc3_ep          *dep;
 540         u32                     wValue;
 541         int                     ret;
 542
 543         wValue = le16_to_cpu(ctrl->wValue);
 544
 545         switch (wValue) {
 546         case USB_ENDPOINT_HALT:
 547                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 548                 if (!dep)
 549                         return -EINVAL;
 550
 551                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 552                         break;
 553
 554                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 555                 if (ret)
 556                         return -EINVAL;
 557
 558                 /* ClearFeature(Halt) may need delayed status */
 559                 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 560                         return USB_GADGET_DELAYED_STATUS;
 561
 562                 break;
 563         default:
 564                 return -EINVAL;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 571                 struct usb_ctrlrequest *ctrl, int set)
 572 {
 573         u32                     recip;
 574         int                     ret;
 575
 576         recip = ctrl->bRequestType & USB_RECIP_MASK;
 577
 578         switch (recip) {
 579         case USB_RECIP_DEVICE:
 580                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 581                 break;
 582         case USB_RECIP_INTERFACE:
 583                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 584                 break;
 585         case USB_RECIP_ENDPOINT:
 586                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 587                 break;
 588         default:
 589                 ret = -EINVAL;
 590         }
 591
 592         return ret;
 593 }
 594
 595 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 596 {
 597         enum usb_device_state state = dwc->gadget->state;
 598         u32 addr;
 599         u32 reg;
 600
 601         addr = le16_to_cpu(ctrl->wValue);
 602         if (addr > 127) {
 603                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 604                 return -EINVAL;
 605         }
 606
 607         if (state == USB_STATE_CONFIGURED) {
 608                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 609                 return -EINVAL;
 610         }
 611
 612         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 613         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 614         reg |= DWC3_DCFG_DEVADDR(addr);
 615         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 616
 617         if (addr)
 618                 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 619         else
 620                 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 621
 622         return 0;
 623 }
 624
 625 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 626 {
 627         int ret = -EINVAL;
 628
 629         if (dwc->async_callbacks) {
 630                 spin_unlock(&dwc->lock);
 631                 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 632                 spin_lock(&dwc->lock);
 633         }
 634         return ret;
 635 }
 636
 637 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 638 {
 639         enum usb_device_state state = dwc->gadget->state;
 640         u32 cfg;
 641         int ret;
 642         u32 reg;
 643
 644         cfg = le16_to_cpu(ctrl->wValue);
 645
 646         switch (state) {
 647         case USB_STATE_DEFAULT:
 648                 return -EINVAL;
 649
 650         case USB_STATE_ADDRESS:
 651                 dwc3_gadget_start_config(dwc, 2);
 652                 dwc3_gadget_clear_tx_fifos(dwc);
 653
 654                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 655                 /* if the cfg matches and the cfg is non zero */
 656                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 657
 658                         /*
 659                          * only change state if set_config has already
 660                          * been processed. If gadget driver returns
 661                          * USB_GADGET_DELAYED_STATUS, we will wait
 662                          * to change the state on the next usb_ep_queue()
 663                          */
 664                         if (ret == 0)
 665                                 usb_gadget_set_state(dwc->gadget,
 666                                                 USB_STATE_CONFIGURED);
 667
 668                         /*
 669                          * Enable transition to U1/U2 state when
 670                          * nothing is pending from application.
 671                          */
 672                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 673                         if (!dwc->dis_u1_entry_quirk)
 674                                 reg |= DWC3_DCTL_ACCEPTU1ENA;
 675                         if (!dwc->dis_u2_entry_quirk)
 676                                 reg |= DWC3_DCTL_ACCEPTU2ENA;
 677                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 678                 }
 679                 break;
 680
 681         case USB_STATE_CONFIGURED:
 682                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 683                 if (!cfg && !ret)
 684                         usb_gadget_set_state(dwc->gadget,
 685                                         USB_STATE_ADDRESS);
 686                 break;
 687         default:
 688                 ret = -EINVAL;
 689         }
 690         return ret;
 691 }
 692
 693 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 694 {
 695         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 696         struct dwc3     *dwc = dep->dwc;
 697
 698         u32             param = 0;
 699         u32             reg;
 700
 701         struct timing {
 702                 u8      u1sel;
 703                 u8      u1pel;
 704                 __le16  u2sel;
 705                 __le16  u2pel;
 706         } __packed timing;
 707
 708         int             ret;
 709
 710         memcpy(&timing, req->buf, sizeof(timing));
 711
 712         dwc->u1sel = timing.u1sel;
 713         dwc->u1pel = timing.u1pel;
 714         dwc->u2sel = le16_to_cpu(timing.u2sel);
 715         dwc->u2pel = le16_to_cpu(timing.u2pel);
 716
 717         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 718         if (reg & DWC3_DCTL_INITU2ENA)
 719                 param = dwc->u2pel;
 720         if (reg & DWC3_DCTL_INITU1ENA)
 721                 param = dwc->u1pel;
 722
 723         /*
 724          * According to Synopsys Databook, if parameter is
 725          * greater than 125, a value of zero should be
 726          * programmed in the register.
 727          */
 728         if (param > 125)
 729                 param = 0;
 730
 731         /* now that we have the time, issue DGCMD Set Sel */
 732         ret = dwc3_send_gadget_generic_command(dwc,
 733                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 734         WARN_ON(ret < 0);
 735 }
 736
 737 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 738 {
 739         struct dwc3_ep  *dep;
 740         enum usb_device_state state = dwc->gadget->state;
 741         u16             wLength;
 742
 743         if (state == USB_STATE_DEFAULT)
 744                 return -EINVAL;
 745
 746         wLength = le16_to_cpu(ctrl->wLength);
 747
 748         if (wLength != 6) {
 749                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 750                                 wLength);
 751                 return -EINVAL;
 752         }
 753
 754         /*
 755          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 756          * queue a usb_request for 6 bytes.
 757          *
 758          * Remember, though, this controller can't handle non-wMaxPacketSize
 759          * aligned transfers on the OUT direction, so we queue a request for
 760          * wMaxPacketSize instead.
 761          */
 762         dep = dwc->eps[0];
 763         dwc->ep0_usb_req.dep = dep;
 764         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 765         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 766         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 767
 768         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 769 }
 770
 771 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 772 {
 773         u16             wLength;
 774         u16             wValue;
 775         u16             wIndex;
 776
 777         wValue = le16_to_cpu(ctrl->wValue);
 778         wLength = le16_to_cpu(ctrl->wLength);
 779         wIndex = le16_to_cpu(ctrl->wIndex);
 780
 781         if (wIndex || wLength)
 782                 return -EINVAL;
 783
 784         dwc->gadget->isoch_delay = wValue;
 785
 786         return 0;
 787 }
 788
 789 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 790 {
 791         int ret;
 792
 793         switch (ctrl->bRequest) {
 794         case USB_REQ_GET_STATUS:
 795                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 796                 break;
 797         case USB_REQ_CLEAR_FEATURE:
 798                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 799                 break;
 800         case USB_REQ_SET_FEATURE:
 801                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 802                 break;
 803         case USB_REQ_SET_ADDRESS:
 804                 ret = dwc3_ep0_set_address(dwc, ctrl);
 805                 break;
 806         case USB_REQ_SET_CONFIGURATION:
 807                 ret = dwc3_ep0_set_config(dwc, ctrl);
 808                 break;
 809         case USB_REQ_SET_SEL:
 810                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 811                 break;
 812         case USB_REQ_SET_ISOCH_DELAY:
 813                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 814                 break;
 815         default:
 816                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 817                 break;
 818         }
 819
 820         return ret;
 821 }
 822
 823 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 824                 const struct dwc3_event_depevt *event)
 825 {
 826         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 827         int ret = -EINVAL;
 828         u32 len;
 829
 830         if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
 831                 goto out;
 832
 833         trace_dwc3_ctrl_req(ctrl);
 834
 835         len = le16_to_cpu(ctrl->wLength);
 836         if (!len) {
 837                 dwc->three_stage_setup = false;
 838                 dwc->ep0_expect_in = false;
 839                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 840         } else {
 841                 dwc->three_stage_setup = true;
 842                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 843                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 844         }
 845
 846         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 847                 ret = dwc3_ep0_std_request(dwc, ctrl);
 848         else
 849                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 850
 851         if (ret == USB_GADGET_DELAYED_STATUS)
 852                 dwc->delayed_status = true;
 853
 854 out:
 855         if (ret < 0)
 856                 dwc3_ep0_stall_and_restart(dwc);
 857 }
 858
 859 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 860                 const struct dwc3_event_depevt *event)
 861 {
 862         struct dwc3_request     *r;
 863         struct usb_request      *ur;
 864         struct dwc3_trb         *trb;
 865         struct dwc3_ep          *ep0;
 866         u32                     transferred = 0;
 867         u32                     status;
 868         u32                     length;
 869         u8                      epnum;
 870
 871         epnum = event->endpoint_number;
 872         ep0 = dwc->eps[0];
 873
 874         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 875         trb = dwc->ep0_trb;
 876         trace_dwc3_complete_trb(ep0, trb);
 877
 878         r = next_request(&ep0->pending_list);
 879         if (!r)
 880                 return;
 881
 882         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 883         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 884                 dwc->setup_packet_pending = true;
 885                 if (r)
 886                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 887
 888                 return;
 889         }
 890
 891         ur = &r->request;
 892
 893         length = trb->size & DWC3_TRB_SIZE_MASK;
 894         transferred = ur->length - length;
 895         ur->actual += transferred;
 896
 897         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 898              ur->length && ur->zero) || dwc->ep0_bounced) {
 899                 trb++;
 900                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 901                 trace_dwc3_complete_trb(ep0, trb);
 902
 903                 if (r->direction)
 904                         dwc->eps[1]->trb_enqueue = 0;
 905                 else
 906                         dwc->eps[0]->trb_enqueue = 0;
 907
 908                 dwc->ep0_bounced = false;
 909         }
 910
 911         if ((epnum & 1) && ur->actual < ur->length)
 912                 dwc3_ep0_stall_and_restart(dwc);
 913         else
 914                 dwc3_gadget_giveback(ep0, r, 0);
 915 }
 916
 917 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 918                 const struct dwc3_event_depevt *event)
 919 {
 920         struct dwc3_request     *r;
 921         struct dwc3_ep          *dep;
 922         struct dwc3_trb         *trb;
 923         u32                     status;
 924
 925         dep = dwc->eps[0];
 926         trb = dwc->ep0_trb;
 927
 928         trace_dwc3_complete_trb(dep, trb);
 929
 930         if (!list_empty(&dep->pending_list)) {
 931                 r = next_request(&dep->pending_list);
 932
 933                 dwc3_gadget_giveback(dep, r, 0);
 934         }
 935
 936         if (dwc->test_mode) {
 937                 int ret;
 938
 939                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 940                 if (ret < 0) {
 941                         dev_err(dwc->dev, "invalid test #%d\n",
 942                                         dwc->test_mode_nr);
 943                         dwc3_ep0_stall_and_restart(dwc);
 944                         return;
 945                 }
 946         }
 947
 948         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 949         if (status == DWC3_TRBSTS_SETUP_PENDING)
 950                 dwc->setup_packet_pending = true;
 951
 952         dwc->ep0state = EP0_SETUP_PHASE;
 953         dwc3_ep0_out_start(dwc);
 954 }
 955
 956 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 957                         const struct dwc3_event_depevt *event)
 958 {
 959         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 960
 961         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 962         dep->resource_index = 0;
 963         dwc->setup_packet_pending = false;
 964
 965         switch (dwc->ep0state) {
 966         case EP0_SETUP_PHASE:
 967                 dwc3_ep0_inspect_setup(dwc, event);
 968                 break;
 969
 970         case EP0_DATA_PHASE:
 971                 dwc3_ep0_complete_data(dwc, event);
 972                 break;
 973
 974         case EP0_STATUS_PHASE:
 975                 dwc3_ep0_complete_status(dwc, event);
 976                 break;
 977         default:
 978                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 979         }
 980 }
 981
 982 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 983                 struct dwc3_ep *dep, struct dwc3_request *req)
 984 {
 985         unsigned int            trb_length = 0;
 986         int                     ret;
 987
 988         req->direction = !!dep->number;
 989
 990         if (req->request.length == 0) {
 991                 if (!req->direction)
 992                         trb_length = dep->endpoint.maxpacket;
 993
 994                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 995                                 DWC3_TRBCTL_CONTROL_DATA, false);
 996                 ret = dwc3_ep0_start_trans(dep);
 997         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 998                         && (dep->number == 0)) {
 999                 u32     maxpacket;
1000                 u32     rem;
1001
1002                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1003                                 &req->request, dep->number);
1004                 if (ret)
1005                         return;
1006
1007                 maxpacket = dep->endpoint.maxpacket;
1008                 rem = req->request.length % maxpacket;
1009                 dwc->ep0_bounced = true;
1010
1011                 /* prepare normal TRB */
1012                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1013                                          req->request.length,
1014                                          DWC3_TRBCTL_CONTROL_DATA,
1015                                          true);
1016
1017                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1018
1019                 /* Now prepare one extra TRB to align transfer size */
1020                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1021                                          maxpacket - rem,
1022                                          DWC3_TRBCTL_CONTROL_DATA,
1023                                          false);
1024                 ret = dwc3_ep0_start_trans(dep);
1025         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1026                    req->request.length && req->request.zero) {
1027
1028                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1029                                 &req->request, dep->number);
1030                 if (ret)
1031                         return;
1032
1033                 /* prepare normal TRB */
1034                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1035                                          req->request.length,
1036                                          DWC3_TRBCTL_CONTROL_DATA,
1037                                          true);
1038
1039                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1040
1041                 if (!req->direction)
1042                         trb_length = dep->endpoint.maxpacket;
1043
1044                 /* Now prepare one extra TRB to align transfer size */
1045                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1046                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1047                                          false);
1048                 ret = dwc3_ep0_start_trans(dep);
1049         } else {
1050                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1051                                 &req->request, dep->number);
1052                 if (ret)
1053                         return;
1054
1055                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1056                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1057                                 false);
1058
1059                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1060
1061                 ret = dwc3_ep0_start_trans(dep);
1062         }
1063
1064         WARN_ON(ret < 0);
1065 }
1066
1067 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1068 {
1069         struct dwc3             *dwc = dep->dwc;
1070         u32                     type;
1071
1072         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1073                 : DWC3_TRBCTL_CONTROL_STATUS2;
1074
1075         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1076         return dwc3_ep0_start_trans(dep);
1077 }
1078
1079 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1080 {
1081         WARN_ON(dwc3_ep0_start_control_status(dep));
1082 }
1083
1084 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1085                 const struct dwc3_event_depevt *event)
1086 {
1087         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1088
1089         __dwc3_ep0_do_control_status(dwc, dep);
1090 }
1091
1092 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1093 {
1094         unsigned int direction = !dwc->ep0_expect_in;
1095
1096         dwc->delayed_status = false;
1097         dwc->clear_stall_protocol = 0;
1098
1099         if (dwc->ep0state != EP0_STATUS_PHASE)
1100                 return;
1101
1102         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1103 }
1104
1105 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1106 {
1107         struct dwc3_gadget_ep_cmd_params params;
1108         u32                     cmd;
1109         int                     ret;
1110
1111         /*
1112          * For status/DATA OUT stage, TRB will be queued on ep0 out
1113          * endpoint for which resource index is zero. Hence allow
1114          * queuing ENDXFER command for ep0 out endpoint.
1115          */
1116         if (!dep->resource_index && dep->number)
1117                 return;
1118
1119         cmd = DWC3_DEPCMD_ENDTRANSFER;
1120         cmd |= DWC3_DEPCMD_CMDIOC;
1121         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1122         memset(&params, 0, sizeof(params));
1123         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1124         WARN_ON_ONCE(ret);
1125         dep->resource_index = 0;
1126 }
1127
1128 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1129                 const struct dwc3_event_depevt *event)
1130 {
1131         switch (event->status) {
1132         case DEPEVT_STATUS_CONTROL_DATA:
1133                 if (!dwc->softconnect || !dwc->connected)
1134                         return;
1135                 /*
1136                  * We already have a DATA transfer in the controller's cache,
1137                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1138                  * it's for the wrong direction.
1139                  *
1140                  * In that case, we must issue END_TRANSFER command to the Data
1141                  * Phase we already have started and issue SetStall on the
1142                  * control endpoint.
1143                  */
1144                 if (dwc->ep0_expect_in != event->endpoint_number) {
1145                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1146
1147                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1148                         dwc3_ep0_end_control_data(dwc, dep);
1149                         dwc3_ep0_stall_and_restart(dwc);
1150                         return;
1151                 }
1152
1153                 break;
1154
1155         case DEPEVT_STATUS_CONTROL_STATUS:
1156                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1157                         return;
1158
1159                 if (dwc->setup_packet_pending) {
1160                         dwc3_ep0_stall_and_restart(dwc);
1161                         return;
1162                 }
1163
1164                 dwc->ep0state = EP0_STATUS_PHASE;
1165
1166                 if (dwc->delayed_status) {
1167                         struct dwc3_ep *dep = dwc->eps[0];
1168
1169                         WARN_ON_ONCE(event->endpoint_number != 1);
1170                         /*
1171                          * We should handle the delay STATUS phase here if the
1172                          * request for handling delay STATUS has been queued
1173                          * into the list.
1174                          */
1175                         if (!list_empty(&dep->pending_list)) {
1176                                 dwc->delayed_status = false;
1177                                 usb_gadget_set_state(dwc->gadget,
1178                                                      USB_STATE_CONFIGURED);
1179                                 dwc3_ep0_do_control_status(dwc, event);
1180                         }
1181
1182                         return;
1183                 }
1184
1185                 dwc3_ep0_do_control_status(dwc, event);
1186         }
1187 }
1188
1189 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1190                 const struct dwc3_event_depevt *event)
1191 {
1192         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1193         u8              cmd;
1194
1195         switch (event->endpoint_event) {
1196         case DWC3_DEPEVT_XFERCOMPLETE:
1197                 dwc3_ep0_xfer_complete(dwc, event);
1198                 break;
1199
1200         case DWC3_DEPEVT_XFERNOTREADY:
1201                 dwc3_ep0_xfernotready(dwc, event);
1202                 break;
1203
1204         case DWC3_DEPEVT_XFERINPROGRESS:
1205         case DWC3_DEPEVT_RXTXFIFOEVT:
1206         case DWC3_DEPEVT_STREAMEVT:
1207                 break;
1208         case DWC3_DEPEVT_EPCMDCMPLT:
1209                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1210
1211                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1212                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1213                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1214                 }
1215                 break;
1216         default:
1217                 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
1218                 break;
1219         }
1220 }