3 * Shared header file for the Linux user-space API for
4 * Linear Systems Ltd. DVB Master ASI interface boards.
6 * Copyright (C) 1999 Tony Bolger <d7v@indigo.ie>
7 * Copyright (C) 2000-2008 Linear Systems Ltd.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of Linear Systems Ltd. nor the names of its
20 * contributors may be used to endorse or promote products derived from
21 * this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY LINEAR SYSTEMS LTD. "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL LINEAR SYSTEMS LTD. OR CONTRIBUTORS
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
33 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Linear Systems can be contacted at <http://www.linsys.ca/>.
43 #define ASI_DRIVER_NAME "asi"
45 #define ASI_MAJOR 61 /* Set to 0 for dynamic allocation.
46 * Otherwise, 61 is available.
47 * See /usr/src/linux/Documentation/devices.txt */
49 #define ASI_TX_BUFFERS_MIN 2 /* This must be at least 2 */
50 /* The minimum transmit buffer size must be positive, divisible by 8,
51 * and large enough that the buffers aren't transferred to the onboard FIFOs
52 * too quickly for the machine to handle the interrupts.
53 * This is especially a problem at startup, when the FIFOs are empty.
54 * Relevant factors include onboard FIFO size, PCI bus throughput,
55 * processor speed, and interrupt latency. */
56 #define ASI_TX_BUFSIZE_MIN 1024
57 #define ASI_RX_BUFFERS_MIN 2 /* This must be at least 2 */
58 #define ASI_RX_BUFSIZE_MIN 8 /* This must be positive and divisible by 8 */
60 #define ASI_TX_BUFFERS 54 /* This must be at least 2 */
61 #define ASI_TX_BUFSIZE 38352 /* This must be positive and divisible by 8 */
62 #define ASI_RX_BUFFERS 54 /* This must be at least 2 */
63 #define ASI_RX_BUFSIZE 38352 /* This must be positive and divisible by 8 */
65 /* Ioctl () definitions */
66 #define ASI_IOC_MAGIC '?' /* This ioctl magic number is currently free. See
67 * /usr/src/linux/Documentation/ioctl-number.txt */
69 #define ASI_IOC_TXGETCAP _IOR(ASI_IOC_MAGIC, 1, unsigned int)
70 #define ASI_IOC_TXGETEVENTS _IOR(ASI_IOC_MAGIC, 2, unsigned int)
71 #define ASI_IOC_TXGETBUFLEVEL _IOR(ASI_IOC_MAGIC, 3, unsigned int)
72 #define ASI_IOC_TXSETSTUFFING _IOW(ASI_IOC_MAGIC, 4, struct asi_txstuffing)
73 #define ASI_IOC_TXGETBYTECOUNT _IOR(ASI_IOC_MAGIC, 5, unsigned int)
74 /* #define ASI_IOC_TXGETFIFO _IOR(ASI_IOC_MAGIC, 6, int) */
75 #define ASI_IOC_TXGETTXD _IOR(ASI_IOC_MAGIC, 7, int)
76 #define ASI_IOC_TXGET27COUNT _IOR(ASI_IOC_MAGIC, 8, unsigned int)
77 #define ASI_IOC_TXSETPID _IOR(ASI_IOC_MAGIC, 9, unsigned int)
78 #define ASI_IOC_TXGETPCRSTAMP _IOR(ASI_IOC_MAGIC, 10, struct asi_pcrstamp)
79 #define ASI_IOC_TXCHANGENEXTIP _IOR(ASI_IOC_MAGIC, 11, int)
81 #define ASI_IOC_RXGETCAP _IOR(ASI_IOC_MAGIC, 65, unsigned int)
82 #define ASI_IOC_RXGETEVENTS _IOR(ASI_IOC_MAGIC, 66, unsigned int)
83 #define ASI_IOC_RXGETBUFLEVEL _IOR(ASI_IOC_MAGIC, 67, unsigned int)
84 /* #define ASI_IOC_RXSETREFRAME _IOW(ASI_IOC_MAGIC, 68, int) */
85 #define ASI_IOC_RXGETSTATUS _IOR(ASI_IOC_MAGIC, 69, int)
86 #define ASI_IOC_RXGETBYTECOUNT _IOR(ASI_IOC_MAGIC, 70, unsigned int)
87 /* #define ASI_IOC_RXGETFIFO _IOR(ASI_IOC_MAGIC, 71, int) */
88 #define ASI_IOC_RXSETINVSYNC _IOW(ASI_IOC_MAGIC, 72, int)
89 #define ASI_IOC_RXGETCARRIER _IOR(ASI_IOC_MAGIC, 73, int)
90 #define ASI_IOC_RXSETDSYNC _IOW(ASI_IOC_MAGIC, 74, int)
91 #define ASI_IOC_RXGETRXD _IOR(ASI_IOC_MAGIC, 75, int)
92 #define ASI_IOC_RXSETPF _IOW(ASI_IOC_MAGIC, 76, unsigned int [256])
93 /* #define ASI_IOC_RXSETPFE _IOW(ASI_IOC_MAGIC, 77, int) */
94 #define ASI_IOC_RXSETPID0 _IOW(ASI_IOC_MAGIC, 78, int)
95 #define ASI_IOC_RXGETPID0COUNT _IOR(ASI_IOC_MAGIC, 79, unsigned int)
96 #define ASI_IOC_RXSETPID1 _IOW(ASI_IOC_MAGIC, 80, int)
97 #define ASI_IOC_RXGETPID1COUNT _IOR(ASI_IOC_MAGIC, 81, unsigned int)
98 #define ASI_IOC_RXSETPID2 _IOW(ASI_IOC_MAGIC, 82, int)
99 #define ASI_IOC_RXGETPID2COUNT _IOR(ASI_IOC_MAGIC, 83, unsigned int)
100 #define ASI_IOC_RXSETPID3 _IOW(ASI_IOC_MAGIC, 84, int)
101 #define ASI_IOC_RXGETPID3COUNT _IOR(ASI_IOC_MAGIC, 85, unsigned int)
102 /* #define ASI_IOC_RXGETSTAMP _IOR(ASI_IOC_MAGIC, 86, unsigned int) */
103 #define ASI_IOC_RXGET27COUNT _IOR(ASI_IOC_MAGIC, 87, unsigned int)
104 #define ASI_IOC_RXGETSTATUS2 _IOR(ASI_IOC_MAGIC, 88, int)
105 #define ASI_IOC_RXSETINPUT _IOR(ASI_IOC_MAGIC, 89, int)
106 #define ASI_IOC_RXGETRXD2 _IOR(ASI_IOC_MAGIC, 90, int)
108 #define ASI_IOC_GETID _IOR(ASI_IOC_MAGIC, 129, unsigned int)
109 #define ASI_IOC_GETVERSION _IOR(ASI_IOC_MAGIC, 130, unsigned int)
111 /* Transmitter event flag bit locations */
112 #define ASI_EVENT_TX_BUFFER_ORDER 0
113 #define ASI_EVENT_TX_BUFFER (1 << ASI_EVENT_TX_BUFFER_ORDER)
114 #define ASI_EVENT_TX_FIFO_ORDER 1
115 #define ASI_EVENT_TX_FIFO (1 << ASI_EVENT_TX_FIFO_ORDER)
116 #define ASI_EVENT_TX_DATA_ORDER 2
117 #define ASI_EVENT_TX_DATA (1 << ASI_EVENT_TX_DATA_ORDER)
119 /* Receiver event flag bit locations */
120 #define ASI_EVENT_RX_BUFFER_ORDER 0
121 #define ASI_EVENT_RX_BUFFER (1 << ASI_EVENT_RX_BUFFER_ORDER)
122 #define ASI_EVENT_RX_FIFO_ORDER 1
123 #define ASI_EVENT_RX_FIFO (1 << ASI_EVENT_RX_FIFO_ORDER)
124 #define ASI_EVENT_RX_CARRIER_ORDER 2
125 #define ASI_EVENT_RX_CARRIER (1 << ASI_EVENT_RX_CARRIER_ORDER)
126 #define ASI_EVENT_RX_AOS_ORDER 3
127 #define ASI_EVENT_RX_AOS (1 << ASI_EVENT_RX_AOS_ORDER)
128 #define ASI_EVENT_RX_LOS_ORDER 4
129 #define ASI_EVENT_RX_LOS (1 << ASI_EVENT_RX_LOS_ORDER)
130 #define ASI_EVENT_RX_DATA_ORDER 5
131 #define ASI_EVENT_RX_DATA (1 << ASI_EVENT_RX_DATA_ORDER)
134 * asi_txstuffing - Transmitter stuffing parameters
135 * @ib: interbyte stuffing
136 * @ip: interpacket stuffing
142 struct asi_txstuffing
{
143 /* Number of K28.5 characters to insert between packet bytes */
146 /* Base number of K28.5 characters to insert between packets,
147 * not including the two required by ASI */
150 /* Number of packets with (ip) bytes of interpacket stuffing
151 * per finetuning cycle */
152 unsigned int normal_ip
;
154 /* Number of packets with (ip + 1) bytes of interpacket stuffing
155 * per finetuning cycle */
158 /* Number of packets with (ip) bytes of interpacket stuffing
159 * per interleaved finetuning cycle */
160 unsigned int il_normal
;
162 /* Number of packets with (ip + 1) bytes of interpacket stuffing
163 * per interleaved finetuning cycle */
168 * asi_pcrstamp - PCR - departure time pair
169 * @adaptation_field_length: adaptation field length
170 * @adaptation_field_flags: adaptation field flags
171 * @PCR: a program clock reference
172 * @count: departure time of this PCR, in 1 / 27 MHz
174 struct asi_pcrstamp
{
175 unsigned char adaptation_field_length
;
176 unsigned char adaptation_field_flags
;
177 unsigned char PCR
[6];
181 /* Interface capabilities */
182 #define ASI_CAP_TX_MAKE204 0x00000004
183 #define ASI_CAP_TX_FINETUNING 0x00000008
184 #define ASI_CAP_TX_BYTECOUNTER 0x00000010
185 #define ASI_CAP_TX_SETCLKSRC 0x00000020
186 #define ASI_CAP_TX_FIFOUNDERRUN 0x00000040
187 #define ASI_CAP_TX_LARGEIB 0x00000080
188 #define ASI_CAP_TX_INTERLEAVING 0x00000100
189 #define ASI_CAP_TX_DATA 0x00000200
190 #define ASI_CAP_TX_RXCLKSRC 0x00000400
191 /* #define ASI_CAP_TX_COMPOSITEREF 0x00000800 */
192 #define ASI_CAP_TX_PCRSTAMP 0x00001000
193 #define ASI_CAP_TX_CHANGENEXTIP 0x00002000
194 #define ASI_CAP_TX_27COUNTER 0x00004000
195 #define ASI_CAP_TX_BYTESOR27 0x00008000
196 #define ASI_CAP_TX_TIMESTAMPS 0x00010000
197 #define ASI_CAP_TX_PTIMESTAMPS 0x00020000
198 #define ASI_CAP_TX_NULLPACKETS 0x00040000
200 #define ASI_CAP_RX_SYNC 0x00000004
201 #define ASI_CAP_RX_MAKE188 0x00000008
202 #define ASI_CAP_RX_BYTECOUNTER 0x00000010
203 /* #define ASI_CAP_RX_FIFOSTATUS 0x00000020 */
204 #define ASI_CAP_RX_INVSYNC 0x00000040
205 #define ASI_CAP_RX_CD 0x00000080
206 #define ASI_CAP_RX_DSYNC 0x00000100
207 #define ASI_CAP_RX_DATA 0x00000200
208 #define ASI_CAP_RX_PIDFILTER 0x00000400
209 #define ASI_CAP_RX_PIDCOUNTER 0x00000800
210 #define ASI_CAP_RX_4PIDCOUNTER 0x00001000
211 #define ASI_CAP_RX_FORCEDMA 0x00002000
212 #define ASI_CAP_RX_27COUNTER 0x00004000
213 #define ASI_CAP_RX_BYTESOR27 0x00008000
214 #define ASI_CAP_RX_TIMESTAMPS 0x00010000
215 #define ASI_CAP_RX_PTIMESTAMPS 0x00020000
216 #define ASI_CAP_RX_NULLPACKETS 0x00040000
217 #define ASI_CAP_RX_REDUNDANT 0x00080000
218 #define ASI_CAP_RX_DATA2 0x00100000
220 /* Transmitter clock source settings */
221 #define ASI_CTL_TX_CLKSRC_ONBOARD 0
222 #define ASI_CTL_TX_CLKSRC_EXT 1
223 #define ASI_CTL_TX_CLKSRC_RX 2
224 /* #define ASI_CTL_TX_CLKSRC_EXT_PAL 3 */
226 /* Transmitter mode settings */
227 #define ASI_CTL_TX_MODE_188 0
228 #define ASI_CTL_TX_MODE_204 1
229 #define ASI_CTL_TX_MODE_MAKE204 2
231 /* Receiver mode settings */
232 #define ASI_CTL_RX_MODE_RAW 0
233 #define ASI_CTL_RX_MODE_188 1
234 #define ASI_CTL_RX_MODE_204 2
235 #define ASI_CTL_RX_MODE_AUTO 3
236 #define ASI_CTL_RX_MODE_AUTOMAKE188 4
237 #define ASI_CTL_RX_MODE_204MAKE188 5
239 /* Timestamping settings */
240 #define ASI_CTL_TSTAMP_NONE 0
241 #define ASI_CTL_TSTAMP_APPEND 1
242 #define ASI_CTL_TSTAMP_PREPEND 2
244 /* Transport settings */
245 #define ASI_CTL_TRANSPORT_DVB_ASI 0
246 #define ASI_CTL_TRANSPORT_SMPTE_310M 1