envydis/hwsq.c

   1 /*
   2  * Copyright (C) 2010-2011 Marcelina Kościelnicka <mwk@0x04.net>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "dis-intern.h"
  26
  27 #define F_NV41P 1
  28 #define F_NV17F 2
  29 #define F_NV41F 4
  30
  31 /*
  32  * Immediate fields
  33  */
  34
  35 static struct rbitfield imm16off = { 8, 16 };
  36 #define IMM16 atomrimm, &imm16off
  37 static struct rbitfield imm32off = { 8, 32 };
  38 #define IMM32 atomrimm, &imm32off
  39 static struct bitfield flagoff = { 0, 5 };
  40 #define FLAG atomimm, &flagoff
  41 static struct bitfield waitoff = { 0, 2 };
  42 #define WAIT atomimm, &waitoff
  43 static struct bitfield waitsoff = { 2, 4, .shr = 1 };
  44 #define WAITS atomimm, &waitsoff
  45 static struct bitfield eventoff = { 8, 5 };
  46 #define EVENT atomimm, &eventoff
  47 static struct bitfield evaloff = { 16, 1 };
  48 #define EVAL atomimm, &evaloff
  49
  50 static struct insn tabevent[] = {
  51         { 0x0000, 0xff00, C("FB_PAUSED") },
  52         { 0x0100, 0xff00, C("HEAD0_VBLANK") },
  53         { 0x0200, 0xff00, C("HEAD0_HBLANK") },
  54         { 0x0300, 0xff00, C("HEAD1_VBLANK") },
  55         { 0x0400, 0xff00, C("HEAD1_HBLANK") },
  56         { 0, 0, EVENT },
  57 };
  58
  59 static struct insn tabfl[] = {
  60         { 0x00, 0x1f, C("GPIO_2_OUT"), .fmask = F_NV17F },
  61         { 0x01, 0x1f, C("GPIO_2_OE"), .fmask = F_NV17F },
  62         { 0x02, 0x1f, C("GPIO_3_OUT"), .fmask = F_NV17F },
  63         { 0x03, 0x1f, C("GPIO_3_OE"), .fmask = F_NV17F },
  64         { 0x04, 0x1f, C("PRAMDAC0_UNK880_28"), .fmask = F_NV17F },
  65         { 0x05, 0x1f, C("PRAMDAC1_UNK880_28"), .fmask = F_NV17F },
  66         { 0x06, 0x1f, C("PRAMDAC0_UNK880_29"), .fmask = F_NV17F },
  67         { 0x07, 0x1f, C("PRAMDAC1_UNK880_29"), .fmask = F_NV17F },
  68         { 0x0e, 0x1f, C("GPIO_9_OUT"), .fmask = F_NV17F },
  69         { 0x0f, 0x1f, C("GPIO_9_OE"), .fmask = F_NV17F },
  70         { 0x10, 0x1f, C("FB_PAUSE"), .fmask = F_NV41P },
  71         { 0x19, 0x1f, C("PWM_2_ENABLE"), .fmask = F_NV41F },
  72         { 0x1a, 0x1f, C("PWM_1_ENABLE"), .fmask = F_NV41F },
  73         { 0x1b, 0x1f, C("PWM_0_ENABLE"), .fmask = F_NV17F },
  74         { 0x1c, 0x1f, C("PBUS_DEBUG_1_UNK22"), .fmask = F_NV17F },
  75         { 0x1d, 0x1f, C("PBUS_DEBUG_1_UNK24"), .fmask = F_NV17F },
  76         { 0x1e, 0x1f, C("PBUS_DEBUG_1_UNK26"), .fmask = F_NV17F },
  77         { 0x1f, 0x1f, C("PBUS_DEBUG_1_UNK27"), .fmask = F_NV17F },
  78         { 0, 0, FLAG },
  79 };
  80
  81 static struct insn tabm[] = {
  82         { 0x00, 0xff, OP1B, N("nop") },
  83         { 0x00, 0xc0, OP1B, N("wait"), WAIT, N("shl"), WAITS },
  84         { 0x40, 0xff, OP3B, N("addrlo"), IMM16, .fmask = F_NV41P },
  85         { 0x42, 0xff, OP3B, N("datalo"), IMM16, .fmask = F_NV41P },
  86         { 0x5f, 0xff, OP3B, N("ewait"), T(event), EVAL, .fmask = F_NV41P },
  87         { 0x7f, 0xff, OP1B, N("exit") },
  88         { 0x80, 0xe0, OP1B, N("unset"), T(fl) },
  89         { 0xa0, 0xe0, OP1B, N("set1"), T(fl) },
  90         { 0xc0, 0xe0, OP1B, N("set0"), T(fl) },
  91         { 0xe0, 0xff, OP5B, N("addr"), IMM32, .fmask = F_NV41P },
  92         { 0xe2, 0xff, OP5B, N("data"), IMM32, .fmask = F_NV41P },
  93         { 0, 0, OP1B, OOPS },
  94 };
  95
  96 static void hwsq_prep(struct disisa *isa) {
  97         isa->vardata = vardata_new("hwsq");
  98         int f_nv41op = vardata_add_feature(isa->vardata, "nv41op", "NV41+ features");
  99         int f_nv17f = vardata_add_feature(isa->vardata, "nv17f", "NV17:G80 flags");
 100         int f_nv41f = vardata_add_feature(isa->vardata, "nv41f", "NV41:G80 flags");
 101         if (f_nv41op == -1 || f_nv17f == -1 || f_nv41f == -1)
 102                 abort();
 103         int vs_chipset = vardata_add_varset(isa->vardata, "chipset", "GPU chipset");
 104         if (vs_chipset == -1)
 105                 abort();
 106         int v_nv17 = vardata_add_variant(isa->vardata, "nv17", "NV17:NV41", vs_chipset);
 107         int v_nv41 = vardata_add_variant(isa->vardata, "nv41", "NV41:G80", vs_chipset);
 108         int v_g80 = vardata_add_variant(isa->vardata, "g80", "G80+", vs_chipset);
 109         if (v_nv17 == -1 || v_nv41 == -1 || v_g80 == -1)
 110                 abort();
 111         vardata_variant_feature(isa->vardata, v_nv17, f_nv17f);
 112         vardata_variant_feature(isa->vardata, v_nv41, f_nv17f);
 113         vardata_variant_feature(isa->vardata, v_nv41, f_nv41f);
 114         vardata_variant_feature(isa->vardata, v_nv41, f_nv41op);
 115         vardata_variant_feature(isa->vardata, v_g80, f_nv41op);
 116         if (vardata_validate(isa->vardata))
 117                 abort();
 118 }
 119
 120 struct disisa hwsq_isa_s = {
 121         tabm,
 122         5,
 123         1,
 124         1,
 125         .prep = hwsq_prep,
 126 };