envydis/vp1.c

   1 /*
   2  * Copyright (C) 2012 Marcelina Kościelnicka <mwk@0x04.net>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "dis-intern.h"
  26
  27 /*
  28  * Immediate fields
  29  */
  30
  31 static struct rbitfield abtargoff = { 0, 16, .shr = 2 };
  32 static struct rbitfield btargoff = { { 9, 15 }, BF_SIGNED, .shr = 2, .pcrel = 1 };
  33 static struct rbitfield imm16off = { 0, 16 };
  34 static struct rbitfield immoff = { { 3, 11 }, BF_SIGNED };
  35 static struct rbitfield uimmoff = { 3, 11 };
  36 static struct rbitfield immloff = { { 0, 19 }, BF_SIGNED };
  37 static struct rbitfield immhoff = { { 0, 16 }, .shr = 16 };
  38 static struct bitfield xdimmoff = { { 0, 13 } };
  39 static struct bitfield compoff = { 3, 2 };
  40 static struct bitfield bitopoff = { 3, 4 };
  41 static struct bitfield cmpopoff = { 19, 4 };
  42 static struct bitfield baruoff = { 3, 2 };
  43 static struct bitfield barwoff = { 20, 2 };
  44 static struct bitfield rbimmoff = { 3, 8 };
  45 static struct bitfield rbimmmuloff = { { 9, 5, 0, 1 }, .shr=2 };
  46 static struct bitfield rbimmbadoff = { 0, 8 };
  47 static struct bitfield shiftoff = { { 5, 3 }, BF_SIGNED };
  48 static struct bitfield altshiftoff = { { 11, 3 }, BF_SIGNED };
  49 static struct bitfield vcxfrmoff = { 22, 2, 0, 1 };
  50 static struct bitfield factor1off = { { 1, 9 }, BF_SIGNED };
  51 static struct bitfield factor2off = { { 10, 9 }, BF_SIGNED };
  52 #define ABTARG atombtarg, &abtargoff
  53 #define BTARG atombtarg, &btargoff
  54 #define CTARG atomctarg, &btargoff
  55 #define IMM16 atomrimm, &imm16off
  56 #define IMM atomrimm, &immoff
  57 #define UIMM atomrimm, &uimmoff
  58 #define IMML atomrimm, &immloff
  59 #define IMMH atomrimm, &immhoff
  60 #define XDIMM atomimm, &xdimmoff
  61 #define COMP atomimm, &compoff
  62 #define BITOP atomimm, &bitopoff
  63 #define CMPOP atomimm, &cmpopoff
  64 #define BARU atomimm, &baruoff
  65 #define BARW atomimm, &barwoff
  66 #define BIMM atomimm, &rbimmoff
  67 #define BIMMMUL atomimm, &rbimmmuloff
  68 #define BIMMBAD atomimm, &rbimmbadoff
  69 #define SHIFT atomimm, &shiftoff
  70 #define ALTSHIFT atomimm, &altshiftoff
  71 #define VCXFRM atomimm, &vcxfrmoff
  72 #define FACTOR1 atomimm, &factor1off
  73 #define FACTOR2 atomimm, &factor2off
  74
  75 /*
  76  * Register fields
  77  */
  78
  79 static struct sreg sreg_sr[] = {
  80         { 30, "tick" },
  81         { 31, "csreq" },
  82         { -1 },
  83 };
  84
  85 static struct sreg sreg_mi[] = {
  86         { -1 },
  87 };
  88
  89 static struct sreg sreg_uc[] = {
  90         { 16, "uccfg" },
  91         { -1 },
  92 };
  93
  94 static struct sreg sreg_l[] = {
  95         { 0, "l0" },
  96         { 1, "l1" },
  97         { 2, "l2" },
  98         { 3, "l3" },
  99         { -1 },
 100 };
 101 static struct sreg rreg_sr[] = {
 102         { 31, 0, SR_ZERO },
 103         { -1 },
 104 };
 105 static struct bitfield dst_bf = { 19, 5 };
 106 static struct bitfield xdst_bf = { 19, 4 };
 107 static struct bitfield ddst_bf = { 19, 3 };
 108 static struct bitfield cdst_bf = { 19, 2 };
 109 static struct bitfield fdst_bf = { 19, 1 };
 110 static struct bitfield src1_bf = { 14, 5 };
 111 static struct bitfield mdst_bf = { 19, 5, 3, 1 };
 112 static struct bitfield xsrc1_bf = { 14, 4 };
 113 static struct bitfield dsrc1_bf = { 14, 3 };
 114 static struct bitfield csrc1_bf = { 14, 2 };
 115 static struct bitfield fsrc1_bf = { 14, 1 };
 116 static struct bitfield msrc1_bf = { 14, 5, 3, 1 };
 117 static struct bitfield src2_bf = { 9, 5 };
 118 static struct bitfield src3_bf = { 4, 5 };
 119 static struct bitfield csrcp_bf = { 3, 2 };
 120 static struct bitfield cdstp_bf = { 0, 2 };
 121 static struct bitfield mcdst_bf = { 0, 3 };
 122 static struct bitfield ignall_bf = { 0, 24 };
 123 static struct reg adst_r = { &dst_bf, "a" };
 124 static struct reg rdst_r = { &dst_bf, "r", .specials = rreg_sr };
 125 static struct reg vdst_r = { &dst_bf, "v" };
 126 static struct reg vdstq_r = { &dst_bf, "v", "q" };
 127 static struct reg ddst_r = { &ddst_bf, "d" };
 128 static struct reg cdst_r = { &cdst_bf, "c" };
 129 static struct reg ldst_r = { &cdst_bf, "l" };
 130 static struct reg xdst_r = { &xdst_bf, "x" };
 131 static struct reg mdst_r = { &mdst_bf, "m" };
 132 static struct reg fdst_r = { &fdst_bf, "f" };
 133 static struct reg srdst_r = { &dst_bf, "sr", .specials = sreg_sr, .always_special = 1 };
 134 static struct reg midst_r = { &dst_bf, "mi", .specials = sreg_mi, .always_special = 1 };
 135 static struct reg ucdst_r = { &dst_bf, "uc", .specials = sreg_uc, .always_special = 1 };
 136 static struct reg sldst_r = { &dst_bf, "l", .specials = sreg_l, .always_special = 1 };
 137 static struct reg adstd_r = { &dst_bf, "a", "d" };
 138 static struct reg asrc1_r = { &src1_bf, "a" };
 139 static struct reg asrc2_r = { &src2_bf, "a" };
 140 static struct reg rsrc2_r = { &src2_bf, "r", .specials = rreg_sr };
 141 static struct reg vsrc2_r = { &src2_bf, "v" };
 142 static struct reg vsrc3_r = { &src3_bf, "v" };
 143 static struct reg asrc1d_r = { &src1_bf, "a", "d" };
 144 static struct reg asrc2d_r = { &src2_bf, "a", "d" };
 145 static struct reg rsrc2d_r = { &src2_bf, "r", "d" };
 146 static struct reg vsrc2d_r = { &src2_bf, "v", "d" };
 147 static struct reg asrc2q_r = { &src2_bf, "a", "q" };
 148 static struct reg rsrc2q_r = { &src2_bf, "r", "q" };
 149 static struct reg vsrc2q_r = { &src2_bf, "v", "q" };
 150 static struct reg rsrc1_r = { &src1_bf, "r", .specials = rreg_sr };
 151 static struct reg vsrc1_r = { &src1_bf, "v" };
 152 static struct reg vsrc1d_r = { &src1_bf, "v", "d" };
 153 static struct reg vsrc1q_r = { &src1_bf, "v", "q" };
 154 static struct reg csrc1_r = { &csrc1_bf, "c" };
 155 static struct reg dsrc1_r = { &dsrc1_bf, "d" };
 156 static struct reg xsrc1_r = { &xsrc1_bf, "x" };
 157 static struct reg msrc1_r = { &msrc1_bf, "m" };
 158 static struct reg fsrc1_r = { &fsrc1_bf, "f" };
 159 static struct reg srsrc1_r = { &src1_bf, "sr", .specials = sreg_sr, .always_special = 1 };
 160 static struct reg misrc1_r = { &src1_bf, "mi", .specials = sreg_mi, .always_special = 1 };
 161 static struct reg ucsrc1_r = { &src1_bf, "uc", .specials = sreg_uc, .always_special = 1 };
 162 static struct reg slsrc1_r = { &src1_bf, "l", .specials = sreg_l, .always_special = 1 };
 163 static struct reg csrcp_r = { &csrcp_bf, "c" };
 164 static struct reg lsrcl_r = { &csrcp_bf, "l" };
 165 static struct reg cdstp_r = { &cdstp_bf, "c" };
 166 static struct reg ldstl_r = { &cdstp_bf, "l" };
 167 static struct reg vcdst_r = { &cdstp_bf, "vc" };
 168 static struct reg vc_r = { 0, "vc" };
 169 static struct reg vcidx_r = { &cdst_bf, "vc" };
 170
 171 #define ADST atomreg, &adst_r
 172 #define RDST atomreg, &rdst_r
 173 #define VDST atomreg, &vdst_r
 174 #define VDSTQ atomreg, &vdstq_r
 175 #define DDST atomreg, &ddst_r
 176 #define CDST atomreg, &cdst_r
 177 #define LDST atomreg, &ldst_r
 178 #define XDST atomreg, &xdst_r
 179 #define MDST atomreg, &mdst_r
 180 #define FDST atomreg, &fdst_r
 181 #define SRDST atomreg, &srdst_r
 182 #define MIDST atomreg, &midst_r
 183 #define UCDST atomreg, &ucdst_r
 184 #define SLDST atomreg, &sldst_r
 185 #define ADSTD atomreg, &adstd_r
 186 #define ASRC1 atomreg, &asrc1_r
 187 #define RSRC1 atomreg, &rsrc1_r
 188 #define VSRC1 atomreg, &vsrc1_r
 189 #define VSRC1D atomreg, &vsrc1d_r
 190 #define VSRC1Q atomreg, &vsrc1q_r
 191 #define CSRC1 atomreg, &csrc1_r
 192 #define DSRC1 atomreg, &dsrc1_r
 193 #define XSRC1 atomreg, &xsrc1_r
 194 #define MSRC1 atomreg, &msrc1_r
 195 #define FSRC1 atomreg, &fsrc1_r
 196 #define SRSRC1 atomreg, &srsrc1_r
 197 #define MISRC1 atomreg, &misrc1_r
 198 #define UCSRC1 atomreg, &ucsrc1_r
 199 #define SLSRC1 atomreg, &slsrc1_r
 200 #define ASRC1D atomreg, &asrc1d_r
 201 #define ASRC2 atomreg, &asrc2_r
 202 #define RSRC2 atomreg, &rsrc2_r
 203 #define VSRC2 atomreg, &vsrc2_r
 204 #define VSRC3 atomreg, &vsrc3_r
 205 #define ASRC2D atomreg, &asrc2d_r
 206 #define RSRC2D atomreg, &rsrc2d_r
 207 #define VSRC2D atomreg, &vsrc2d_r
 208 #define ASRC2Q atomreg, &asrc2q_r
 209 #define RSRC2Q atomreg, &rsrc2q_r
 210 #define VSRC2Q atomreg, &vsrc2q_r
 211 #define CSRCP atomreg, &csrcp_r
 212 #define CDSTP atomreg, &cdstp_r
 213 #define VCDST atomreg, &vcdst_r
 214 #define VC atomreg, &vc_r
 215 #define LSRCL atomreg, &lsrcl_r
 216 #define LDSTL atomreg, &ldstl_r
 217 #define VCIDX atomreg, &vcidx_r
 218 #define IGNCE atomign, &cdstp_bf
 219 #define IGNCD atomign, &mcdst_bf
 220 #define IGNALL atomign, &ignall_bf
 221 #define IGNDST atomign, &dst_bf
 222 #define IGNSRC1 atomign, &src1_bf
 223
 224 F1(intr, 16, N("intr"))
 225
 226 F(mcdst, 2, CDSTP, IGNCE);
 227 F(vcdst, 2, VCDST, IGNCE);
 228
 229 F(xdimm, 13, XDIMM, );
 230
 231 F(barldsti, 19, N("st"), N("ld"));
 232 F(barldstr, 0, N("st"), N("ld"));
 233
 234 F(s2vmode, 0, N("factor"), N("mask"))
 235 F(signop, 28, N("s"), N("u"))
 236 F(sign1, 2, N("u"), N("s"))
 237 F(sign2, 1, N("u"), N("s"))
 238 F(signs, 9, N("u"), N("s"))
 239 F(signd, 12, N("u"), N("s"))
 240 F1(lrp2x, 10, N("xor"))
 241 F1(vawrite, 11, N("va"))
 242 F(rnd, 8, N("rd"), N("rn"))
 243 F(altrnd, 9, N("rd"), N("rn"))
 244 F(fi, 3, N("fract"), N("int"))
 245 F(hilo, 4, N("hi"), N("lo"))
 246 F(vcflag, 21, N("sf"), N("zf"))
 247 F(vcsel, 2, N("sf"), N("zf"))
 248 F(swz, 3, N("lo"), N("hi"))
 249
 250 static struct insn tabaslctop[] = {
 251         { 0x00000000, 0x000001e0, SESTART, N("slct"), CSRCP, N("sf"), ASRC2D, SEEND },
 252         { 0x00000020, 0x000001e0, SESTART, N("slct"), CSRCP, N("zf"), ASRC2D, SEEND },
 253         { 0x00000040, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19"), ASRC2D, SEEND },
 254         { 0x00000060, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20d"), ASRC2D, SEEND },
 255         { 0x00000080, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20"), ASRC2Q, SEEND },
 256         { 0x000000a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b21"), ASRC2D, SEEND },
 257         { 0x000000c0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19a"), ASRC2D, SEEND },
 258         { 0x000000e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b18"), ASRC2D, SEEND },
 259         { 0x00000100, 0x000001e0, SESTART, N("slct"), CSRCP, N("asf"), ASRC2D, SEEND },
 260         { 0x00000120, 0x000001e0, SESTART, N("slct"), CSRCP, N("azf"), ASRC2D, SEEND },
 261         { 0x00000140, 0x000001e0, SESTART, N("slct"), CSRCP, N("aef"), ASRC2D, SEEND },
 262         { 0x00000160, 0x000001e0, SESTART, N("slct"), CSRCP, U("11"), ASRC2D, SEEND },
 263         { 0x00000180, 0x000001e0, SESTART, N("slct"), CSRCP, U("12"), ASRC2D, SEEND },
 264         { 0x000001a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("lzf"), ASRC2D, SEEND },
 265         { 0x000001c0, 0x000001e0, ASRC2 },
 266         { 0x000001e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("true"), ASRC2D, SEEND },
 267         { 0, 0, OOPS }
 268 };
 269
 270 static struct insn tabslctop[] = {
 271         { 0x00000000, 0x000001e0, SESTART, N("slct"), CSRCP, N("sf"), RSRC2D, SEEND },
 272         { 0x00000020, 0x000001e0, SESTART, N("slct"), CSRCP, N("zf"), RSRC2D, SEEND },
 273         { 0x00000040, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19"), RSRC2D, SEEND },
 274         { 0x00000060, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20d"), RSRC2D, SEEND },
 275         { 0x00000080, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20"), RSRC2Q, SEEND },
 276         { 0x000000a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b21"), RSRC2D, SEEND },
 277         { 0x000000c0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19a"), RSRC2D, SEEND },
 278         { 0x000000e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b18"), RSRC2D, SEEND },
 279         { 0x00000100, 0x000001e0, SESTART, N("slct"), CSRCP, N("asf"), RSRC2D, SEEND },
 280         { 0x00000120, 0x000001e0, SESTART, N("slct"), CSRCP, N("azf"), RSRC2D, SEEND },
 281         { 0x00000140, 0x000001e0, SESTART, N("slct"), CSRCP, N("aef"), RSRC2D, SEEND },
 282         { 0x00000160, 0x000001e0, SESTART, N("slct"), CSRCP, U("11"), RSRC2D, SEEND },
 283         { 0x00000180, 0x000001e0, SESTART, N("slct"), CSRCP, U("12"), RSRC2D, SEEND },
 284         { 0x000001a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("lzf"), RSRC2D, SEEND },
 285         { 0x000001c0, 0x000001e0, RSRC2 },
 286         { 0x000001e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("true"), RSRC2D, SEEND },
 287         { 0, 0, OOPS }
 288 };
 289
 290 static struct insn tabvslctop[] = {
 291         { 0x00000000, 0x000001e0, SESTART, N("slct"), CSRCP, N("sf"), VSRC2D, SEEND },
 292         { 0x00000020, 0x000001e0, SESTART, N("slct"), CSRCP, N("zf"), VSRC2D, SEEND },
 293         { 0x00000040, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19"), VSRC2D, SEEND },
 294         { 0x00000060, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20d"), VSRC2D, SEEND },
 295         { 0x00000080, 0x000001e0, SESTART, N("slct"), CSRCP, N("b20"), VSRC2Q, SEEND },
 296         { 0x000000a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b21"), VSRC2D, SEEND },
 297         { 0x000000c0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b19a"), VSRC2D, SEEND },
 298         { 0x000000e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("b18"), VSRC2D, SEEND },
 299         { 0x00000100, 0x000001e0, SESTART, N("slct"), CSRCP, N("asf"), VSRC2D, SEEND },
 300         { 0x00000120, 0x000001e0, SESTART, N("slct"), CSRCP, N("azf"), VSRC2D, SEEND },
 301         { 0x00000140, 0x000001e0, SESTART, N("slct"), CSRCP, N("aef"), VSRC2D, SEEND },
 302         { 0x00000160, 0x000001e0, SESTART, N("slct"), CSRCP, U("11"), VSRC2D, SEEND },
 303         { 0x00000180, 0x000001e0, SESTART, N("slct"), CSRCP, U("12"), VSRC2D, SEEND },
 304         { 0x000001a0, 0x000001e0, SESTART, N("slct"), CSRCP, N("lzf"), VSRC2D, SEEND },
 305         { 0x000001c0, 0x000001e0, VSRC2 },
 306         { 0x000001e0, 0x000001e0, SESTART, N("slct"), CSRCP, N("true"), VSRC2D, SEEND },
 307         { 0, 0, OOPS }
 308 };
 309
 310 static struct insn tabpred[] = {
 311         { 0x00000000, 0x000001e0, CSRCP, N("sf") },
 312         { 0x00000020, 0x000001e0, CSRCP, N("zf") },
 313         { 0x00000040, 0x000001e0, CSRCP, N("b19") },
 314         { 0x00000060, 0x000001e0, CSRCP, N("b20d") },
 315         { 0x00000080, 0x000001e0, CSRCP, N("b20") },
 316         { 0x000000a0, 0x000001e0, CSRCP, N("b21") },
 317         { 0x000000c0, 0x000001e0, CSRCP, N("b19a") },
 318         { 0x000000e0, 0x000001e0, CSRCP, N("b18") },
 319         { 0x00000100, 0x000001e0, CSRCP, N("asf") },
 320         { 0x00000120, 0x000001e0, CSRCP, N("azf") },
 321         { 0x00000140, 0x000001e0, CSRCP, N("aef") },
 322         { 0x00000160, 0x000001e0, CSRCP, U("11") },
 323         { 0x00000180, 0x000001e0, CSRCP, U("12") },
 324         { 0x000001a0, 0x000001e0, CSRCP, N("lzf") },
 325         { 0x000001c0, 0x000001e0, CSRCP, N("false") },
 326         { 0x000001e0, 0x000001e0, CSRCP, N("true") },
 327         { 0, 0, OOPS }
 328 };
 329
 330 static struct insn tabm[] = {
 331         { 0x01000000, 0xef000000, N("bmul"), T(rnd), T(signop), RDST, T(sign1), RSRC1, T(sign2), RSRC2 },
 332         { 0x02000000, 0xef000000, N("bmula"), T(rnd), T(signop), RDST, T(sign1), RSRC1, T(sign2), RSRC2 },
 333         { 0x04000000, 0xff000000, N("bvecmad"), RSRC1, RSRC2Q, T(pred), VCIDX, T(vcflag), VCXFRM },
 334         { 0x05000000, 0xff000000, N("bvecmadsel"), RSRC1, RSRC2Q, T(pred), VCIDX, T(vcflag), VCXFRM },
 335         { 0x08000000, 0xef000000, N("bmin"), T(signop), RDST, T(mcdst), RSRC1, T(slctop) },
 336         { 0x09000000, 0xef000000, N("bmax"), T(signop), RDST, T(mcdst), RSRC1, T(slctop) },
 337         { 0x0a000000, 0xef000000, N("babs"), T(signop), RDST, T(mcdst), RSRC1 },
 338         { 0x0b000000, 0xef000000, N("bneg"), T(signop), RDST, T(mcdst), RSRC1 },
 339         { 0x0c000000, 0xef000000, N("badd"), T(signop), RDST, T(mcdst), RSRC1, T(slctop) },
 340         { 0x0d000000, 0xef000000, N("bsub"), T(signop), RDST, T(mcdst), RSRC1, T(slctop) },
 341         { 0x0e000000, 0xef000000, N("bshr"), T(signop), RDST, T(mcdst), RSRC1, T(slctop) },
 342         { 0x0f000000, 0xff000000, N("bvec"), RSRC1, VCIDX, T(vcflag), VCXFRM },
 343         { 0x21000000, 0xef000000, N("bmul"), T(rnd), T(signop), RDST, T(sign1), RSRC1, T(sign2), BIMMMUL },
 344         { 0x22000000, 0xef000000, N("bmula"), T(rnd), T(signop), RDST, T(sign1), RSRC1, T(sign2), BIMMBAD },
 345         { 0x24000000, 0xff000000, N("vec"), FACTOR1, FACTOR2, VCIDX, T(vcflag), VCXFRM },
 346         { 0x25000000, 0xff000000, N("band"), RDST, RSRC1, BIMM },
 347         { 0x26000000, 0xff000000, N("bor"), RDST, RSRC1, BIMM },
 348         { 0x27000000, 0xff000000, N("bxor"), RDST, RSRC1, BIMM },
 349         { 0x28000000, 0xef000000, N("bmin"), T(signop), RDST, T(mcdst), RSRC1, BIMM },
 350         { 0x29000000, 0xef000000, N("bmax"), T(signop), RDST, T(mcdst), RSRC1, BIMM },
 351         { 0x2a000000, 0xef000000, N("babs"), T(signop), RDST, T(mcdst), RSRC1 },
 352         { 0x2b000000, 0xef000000, N("bneg"), T(signop), RDST, T(mcdst), RSRC1 },
 353         { 0x2c000000, 0xef000000, N("badd"), T(signop), RDST, T(mcdst), RSRC1, BIMM },
 354         { 0x2d000000, 0xef000000, N("bsub"), T(signop), RDST, T(mcdst), RSRC1, BIMM },
 355         { 0x2e000000, 0xef000000, N("bshr"), T(signop), RDST, T(mcdst), RSRC1, BIMM },
 356         { 0x41000000, 0xef000000, N("mul"), RDST, T(mcdst), RSRC1, T(slctop) },
 357         { 0x42000008, 0xff000078, N("nor"), RDST, T(mcdst), RSRC1, RSRC2 },
 358         { 0x42000010, 0xff000078, N("and"), RDST, T(mcdst), N("not"), RSRC1, RSRC2 },
 359         { 0x42000020, 0xff000078, N("and"), RDST, T(mcdst), RSRC1, N("not"), RSRC2 },
 360         { 0x42000030, 0xff000078, N("xor"), RDST, T(mcdst), RSRC1, RSRC2 },
 361         { 0x42000038, 0xff000078, N("nand"), RDST, T(mcdst), RSRC1, RSRC2 },
 362         { 0x42000040, 0xff000078, N("and"), RDST, T(mcdst), RSRC1, RSRC2 },
 363         { 0x42000048, 0xff000078, N("nxor"), RDST, T(mcdst), RSRC1, RSRC2 },
 364         { 0x42000058, 0xff000078, N("or"), RDST, T(mcdst), N("not"), RSRC1, RSRC2 },
 365         { 0x42000068, 0xff000078, N("or"), RDST, T(mcdst), RSRC1, N("not"), RSRC2 },
 366         { 0x42000070, 0xff000078, N("or"), RDST, T(mcdst), RSRC1, RSRC2 },
 367         { 0x42000000, 0xff000000, N("bitop"), BITOP, RDST, T(mcdst), RSRC1, RSRC2 },
 368         { 0x45000000, 0xff000000, N("vecms"), RSRC1, VCIDX, T(vcflag), VCXFRM },
 369         { 0x48000000, 0xef000000, N("min"), RDST, T(mcdst), RSRC1, T(slctop) },
 370         { 0x49000000, 0xef000000, N("max"), RDST, T(mcdst), RSRC1, T(slctop) },
 371         /* also 7a, but who can know what the official opcode is... */
 372         { 0x4a000000, 0xef000000, N("abs"), RDST, T(mcdst), RSRC1 },
 373         { 0x4b000000, 0xef000000, N("neg"), RDST, T(mcdst), RSRC1 },
 374         { 0x4c000000, 0xef000000, N("add"), RDST, T(mcdst), RSRC1, T(slctop) },
 375         { 0x4d000000, 0xef000000, N("sub"), RDST, T(mcdst), RSRC1, T(slctop) },
 376         { 0x4e000000, 0xff000000, N("sar"), RDST, T(mcdst), RSRC1, T(slctop) },
 377         { 0x4f000000, 0xff000000, N("snop"), IGNALL },
 378         { 0x5e000000, 0xff000000, N("shr"), RDST, T(mcdst), RSRC1, T(slctop) },
 379         { 0x61000000, 0xef000000, N("mul"), RDST, T(mcdst), RSRC1, IMM },
 380         { 0x62000000, 0xff000000, N("and"), RDST, T(mcdst), RSRC1, IMM },
 381         { 0x63000000, 0xff000000, N("xor"), RDST, T(mcdst), RSRC1, IMM },
 382         { 0x64000000, 0xff000000, N("or"), RDST, T(mcdst), RSRC1, IMM },
 383         { 0x65000000, 0xff000000, N("mov"), RDST, IMML },
 384         { 0x68000000, 0xef000000, N("min"), RDST, T(mcdst), RSRC1, IMM },
 385         { 0x69000000, 0xef000000, N("max"), RDST, T(mcdst), RSRC1, IMM },
 386         { 0x6a000000, 0xff0000e0, N("mov"), VDST, COMP, RSRC1, IGNCD },
 387         { 0x6a000040, 0xff0000f8, N("mov"), SRDST, RSRC1, IGNCD },
 388         { 0x6a000048, 0xff0000f8, N("mov"), MIDST, RSRC1, IGNCD },
 389         { 0x6a000050, 0xff0000f8, N("mov"), UCDST, RSRC1, IGNCD },
 390         { 0x6a000058, 0xff0000f8, N("mov"), SLDST, RSRC1, IGNCD },
 391         { 0x6a000060, 0xff0000f8, N("mov"), ADST, RSRC1, IGNCD },
 392         { 0x6a0000a0, 0xff0000f0, N("mov"), MDST, RSRC1, IGNCD },
 393         { 0x6a0000b0, 0xff0000f8, N("mov"), DDST, RSRC1, IGNCD },
 394         { 0x6a0000b8, 0xff0000f8, N("mov"), FDST, RSRC1, IGNCD },
 395         { 0x6a0000c0, 0xff0000f8, N("mov"), XDST, RSRC1, IGNCD },
 396         { 0x6b000000, 0xff0000e0, N("mov"), RDST, VSRC1, COMP, IGNCD },
 397         { 0x6b000040, 0xff0000f8, N("mov"), RDST, SRSRC1, IGNCD },
 398         { 0x6b000048, 0xff0000f8, N("mov"), RDST, MISRC1, IGNCD },
 399         { 0x6b000050, 0xff0000f8, N("mov"), RDST, UCSRC1, IGNCD },
 400         { 0x6b000058, 0xff0000f8, N("mov"), RDST, SLSRC1, IGNCD },
 401         { 0x6b000060, 0xff0000f8, N("mov"), RDST, ASRC1, IGNCD },
 402         { 0x6b000068, 0xff0000f8, N("mov"), RDST, CSRC1, IGNCD },
 403         { 0x6b0000a0, 0xff0000f0, N("mov"), RDST, MSRC1, IGNCD },
 404         { 0x6b0000b0, 0xff0000f8, N("mov"), RDST, DSRC1, IGNCD },
 405         { 0x6b0000b8, 0xff0000f8, N("mov"), RDST, FSRC1, IGNCD },
 406         { 0x6b0000c0, 0xff0000f8, N("mov"), RDST, XSRC1, IGNCD },
 407         { 0x6c000000, 0xef000000, N("add"), RDST, T(mcdst), RSRC1, IMM },
 408         { 0x6d000000, 0xef000000, N("sub"), RDST, T(mcdst), RSRC1, IMM },
 409         { 0x6e000000, 0xff000000, N("sar"), RDST, T(mcdst), RSRC1, IMM },
 410         { 0x75000000, 0xff000000, N("sethi"), RDST, IMMH },
 411         { 0x7a000000, 0xff000000, N("abs"), RDST, T(mcdst), RSRC1 },
 412         { 0x7b000000, 0xff000000, N("neg"), RDST, T(mcdst), RSRC1 },
 413         { 0x7e000000, 0xff000000, N("shr"), RDST, T(mcdst), RSRC1, IMM },
 414         { 0x80000000, 0xff000000, N("vmul"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, T(sign2), VSRC2 },
 415         { 0xa0000000, 0xff000000, N("vmul"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, T(sign2), BIMMMUL },
 416         { 0xb0000000, 0xff000000, N("vmul"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, T(sign2), BIMMBAD },
 417         { 0x81000000, 0xef000000, N("vmul"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1, T(sign2), VSRC2 },
 418         { 0xa1000000, 0xef000000, N("vmul"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1, T(sign2), BIMMMUL },
 419         { 0x82000000, 0xef000000, N("vmac"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1, T(sign2), VSRC2 },
 420         { 0xa2000000, 0xef000000, N("vmac"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1, T(sign2), BIMMMUL },
 421         { 0x83000000, 0xef000000, N("vmac"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, T(sign2), VSRC2 },
 422         { 0xa3000000, 0xff000000, N("vmac"), T(signop), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, T(sign2), BIMMMUL },
 423         { 0x84000000, 0xff000000, N("vmad2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1D, T(sign2), VSRC2 },
 424         { 0x85000000, 0xef000000, N("vmad2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1D, T(sign2), VSRC2 },
 425         { 0x86000000, 0xff000000, N("vmac2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1D },
 426         { 0x96000000, 0xff000000, N("vmac2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, VSRC3 },
 427         { 0xa6000000, 0xff000000, N("vmac2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), DISCARD, T(sign1), VSRC1, VSRC3 },
 428         { 0x87000000, 0xef000000, N("vmac2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1D },
 429         { 0xa7000000, 0xff000000, N("vmac2"), T(signop), T(s2vmode), T(rnd), T(fi), SHIFT, T(hilo), VDST, T(sign1), VSRC1, VSRC3 },
 430         { 0xb3000000, 0xff000000, N("vlrp2"), T(signd), T(vawrite), T(rnd), SHIFT, VDST, T(signs), T(lrp2x), VSRC1Q, CSRCP, VCDST, T(vcsel) },
 431         { 0xb4000000, 0xff000000, N("vlrp4a"), T(rnd), SHIFT, DISCARD, VSRC1Q, CSRCP, VCDST, T(vcsel) },
 432         { 0xb5000000, 0xff000000, N("vlrpf"), T(rnd), SHIFT, DISCARD, VSRC1Q, CSRCP, VSRC2, VCDST, T(vcsel) },
 433         { 0xb6000000, 0xff000000, N("vlrp4b"), N("u"), T(altrnd), ALTSHIFT, VDST, VSRC1Q, CSRCP, T(pred), VCDST, T(vcsel) },
 434         { 0xb7000000, 0xff000000, N("vlrp4b"), N("s"), T(altrnd), ALTSHIFT, VDST, VSRC1Q, CSRCP, T(pred), VCDST, T(vcsel) },
 435         { 0x88000000, 0xef000000, N("vmin"), T(signop), VDST, T(vcdst), VSRC1, VSRC2 },
 436         { 0x89000000, 0xef000000, N("vmax"), T(signop), VDST, T(vcdst), VSRC1, VSRC2 },
 437         { 0x8a000000, 0xef000000, N("vabs"), T(signop), VDST, T(vcdst), VSRC1 },
 438         { 0x8b000000, 0xff000000, N("vneg"), T(signop), VDST, T(vcdst), VSRC1 },
 439         { 0x8c000000, 0xef000000, N("vadd"), T(signop), VDST, T(vcdst), VSRC1, VSRC2 },
 440         { 0x8d000000, 0xef000000, N("vsub"), T(signop), VDST, T(vcdst), VSRC1, VSRC2 },
 441         { 0x8e000000, 0xef000000, N("vshr"), T(signop), VDST, T(vcdst), VSRC1, VSRC2 },
 442         { 0x8f000000, 0xff000000, N("vcmpad"), CMPOP, T(vcdst), VSRC1D, T(vslctop) },
 443         { 0x90000000, 0xff000000, N("vlrp"), T(rnd), SHIFT, VDST, VSRC1D, VSRC2 },
 444         { 0x94000008, 0xff000078, N("vnor"), VDST, T(vcdst), VSRC1, VSRC2 },
 445         { 0x94000010, 0xff000078, N("vand"), VDST, T(vcdst), N("not"), VSRC1, VSRC2 },
 446         { 0x94000020, 0xff000078, N("vand"), VDST, T(vcdst), VSRC1, N("not"), VSRC2 },
 447         { 0x94000030, 0xff000078, N("vxor"), VDST, T(vcdst), VSRC1, VSRC2 },
 448         { 0x94000038, 0xff000078, N("vnand"), VDST, T(vcdst), VSRC1, VSRC2 },
 449         { 0x94000040, 0xff000078, N("vand"), VDST, T(vcdst), VSRC1, VSRC2 },
 450         { 0x94000048, 0xff000078, N("vnxor"), VDST, T(vcdst), VSRC1, VSRC2 },
 451         { 0x94000058, 0xff000078, N("vor"), VDST, T(vcdst), N("not"), VSRC1, VSRC2 },
 452         { 0x94000068, 0xff000078, N("vor"), VDST, T(vcdst), VSRC1, N("not"), VSRC2 },
 453         { 0x94000070, 0xff000078, N("vor"), VDST, T(vcdst), VSRC1, VSRC2 },
 454         { 0x94000000, 0xff000000, N("vbitop"), BITOP, VDST, T(vcdst), VSRC1, VSRC2 },
 455         { 0x9b000000, 0xff000000, N("vswz"), VDST, VSRC1, VSRC2, T(swz), VSRC3 },
 456         { 0x9f000000, 0xff000000, N("vadd9"), VDST, T(vcdst), VSRC1, VSRC2, VSRC3 },
 457         { 0xa4000000, 0xff000000, N("vclip"), VDST, T(vcdst), VSRC1, VSRC2, VSRC3 },
 458         { 0xa5000000, 0xff000000, N("vminabs"), VDST, T(vcdst), VSRC1, VSRC2 },
 459         { 0xa8000000, 0xef000000, N("vmin"), T(signop), VDST, T(vcdst), VSRC1, BIMM },
 460         { 0xa9000000, 0xef000000, N("vmax"), T(signop), VDST, T(vcdst), VSRC1, BIMM },
 461         { 0xac000000, 0xef000000, N("vadd"), T(signop), VDST, T(vcdst), VSRC1, BIMM },
 462         { 0xbd000000, 0xff000000, N("vsub"), T(signop), VDST, T(vcdst), VSRC1, BIMM },
 463         { 0xae000000, 0xef000000, N("vshr"), T(signop), VDST, T(vcdst), VSRC1, BIMM },
 464         { 0xaa000000, 0xff000000, N("vand"), VDST, T(vcdst), VSRC1, BIMM },
 465         { 0xab000000, 0xff000000, N("vxor"), VDST, T(vcdst), VSRC1, BIMM },
 466         { 0xaf000000, 0xff000000, N("vor"), VDST, T(vcdst), VSRC1, BIMM },
 467         { 0xba000000, 0xff000000, N("mov"), VDST, T(vcdst), VSRC1 },
 468         { 0xbb000000, 0xff000000, N("mov"), VDST, VC },
 469         { 0xad000000, 0xff000000, N("vmov"), VDST, T(vcdst), BIMM },
 470         { 0xbf000000, 0xff000000, N("vnop"), IGNALL },
 471         { 0xc0000000, 0xff000000, N("ldavh"), VDST, T(mcdst), ASRC1, T(aslctop) },
 472         { 0xc1000000, 0xff000000, N("ldavv"), VDST, T(mcdst), ASRC1, T(aslctop) },
 473         { 0xc2000000, 0xff000000, N("ldas"), RDST, T(mcdst), ASRC1, T(aslctop) },
 474         { 0xc3000000, 0xff000000, N("xdld"), ADST, ASRC1D, T(xdimm) },
 475         { 0xc4000000, 0xff000000, N("stavh"), VSRC1, T(mcdst), ADST, T(aslctop) },
 476         { 0xc5000000, 0xff000000, N("stavv"), VSRC1, T(mcdst), ADST, T(aslctop) },
 477         { 0xc6000000, 0xff000000, N("stas"), RSRC1, T(mcdst), ADST, T(aslctop) },
 478         { 0xc7000000, 0xff000000, N("xdst"), ADSTD, ASRC1, T(xdimm) },
 479         { 0xc8000000, 0xff000000, N("ldaxh"), VDSTQ, T(mcdst), ASRC1, T(aslctop) },
 480         { 0xc9000000, 0xff000000, N("ldaxv"), VDSTQ, T(mcdst), ASRC1, T(aslctop) },
 481         { 0xca000000, 0xff000000, N("aadd"), ADST, T(mcdst), T(aslctop), IGNSRC1 },
 482         { 0xcb000000, 0xff000000, N("add"), ADST, T(mcdst), ASRC1, T(aslctop) },
 483         { 0xcc000000, 0xff000000, N("setlo"), ADST, IMM16 },
 484         { 0xcd000000, 0xff000000, N("sethi"), ADST, IMMH },
 485         { 0xce000000, 0xff010000, N("xdbar"), T(barldsti), BARW, BARU },
 486         { 0xce010000, 0xff010000, N("xdbar"), T(barldstr), ADST, BARU },
 487         { 0xcf000000, 0xff010000, N("xdwait"), T(barldsti), BARW, BARU },
 488         { 0xcf010000, 0xff010000, N("xdwait"), T(barldstr), ADST, BARU },
 489         { 0xd0000000, 0xff000000, N("ldavh"), VDST, T(mcdst), ASRC1, IMM },
 490         { 0xd1000000, 0xff000000, N("ldavv"), VDST, T(mcdst), ASRC1, IMM },
 491         { 0xd2000000, 0xff000000, N("ldas"), RDST, T(mcdst), ASRC1, IMM },
 492         { 0xd3000008, 0xff000078, N("nor"), ADST, T(mcdst), ASRC1, ASRC2 },
 493         { 0xd3000010, 0xff000078, N("and"), ADST, T(mcdst), N("not"), ASRC1, ASRC2 },
 494         { 0xd3000020, 0xff000078, N("and"), ADST, T(mcdst), ASRC1, N("not"), ASRC2 },
 495         { 0xd3000030, 0xff000078, N("xor"), ADST, T(mcdst), ASRC1, ASRC2 },
 496         { 0xd3000038, 0xff000078, N("nand"), ADST, T(mcdst), ASRC1, ASRC2 },
 497         { 0xd3000040, 0xff000078, N("and"), ADST, T(mcdst), ASRC1, ASRC2 },
 498         { 0xd3000048, 0xff000078, N("nxor"), ADST, T(mcdst), ASRC1, ASRC2 },
 499         { 0xd3000058, 0xff000078, N("or"), ADST, T(mcdst), N("not"), ASRC1, ASRC2 },
 500         { 0xd3000068, 0xff000078, N("or"), ADST, T(mcdst), ASRC1, N("not"), ASRC2 },
 501         { 0xd3000070, 0xff000078, N("or"), ADST, T(mcdst), ASRC1, ASRC2 },
 502         { 0xd3000000, 0xff000000, N("bitop"), BITOP, ADST, T(mcdst), ASRC1, ASRC2 },
 503         { 0xd4000000, 0xff000000, N("stavh"), VSRC1, T(mcdst), ADST, IMM },
 504         { 0xd5000000, 0xff000000, N("stavv"), VSRC1, T(mcdst), ADST, IMM },
 505         { 0xd6000000, 0xff000000, N("stas"), RSRC1, T(mcdst), ADST, IMM },
 506         { 0xd7000000, 0xff000001, N("ldr"), VDST, ASRC1, VSRC2 },
 507         { 0xd7000001, 0xff000001, N("star"), VSRC1, ADST, T(aslctop) },
 508         { 0xd8000000, 0xff000000, N("ldvh"), VDST, T(mcdst), ASRC1, UIMM },
 509         { 0xd9000000, 0xff000000, N("ldvv"), VDST, T(mcdst), ASRC1, UIMM },
 510         { 0xda000000, 0xff000000, N("lds"), RDST, T(mcdst), ASRC1, UIMM },
 511         { 0xdc000000, 0xff000000, N("stvh"), VSRC1, T(mcdst), ADST, UIMM },
 512         { 0xdd000000, 0xff000000, N("stvv"), VSRC1, T(mcdst), ADST, UIMM },
 513         { 0xde000000, 0xff000000, N("sts"), RSRC1, T(mcdst), ADST, UIMM },
 514         { 0xdf000000, 0xff000000, N("anop"), IGNALL },
 515         { 0xe00001e0, 0xff0001f8, N("bra"), T(mcdst), BTARG },
 516         { 0xe0000000, 0xff000000, N("bra"), T(mcdst), T(pred), BTARG },
 517         { 0xe10001e0, 0xff0001f8, N("bra"), N("loop"), LDSTL, T(mcdst), LSRCL, BTARG },
 518         { 0xe1000000, 0xff000000, N("bra"), N("loop"), LDSTL, T(mcdst), LSRCL, T(pred), BTARG },
 519         { 0xe2000000, 0xff000000, N("bra"), T(mcdst), N("not"), T(pred), BTARG },
 520         { 0xe3000000, 0xff000000, N("bra"), N("loop"), LDSTL, T(mcdst), LSRCL, N("not"), T(pred), BTARG },
 521         { 0xe40001e0, 0xff0001f8, N("call"), T(mcdst), CTARG },
 522         { 0xe4000000, 0xff000000, N("call"), T(mcdst), T(pred), CTARG },
 523         { 0xe50001e0, 0xff0001f8, N("call"), N("loop"), LDSTL, T(mcdst), LSRCL, BTARG },
 524         { 0xe5000000, 0xff000000, N("call"), N("loop"), LDSTL, T(mcdst), LSRCL, T(pred), BTARG },
 525         { 0xe6000000, 0xff000000, N("call"), T(mcdst), N("not"), T(pred), CTARG },
 526         { 0xe7000000, 0xff000000, N("call"), N("loop"), LDSTL, T(mcdst), LSRCL, N("not"), T(pred), BTARG },
 527         { 0xe8000000, 0xff000000, N("ret"), T(mcdst), IGNALL },
 528         { 0xea000000, 0xff000000, N("abra"), IGNDST, ABTARG },
 529         { 0xef000000, 0xff000000, N("bnop"), IGNALL },
 530         { 0xf0000000, 0xff000000, N("mov"), LDST, CDST, IMM16 },
 531         { 0xff000000, 0xff000000, N("exit"), IGNDST, T(intr), IMM16 },
 532         { 0, 0, OOPS },
 533 };
 534
 535 static struct insn tabroot[] = {
 536         { 0, 0, OP1B, T(m) },
 537 };
 538
 539 struct disisa vp1_isa_s = {
 540         tabroot,
 541         1,
 542         1,
 543         4,
 544 };