x86_64_sse2_x87/fasm/examples/x86/include/ext/avx512f.inc

   1 \r
   2 if ~ defined AVX_512\r
   3 \r
   4         restore AVX_512 ; this ensures that symbol cannot be forward-referenced\r
   5         AVX_512 = 1\r
   6 \r
   7         include 'avx2.inc'\r
   8 \r
   9         element AVX_512.reg\r
  10 \r
  11         element AVX_512.r128 : AVX_512.reg + 16\r
  12         element AVX_512.r256 : AVX_512.reg + 32\r
  13         element AVX_512.r512 : AVX_512.reg + 64\r
  14 \r
  15         repeat 8, i:0\r
  16                 element zmm#i? : AVX_512.r512 + i\r
  17         end repeat\r
  18 \r
  19         if defined xmm8\r
  20                 repeat 16, i:16\r
  21                         element xmm#i? : AVX_512.r128 + i\r
  22                         element ymm#i? : AVX_512.r256 + i\r
  23                 end repeat\r
  24                 repeat 8+16, i:8\r
  25                         element zmm#i? : AVX_512.r512 + i\r
  26                 end repeat\r
  27         end if\r
  28 \r
  29         element AVX_512.maskreg\r
  30 \r
  31         repeat 8, i:0\r
  32                 element k#i? : AVX_512.maskreg + i\r
  33         end repeat\r
  34 \r
  35         define x86.dqqword? :64\r
  36         define x86.zword? :64\r
  37 \r
  38         EVEX_AS_VEX = 0\r
  39         EVEX_W1 = 1 shl 15\r
  40         EVEX_REQUIRED = 1 shl 10\r
  41         EVEX_FORBIDDEN = 1 shl 2\r
  42         EVEX_VL = 1 shl 22\r
  43 \r
  44         AVX512VL = 0\r
  45 \r
  46         calminstruction AVX_512.parse_operand namespace, operand\r
  47 \r
  48                 local   size, type, mod, rm, imm\r
  49                 local   i, sym, cmd\r
  50 \r
  51                 asmcmd  =x86.=parse_operand namespace, operand\r
  52 \r
  53                 arrange type, namespace.=type\r
  54                 arrange size, namespace.=size\r
  55                 arrange imm, namespace.=imm\r
  56 \r
  57                 check   type = 'reg' & size = 1 & rm >= 4 & (~ defined x86.REX_FORBIDDEN | rm and x86.REX_FORBIDDEN)\r
  58                 jyes    invalid_operand\r
  59                 check   type = 'imm' & size = 0\r
  60                 jno     export_common\r
  61 \r
  62                 check   imm eq 1 elementof imm & 1 metadataof imm relativeto SSE.reg\r
  63                 jyes    xmm_register\r
  64                 check   imm eq 1 elementof imm & 1 metadataof imm relativeto AVX.reg\r
  65                 jyes    ymm_register\r
  66                 check   1 metadataof (1 metadataof imm) relativeto AVX_512.reg & imm eq 1 elementof imm\r
  67                 jyes    xyzmm_register\r
  68                 check   imm eq 1 elementof imm & 1 metadataof imm relativeto AVX_512.maskreg\r
  69                 jyes    mask_register\r
  70                 exit\r
  71 \r
  72             invalid_operand:\r
  73                 asmcmd  =err 'invalid operand'\r
  74 \r
  75             xmm_register:\r
  76 \r
  77                 compute rm, 1 metadataof imm - SSE.reg\r
  78                 compute size, 16\r
  79 \r
  80                 jump    export_mmreg\r
  81 \r
  82             ymm_register:\r
  83 \r
  84                 compute rm, 1 metadataof imm - AVX.reg\r
  85                 compute size, 32\r
  86 \r
  87                 jump    export_mmreg\r
  88 \r
  89             mask_register:\r
  90 \r
  91                 compute rm, 1 metadataof imm - AVX_512.maskreg\r
  92                 compute size, 8\r
  93                 compute type, 'maskreg'\r
  94 \r
  95                 jump    export_reg\r
  96 \r
  97             xyzmm_register:\r
  98 \r
  99                 compute rm, 1 metadataof imm - 1 elementof (1 metadataof imm)\r
 100                 compute size, 1 metadataof (1 metadataof imm) - AVX_512.reg\r
 101 \r
 102             export_mmreg:\r
 103 \r
 104                 compute type, 'mmreg'\r
 105 \r
 106             export_reg:\r
 107 \r
 108                 compute mod, 11b\r
 109 \r
 110                 arrange sym, namespace.=mod\r
 111                 publish sym, mod\r
 112 \r
 113                 arrange sym, namespace.=rm\r
 114                 publish sym, rm\r
 115 \r
 116                 arrange sym, namespace.=type\r
 117                 publish sym, type\r
 118 \r
 119                 arrange sym, namespace.=size\r
 120                 publish sym, size\r
 121 \r
 122             export_common:\r
 123 \r
 124                 compute i, 0\r
 125 \r
 126                 arrange sym, namespace.=mask\r
 127                 publish sym, i\r
 128 \r
 129                 arrange sym, namespace.=evex_b\r
 130                 publish sym, i\r
 131 \r
 132                 arrange sym, namespace.=memsize\r
 133                 publish sym, i\r
 134 \r
 135         end calminstruction\r
 136 \r
 137         calminstruction AVX_512.parse_operand_k1z namespace,operand\r
 138 \r
 139                 local   k1, z, mask, sym\r
 140                 transform operand\r
 141                 match   operand {k1} { =z? }, operand\r
 142                 jyes    k1z\r
 143                 match   operand {k1}, operand\r
 144                 jyes    k1\r
 145                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 146                 exit\r
 147             k1z:\r
 148                 compute z, 80h\r
 149                 jump    masked\r
 150             k1:\r
 151                 compute z, 0\r
 152             masked:\r
 153                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 154                 arrange sym, namespace.=type\r
 155                 check   z & sym = 'mem'\r
 156                 jyes    invalid_mask\r
 157                 check   k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0\r
 158                 jno     invalid_mask\r
 159                 compute mask, (1 metadataof k1 - AVX_512.maskreg) or z\r
 160                 arrange sym, namespace.=mask\r
 161                 publish sym, mask\r
 162                 exit\r
 163             invalid_mask:\r
 164                 asmcmd  =err 'invalid mask'\r
 165 \r
 166         end calminstruction\r
 167 \r
 168         calminstruction AVX_512.parse_operand_k1 namespace,operand\r
 169 \r
 170                 local   k1, mask, sym\r
 171                 transform operand\r
 172                 match   operand {k1}, operand\r
 173                 jyes    k1\r
 174                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 175                 exit\r
 176             k1:\r
 177                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 178                 arrange sym, namespace.=type\r
 179                 check   k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0\r
 180                 jno     invalid_mask\r
 181                 compute mask, 1 metadataof k1 - AVX_512.maskreg\r
 182                 arrange sym, namespace.=mask\r
 183                 publish sym, mask\r
 184                 exit\r
 185             invalid_mask:\r
 186                 asmcmd  =err 'invalid mask'\r
 187 \r
 188         end calminstruction\r
 189 \r
 190         calminstruction AVX_512.parse_operand_bcst namespace,operand,unit\r
 191 \r
 192                 local   broadcast, memsize, size, b\r
 193                 local   sym\r
 194 \r
 195                 transform operand\r
 196                 match   operand {broadcast}, operand\r
 197                 jyes    mem_bcst\r
 198                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 199                 exit\r
 200 \r
 201             invalid_operand:\r
 202                 asmcmd  =err 'invalid operand'\r
 203 \r
 204             mem_bcst:\r
 205                 asmcmd  =AVX_512.=parse_operand namespace, operand\r
 206                 arrange sym, namespace.=type\r
 207                 check   sym = 'mem'\r
 208                 jno     invalid_operand\r
 209 \r
 210                 arrange size, namespace.=size\r
 211                 compute memsize, unit\r
 212                 check   memsize\r
 213                 jyes    implied_unit\r
 214                 check   size\r
 215                 jno     operand_size_not_specified\r
 216                 compute memsize, size\r
 217                 jump    unit_ok\r
 218             operand_size_not_specified:\r
 219                 asmcmd  =err 'operand size not specified'\r
 220                 exit\r
 221             implied_unit:\r
 222                 check   size and not memsize\r
 223                 jno     unit_ok\r
 224                 asmcmd  =err 'invalid operand size'\r
 225                 exit\r
 226             unit_ok:\r
 227 \r
 228                 match   =1to2?, broadcast\r
 229                 jyes    bcst_2\r
 230                 match   =1to4?, broadcast\r
 231                 jyes    bcst_4\r
 232                 match   =1to8?, broadcast\r
 233                 jyes    bcst_8\r
 234                 match   =1to16?, broadcast\r
 235                 jyes    bcst_16\r
 236                 asmcmd  =err 'invalid broadcast'\r
 237                 exit\r
 238             bcst_2:\r
 239                 compute broadcast, 2\r
 240                 jump    bcst_ok\r
 241             bcst_4:\r
 242                 compute broadcast, 4\r
 243                 jump    bcst_ok\r
 244             bcst_8:\r
 245                 compute broadcast, 8\r
 246                 jump    bcst_ok\r
 247             bcst_16:\r
 248                 compute broadcast, 16\r
 249             bcst_ok:\r
 250                 compute size, memsize * broadcast\r
 251                 compute b, 1\r
 252 \r
 253                 arrange sym, namespace.=memsize\r
 254                 publish sym, memsize\r
 255 \r
 256                 arrange sym, namespace.=size\r
 257                 publish sym, size\r
 258 \r
 259                 arrange sym, namespace.=broadcast\r
 260                 publish sym, broadcast\r
 261 \r
 262                 arrange sym, namespace.=evex_b\r
 263                 publish sym, b\r
 264 \r
 265         end calminstruction\r
 266 \r
 267         calminstruction AVX_512.parse_er namespace,operand,vsize:64\r
 268 \r
 269                 local   type, size, rounding, b\r
 270                 local   sym\r
 271 \r
 272                 arrange type, namespace.=type\r
 273                 arrange size, namespace.=size\r
 274                 check   type = 'mem' | size <> vsize\r
 275                 jyes    invalid_operand\r
 276 \r
 277                 match   { =rn?-=sae? }, operand\r
 278                 jyes    rounding_0\r
 279                 match   { =rd?-=sae? }, operand\r
 280                 jyes    rounding_1\r
 281                 match   { =ru?-=sae? }, operand\r
 282                 jyes    rounding_2\r
 283                 match   { =rz?-=sae? }, operand\r
 284                 jyes    rounding_3\r
 285             invalid_operand:\r
 286                 asmcmd  =err 'invalid operand'\r
 287                 exit\r
 288             rounding_0:\r
 289                 compute rounding, 0\r
 290                 jump    rounding_ok\r
 291             rounding_1:\r
 292                 compute rounding, 1\r
 293                 jump    rounding_ok\r
 294             rounding_2:\r
 295                 compute rounding, 2\r
 296                 jump    rounding_ok\r
 297             rounding_3:\r
 298                 compute rounding, 3\r
 299                 jump    rounding_ok\r
 300 \r
 301             rounding_ok:\r
 302                 compute b, 1\r
 303 \r
 304                 arrange sym, namespace.=rounding\r
 305                 publish sym, rounding\r
 306 \r
 307                 arrange sym, namespace.=evex_b\r
 308                 publish sym, b\r
 309 \r
 310         end calminstruction\r
 311 \r
 312         calminstruction AVX_512.parse_sae namespace,operand\r
 313 \r
 314                 local   type, rounding, b\r
 315                 local   sym\r
 316 \r
 317                 arrange type, namespace.=type\r
 318                 check   type = 'mem'\r
 319                 jyes    invalid_operand\r
 320 \r
 321                 match   { =sae? }, operand\r
 322                 jno     invalid_operand\r
 323 \r
 324                 compute b, 1\r
 325                 compute rounding, -1\r
 326 \r
 327                 arrange sym, namespace.=rounding\r
 328                 publish sym, rounding\r
 329 \r
 330                 arrange sym, namespace.=evex_b\r
 331                 publish sym, b\r
 332 \r
 333                 exit\r
 334 \r
 335             invalid_operand:\r
 336                 asmcmd  =err 'invalid operand'\r
 337 \r
 338         end calminstruction\r
 339 \r
 340         calminstruction AVX_512.store_instruction vsize*,vex_mpw*,evex_f*,opcode*,rm_operand*,mask*,reg*,vreg:0,imm_size:0,imm\r
 341 \r
 342                 local   evex, evex_flags\r
 343                 local   segment_prefix, evex_b, rounding, memsize\r
 344                 local   mode, mod, rm\r
 345                 local   scale, index, base\r
 346                 local   displacement, displacement_size, auto_relative\r
 347                 local   evex_displacement_size, compressed_displacement\r
 348                 local   sym\r
 349 \r
 350                 arrange segment_prefix, rm_operand.=segment_prefix\r
 351                 arrange evex_b, rm_operand.=evex_b\r
 352                 arrange rounding, rm_operand.=rounding\r
 353                 arrange memsize, rm_operand.=memsize\r
 354 \r
 355                 arrange mode, rm_operand.=mode\r
 356                 arrange mod, rm_operand.=mod\r
 357                 arrange rm, rm_operand.=rm\r
 358 \r
 359                 arrange scale, rm_operand.=scale\r
 360                 arrange index, rm_operand.=index\r
 361                 arrange base, rm_operand.=base\r
 362 \r
 363                 arrange displacement_size, rm_operand.=displacement_size\r
 364                 arrange displacement, rm_operand.=displacement\r
 365                 arrange auto_relative, rm_operand.=auto_relative\r
 366 \r
 367                 check   segment_prefix\r
 368                 jno     segment_prefix_ok\r
 369 \r
 370                 check   mode = 64\r
 371                 jyes    segment_in_long_mode\r
 372                 check   mode = 16 & ( rm = 2 | rm = 3 | ( mod > 0 & rm = 6 ) )\r
 373                 jyes    ss_segment_default\r
 374                 check   mode = 32 & ( ( mod > 0 & rm = 5 ) | ( rm = 4 & base = 4 ) | ( mod > 0 & rm = 4 & base = 5 ) )\r
 375                 jyes    ss_segment_default\r
 376 \r
 377             ds_segment_default:\r
 378                 check   segment_prefix = 3Eh\r
 379                 jyes    segment_prefix_ok\r
 380                 jump    store_segment_prefix\r
 381             ss_segment_default:\r
 382                 check   segment_prefix = 36h\r
 383                 jyes    segment_prefix_ok\r
 384                 jump    store_segment_prefix\r
 385             segment_in_long_mode:\r
 386                 check   segment_prefix < 64h\r
 387                 jyes    segment_prefix_ok\r
 388             store_segment_prefix:\r
 389                 asmcmd  =db segment_prefix\r
 390             segment_prefix_ok:\r
 391 \r
 392                 check   mod <> 11b & mode <> x86.mode\r
 393                 jno     addressing_prefix_ok\r
 394                 check   mode = 64 | (mode = 16 & x86.mode = 64)\r
 395                 jno     store_addressing_prefix\r
 396                 asmcmd  =err 'illegal addressing mode'\r
 397             store_addressing_prefix:\r
 398                 asmcmd  =db 67h\r
 399             addressing_prefix_ok:\r
 400 \r
 401                 compute evex, vex_mpw\r
 402                 compute evex_flags, evex_f\r
 403 \r
 404                 check   evex_b\r
 405                 jno     evex_L'L\r
 406                 compute evex, evex or evex_b shl 20\r
 407             evex_L'L:\r
 408                 check   mod = 11b & evex_b & rounding >= 0\r
 409                 jyes    evex_rounding\r
 410                 check   vsize = 64\r
 411                 jyes    evex_L'\r
 412                 check   evex_flags and EVEX_VL & AVX512VL = 0\r
 413                 jno     evex_L\r
 414                 compute evex_flags, evex_flags or EVEX_FORBIDDEN\r
 415             evex_L:\r
 416                 check   vsize = 32\r
 417                 jno     evex_mask\r
 418                 compute evex, evex or 1 shl 21\r
 419                 jump    evex_mask\r
 420             evex_L':\r
 421                 compute evex, evex or 1 shl 22\r
 422                 jump    evex_mask\r
 423             evex_rounding:\r
 424                 compute evex, evex or rounding shl 21\r
 425 \r
 426             evex_mask:\r
 427                 check   mask\r
 428                 jno     evex_X\r
 429                 compute evex, evex or mask shl 16\r
 430 \r
 431             evex_X:\r
 432                 check   rm and 10000b | (mod <> 11b & mode > 16 & rm = 4 & index and 1000b)\r
 433                 jno     evex_B\r
 434                 compute evex, evex or 1 shl 6\r
 435             evex_B:\r
 436                 check   rm and 1000b | (mod <> 11b & mode > 16 & rm = 4 & base and 1000b)\r
 437                 jno     evex_R'\r
 438                 compute evex, evex or 1 shl 5\r
 439             evex_R':\r
 440                 check   reg and 10000b\r
 441                 jno     evex_R\r
 442                 compute evex, evex or 1 shl 4\r
 443             evex_R:\r
 444                 check   reg and 1000b\r
 445                 jno     evex_V'\r
 446                 compute evex, evex or 1 shl 7\r
 447             evex_V':\r
 448                 check   vreg and 10000b\r
 449                 jno     evex_vvvv\r
 450                 compute evex, evex or 1 shl 19\r
 451             evex_vvvv:\r
 452                 compute evex, evex or (vreg and 1111b) shl 11\r
 453 \r
 454                 check   x86.mode < 64 & evex and 00001000_01000000_11110000b\r
 455                 jno     allowed\r
 456                 asmcmd  =err 'instruction requires long mode'\r
 457             allowed:\r
 458 \r
 459                 check   displacement_size\r
 460                 jno     no_displacement_compression\r
 461                 compute displacement, displacement\r
 462                 check   memsize\r
 463                 jyes    displacement_compression\r
 464                 compute memsize, vsize\r
 465             displacement_compression:\r
 466                 check   displacement relativeto 0 & displacement mod? memsize = 0\r
 467                 jno     displacement_incompressible\r
 468                 compute compressed_displacement, displacement / memsize\r
 469                 check   compressed_displacement < 80h & compressed_displacement >= -80h\r
 470                 jyes    displacement_compressed\r
 471                 check   compressed_displacement - 1 shl mode >= -80h & compressed_displacement < 1 shl mode\r
 472                 jno     displacement_incompressible\r
 473                 compute compressed_displacement, compressed_displacement - 1 shl mode\r
 474             displacement_compressed:\r
 475                 compute evex_displacement_size, 1\r
 476                 jump    choose_prefix\r
 477             displacement_incompressible:\r
 478                 compute evex_displacement_size, 4\r
 479                 check   mode > 16\r
 480                 jyes    choose_prefix\r
 481                 compute evex_displacement_size, 2\r
 482                 jump    choose_prefix\r
 483             no_displacement_compression:\r
 484                 compute evex_displacement_size, displacement_size\r
 485 \r
 486             choose_prefix:\r
 487                 check   evex_flags and EVEX_REQUIRED | evex and 11011111_00000000_00010000b | rm and 10000b\r
 488                 jyes    evex_required\r
 489                 check   ~ evex_flags and EVEX_FORBIDDEN & evex_displacement_size + 1 < displacement_size\r
 490                 jyes    evex\r
 491                 jump    vex\r
 492             evex_required:\r
 493                 check   evex_flags and EVEX_FORBIDDEN\r
 494                 jno     evex\r
 495                 asmcmd  =err 'invalid operand'\r
 496 \r
 497             vex:\r
 498                 local   byte2, byte3\r
 499                 compute vex, evex and 11111011_11111111b or (evex and 1 shl 21) shr (21-10)\r
 500                 check   vex and 10000000_01111111b <> 1\r
 501                 jyes    vex_3byte\r
 502             vex_2byte:\r
 503                 compute byte2, ((vex and 10000000b) or ((vex shr 8) and 1111111b)) xor 11111000b\r
 504                 asmcmd  =db 0C5h,byte2\r
 505                 jump    evex_done\r
 506             vex_3byte:\r
 507                 compute byte2, (vex and 11111111b) xor 11100000b\r
 508                 compute byte3, (vex shr 8) xor 01111000b\r
 509                 asmcmd  =db 0C4h,byte2,byte3\r
 510                 jump    evex_done\r
 511 \r
 512             evex:\r
 513                 compute evex, evex or 1 shl 10\r
 514                 check   evex_flags and EVEX_W1\r
 515                 jno     evex_4byte\r
 516                 compute evex, evex or 1 shl 15\r
 517             evex_4byte:\r
 518                 compute evex, 62h + (evex xor 00001000_01111000_11110000b) shl 8\r
 519                 asmcmd  =dd evex\r
 520                 check   mod <> 11b & mod <> 0 & evex_displacement_size > 0\r
 521                 jno     evex_done\r
 522                 compute displacement_size, evex_displacement_size\r
 523                 check   evex_displacement_size = 1\r
 524                 jyes    evex_compressed_displacement\r
 525                 compute mod, 2\r
 526                 jump    evex_done\r
 527             evex_compressed_displacement:\r
 528                 arrange sym, rm_operand.=displacement\r
 529                 publish sym, compressed_displacement\r
 530                 compute mod, 1\r
 531             evex_done:\r
 532 \r
 533                 local   modrm, sib\r
 534 \r
 535                 compute modrm, mod shl 6 + (reg and 111b) shl 3 + rm and 111b\r
 536                 asmcmd  =db opcode, modrm\r
 537 \r
 538                 check   mod <> 11b & rm = 4 & mode <> 16\r
 539                 jno     sib_ok\r
 540                 compute sib, (bsf scale) shl 6 + (index and 111b) shl 3 + base and 111b\r
 541                 asmcmd  =db sib\r
 542             sib_ok:\r
 543 \r
 544                 check   displacement_size = 1\r
 545                 jyes    displacement_8bit\r
 546                 check   displacement_size = 2\r
 547                 jyes    displacement_16bit\r
 548                 check   displacement_size = 4 | displacement_size = 8\r
 549                 jno     displacement_ok\r
 550 \r
 551                 check   auto_relative\r
 552                 jno     auto_relative_ok\r
 553                 check   imm_size < 8\r
 554                 jyes    adjust_auto_relative_displacement\r
 555                 compute displacement, displacement - ($ + 4 + 4)\r
 556                 jump    auto_relative_ok\r
 557               adjust_auto_relative_displacement:\r
 558                 compute displacement, displacement - ($ + 4 + imm_size)\r
 559               auto_relative_ok:\r
 560 \r
 561                 check   mode = 64 & displacement relativeto 0\r
 562                 jno     displacement_ready\r
 563                 check   displacement - 1 shl 64 >= -80000000h & displacement < 1 shl 64\r
 564                 jyes    adjust_displacement_wrap\r
 565                 check   displacement >= -80000000h & displacement < 80000000h\r
 566                 jyes    displacement_ready\r
 567                 asmcmd  =err 'address value out of signed range'\r
 568               adjust_displacement_wrap:\r
 569                 compute displacement, displacement - 1 shl 64\r
 570               displacement_ready:\r
 571 \r
 572                 arrange sym, rm_operand.=displacement\r
 573                 publish sym, displacement\r
 574 \r
 575                 asmcmd  =dd rm_operand.=displacement\r
 576 \r
 577                 jump    displacement_ok\r
 578             displacement_16bit:\r
 579                 asmcmd  =dw rm_operand.=displacement\r
 580                 jump    displacement_ok\r
 581             displacement_8bit:\r
 582                 asmcmd  =db rm_operand.=displacement\r
 583             displacement_ok:\r
 584 \r
 585                 check   imm_size = 1\r
 586                 jyes    immediate_8bit\r
 587                 check   imm_size = 2\r
 588                 jyes    immediate_16bit\r
 589                 check   imm_size = 4\r
 590                 jyes    immediate_32bit\r
 591                 check   imm_size = 8\r
 592                 jno     immediate_ok\r
 593                 asmcmd  =x86.=simm32 imm\r
 594                 jump    immediate_ok\r
 595             immediate_32bit:\r
 596                 asmcmd  =dd imm\r
 597                 jump    immediate_ok\r
 598             immediate_16bit:\r
 599                 asmcmd  =dw imm\r
 600                 jump    immediate_ok\r
 601             immediate_8bit:\r
 602                 asmcmd  =db imm\r
 603             immediate_ok:\r
 604 \r
 605         end calminstruction\r
 606 \r
 607         macro AVX_512.basic_instruction_bcst_er vex_mpw,evex_f,opcode,unit,dest,src,src_er&\r
 608                 AVX_512.parse_operand_k1z @dest,dest\r
 609                 AVX_512.parse_operand @src,src\r
 610                 match src2=,er, src_er\r
 611                         AVX_512.parse_operand @src2,src2\r
 612                         AVX_512.parse_er @src2,er\r
 613                 else\r
 614                         AVX_512.parse_operand_bcst @src2,src_er,unit\r
 615                 end match\r
 616                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 617                         if @src.size <> @dest.size | @src2.size and not @dest.size\r
 618                                 err 'operand sizes do not match'\r
 619                         end if\r
 620                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 621                 else\r
 622                         err 'invalid combination of operands'\r
 623                 end if\r
 624         end macro\r
 625 \r
 626         macro AVX_512.basic_instruction_bcst_sae vex_mpw,evex_f,opcode,unit,dest,src,src_sae&\r
 627                 AVX_512.parse_operand_k1z @dest,dest\r
 628                 AVX_512.parse_operand @src,src\r
 629                 match src2=,sae, src_sae\r
 630                         AVX_512.parse_operand @src2,src2\r
 631                         AVX_512.parse_sae @src2,sae\r
 632                 else\r
 633                         AVX_512.parse_operand_bcst @src2,src_sae,unit\r
 634                 end match\r
 635                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 636                         if @src.size <> @dest.size | @src2.size and not @dest.size\r
 637                                 err 'operand sizes do not match'\r
 638                         end if\r
 639                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 640                 else\r
 641                         err 'invalid combination of operands'\r
 642                 end if\r
 643         end macro\r
 644 \r
 645         macro AVX_512.basic_instruction_bcst_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&\r
 646                 AVX_512.parse_operand_k1z @dest,dest\r
 647                 AVX_512.parse_operand @src,src\r
 648                 AVX_512.parse_operand_bcst @src2,src2,unit\r
 649                 match sae=,imm, aux\r
 650                         AVX_512.parse_sae @src2,sae\r
 651                         x86.parse_operand @aux,imm\r
 652                 else\r
 653                         x86.parse_operand @aux,aux\r
 654                 end match\r
 655                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
 656                         if @src.size <> @dest.size | @src2.size and not @dest.size | @aux.size and not 1\r
 657                                 err 'operand sizes do not match'\r
 658                         end if\r
 659                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
 660                 else\r
 661                         err 'invalid combination of operands'\r
 662                 end if\r
 663         end macro\r
 664 \r
 665         macro AVX_512.basic_instruction_bcst vex_mpw,evex_f,opcode,unit,dest,src,src2\r
 666                 AVX_512.parse_operand_k1z @dest,dest\r
 667                 AVX_512.parse_operand @src,src\r
 668                 AVX_512.parse_operand_bcst @src2,src2,unit\r
 669                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 670                         if @src.size <> @dest.size | @src2.size and not @dest.size\r
 671                                 err 'operand sizes do not match'\r
 672                         end if\r
 673                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 674                 else\r
 675                         err 'invalid combination of operands'\r
 676                 end if\r
 677         end macro\r
 678 \r
 679         macro AVX_512.basic_instruction_bcst_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux\r
 680                 AVX_512.parse_operand_k1z @dest,dest\r
 681                 AVX_512.parse_operand @src,src\r
 682                 AVX_512.parse_operand_bcst @src2,src2,unit\r
 683                 x86.parse_operand @aux,aux\r
 684                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
 685                         if @aux.size and not 1\r
 686                                 err 'invalid operand size'\r
 687                         else if @src.size <> @dest.size | @src2.size and not @dest.size\r
 688                                 err 'operand sizes do not match'\r
 689                         end if\r
 690                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
 691                 else\r
 692                         err 'invalid combination of operands'\r
 693                 end if\r
 694         end macro\r
 695 \r
 696         macro AVX_512.basic_instruction_er vex_mpw,evex_f,opcode,unit,dest,src,src_er&\r
 697                 AVX_512.parse_operand_k1z @dest,dest\r
 698                 AVX_512.parse_operand @src,src\r
 699                 match src2=,er, src_er\r
 700                         AVX_512.parse_operand @src2,src2\r
 701                         AVX_512.parse_er @src2,er,(unit-1) and not 15 + 16\r
 702                 else\r
 703                         AVX_512.parse_operand @src2,src_er\r
 704                 end match\r
 705                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 706                         if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )\r
 707                                 err 'invalid operand size'\r
 708                         else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))\r
 709                                 err 'operand sizes do not match'\r
 710                         end if\r
 711                         @src2.memsize = unit\r
 712                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 713                 else\r
 714                         err 'invalid combination of operands'\r
 715                 end if\r
 716         end macro\r
 717 \r
 718         macro AVX_512.basic_instruction_sae vex_mpw,evex_f,opcode,unit,dest,src,src_sae&\r
 719                 AVX_512.parse_operand_k1z @dest,dest\r
 720                 AVX_512.parse_operand @src,src\r
 721                 match src2=,sae, src_sae\r
 722                         AVX_512.parse_operand @src2,src2\r
 723                         AVX_512.parse_sae @src2,sae\r
 724                 else\r
 725                         AVX_512.parse_operand @src2,src_sae\r
 726                 end match\r
 727                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 728                         if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )\r
 729                                 err 'invalid operand size'\r
 730                         else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))\r
 731                                 err 'operand sizes do not match'\r
 732                         end if\r
 733                         @src2.memsize = unit\r
 734                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 735                 else\r
 736                         err 'invalid combination of operands'\r
 737                 end if\r
 738         end macro\r
 739 \r
 740         macro AVX_512.basic_instruction_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&\r
 741                 AVX_512.parse_operand_k1z @dest,dest\r
 742                 AVX_512.parse_operand @src,src\r
 743                 AVX_512.parse_operand @src2,src2\r
 744                 match sae=,imm, aux\r
 745                         AVX_512.parse_sae @src2,sae\r
 746                         x86.parse_operand @aux,imm\r
 747                 else\r
 748                         x86.parse_operand @aux,aux\r
 749                 end match\r
 750                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
 751                         if ( unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) ) ) | @aux.size and not 1\r
 752                                 err 'invalid operand size'\r
 753                         else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))\r
 754                                 err 'operand sizes do not match'\r
 755                         end if\r
 756                         @src2.memsize = unit\r
 757                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
 758                 else\r
 759                         err 'invalid combination of operands'\r
 760                 end if\r
 761         end macro\r
 762 \r
 763         macro AVX_512.basic_instruction vex_mpw,evex_f,opcode,unit,dest,src,src2\r
 764                 AVX_512.parse_operand_k1z @dest,dest\r
 765                 AVX_512.parse_operand @src,src\r
 766                 AVX_512.parse_operand @src2,src2\r
 767                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
 768                         if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )\r
 769                                 err 'invalid operand size'\r
 770                         else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))\r
 771                                 err 'operand sizes do not match'\r
 772                         end if\r
 773                         @src2.memsize = unit\r
 774                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
 775                 else\r
 776                         err 'invalid combination of operands'\r
 777                 end if\r
 778         end macro\r
 779 \r
 780         macro AVX_512.basic_instruction_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&\r
 781                 AVX_512.parse_operand_k1z @dest,dest\r
 782                 AVX_512.parse_operand @src,src\r
 783                 AVX_512.parse_operand @src2,src2\r
 784                 x86.parse_operand @aux,aux\r
 785                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
 786                         if ( unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) ) ) | @aux.size and not 1\r
 787                                 err 'invalid operand size'\r
 788                         else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))\r
 789                                 err 'operand sizes do not match'\r
 790                         end if\r
 791                         @src2.memsize = unit\r
 792                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
 793                 else\r
 794                         err 'invalid combination of operands'\r
 795                 end if\r
 796         end macro\r
 797 \r
 798         macro AVX_512.single_source_instruction_bcst_er vex_mpw,evex_f,opcode,unit,dest,src_er&\r
 799                 AVX_512.parse_operand_k1z @dest,dest\r
 800                 match src=,er, src_er\r
 801                         AVX_512.parse_operand @src,src\r
 802                         AVX_512.parse_er @src,er\r
 803                 else\r
 804                         AVX_512.parse_operand_bcst @src,src_er,unit\r
 805                 end match\r
 806                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
 807                         if @src.size and not @dest.size\r
 808                                 err 'operand sizes do not match'\r
 809                         end if\r
 810                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
 811                 else\r
 812                         err 'invalid combination of operands'\r
 813                 end if\r
 814         end macro\r
 815 \r
 816         macro AVX_512.single_source_instruction_bcst_sae vex_mpw,evex_f,opcode,unit,dest,src_sae&\r
 817                 AVX_512.parse_operand_k1z @dest,dest\r
 818                 match src=,sae, src_sae\r
 819                         AVX_512.parse_operand @src,src\r
 820                         AVX_512.parse_sae @src,sae\r
 821                 else\r
 822                         AVX_512.parse_operand_bcst @src,src_sae,unit\r
 823                 end match\r
 824                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
 825                         if @src.size and not @dest.size\r
 826                                 err 'operand sizes do not match'\r
 827                         end if\r
 828                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
 829                 else\r
 830                         err 'invalid combination of operands'\r
 831                 end if\r
 832         end macro\r
 833 \r
 834         macro AVX_512.single_source_instruction_bcst_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,aux&\r
 835                 AVX_512.parse_operand_k1z @dest,dest\r
 836                 AVX_512.parse_operand_bcst @src,src,unit\r
 837                 match sae=,imm, aux\r
 838                         AVX_512.parse_sae @src,sae\r
 839                         x86.parse_operand @aux,imm\r
 840                 else\r
 841                         x86.parse_operand @aux,aux\r
 842                 end match\r
 843                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
 844                         if @aux.size and not 1\r
 845                                 err 'invalid operand size'\r
 846                         else if @src.size and not @dest.size\r
 847                                 err 'operand sizes do not match'\r
 848                         end if\r
 849                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm,,1,@aux.imm\r
 850                 else\r
 851                         err 'invalid combination of operands'\r
 852                 end if\r
 853         end macro\r
 854 \r
 855         macro AVX_512.single_source_instruction_bcst vex_mpw,evex_f,opcode,unit,dest,src&\r
 856                 AVX_512.parse_operand_k1z @dest,dest\r
 857                 AVX_512.parse_operand_bcst @src,src,unit\r
 858                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
 859                         if @src.size and not @dest.size\r
 860                                 err 'operand sizes do not match'\r
 861                         end if\r
 862                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
 863                 else\r
 864                         err 'invalid combination of operands'\r
 865                 end if\r
 866         end macro\r
 867 \r
 868         macro AVX_512.single_source_instruction vex_mpw,evex_f,opcode,unit,dest,src\r
 869                 AVX_512.parse_operand_k1z @dest,dest\r
 870                 AVX_512.parse_operand @src,src\r
 871                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
 872                         if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src.type = 'mem' & @src.size and not unit) )\r
 873                                 err 'invalid operand size'\r
 874                         else if @src.size and not @dest.size & (unit = 0 | @src.type = 'mmreg')\r
 875                                 err 'operand sizes do not match'\r
 876                         end if\r
 877                         @src.memsize = unit\r
 878                         AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
 879                 else\r
 880                         err 'invalid combination of operands'\r
 881                 end if\r
 882         end macro\r
 883 \r
 884         iterate <instr,opcode>, add,58h, mul,59h, sub,5Ch, div,5Eh\r
 885 \r
 886                 macro v#instr#pd? dest*,src*,src2*&\r
 887                         AVX_512.basic_instruction_bcst_er VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
 888                 end macro\r
 889 \r
 890                 macro v#instr#ps? dest*,src*,src2*&\r
 891                         AVX_512.basic_instruction_bcst_er VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
 892                 end macro\r
 893 \r
 894                 macro v#instr#sd? dest*,src*,src2*&\r
 895                         AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,opcode,8,dest,src,src2\r
 896                 end macro\r
 897 \r
 898                 macro v#instr#ss? dest*,src*,src2*&\r
 899                         AVX_512.basic_instruction_er VEX_F3_0F_W0,EVEX_AS_VEX,opcode,4,dest,src,src2\r
 900                 end macro\r
 901 \r
 902         end iterate\r
 903 \r
 904         iterate <instr,opcode>, min,5Dh, max,5Fh\r
 905 \r
 906                 macro v#instr#pd? dest*,src*,src2*&\r
 907                         AVX_512.basic_instruction_bcst_sae VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
 908                 end macro\r
 909 \r
 910                 macro v#instr#ps? dest*,src*,src2*&\r
 911                         AVX_512.basic_instruction_bcst_sae VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
 912                 end macro\r
 913 \r
 914                 macro v#instr#sd? dest*,src*,src2*&\r
 915                         AVX_512.basic_instruction_sae VEX_F2_0F_W0,EVEX_W1,opcode,8,dest,src,src2\r
 916                 end macro\r
 917 \r
 918                 macro v#instr#ss? dest*,src*,src2*&\r
 919                         AVX_512.basic_instruction_sae VEX_F3_0F_W0,EVEX_AS_VEX,opcode,4,dest,src,src2\r
 920                 end macro\r
 921 \r
 922         end iterate\r
 923 \r
 924         iterate <instr,opcode>, unpckh,15h, unpckl,14h\r
 925 \r
 926                 macro v#instr#pd? dest*,src*,src2*&\r
 927                         AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
 928                 end macro\r
 929 \r
 930                 macro v#instr#ps? dest*,src*,src2*&\r
 931                         AVX_512.basic_instruction_bcst VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
 932                 end macro\r
 933 \r
 934         end iterate\r
 935 \r
 936         macro vsqrtpd? dest*,src*&\r
 937                 AVX_512.single_source_instruction_bcst_er VEX_66_0F_W0,EVEX_W1+EVEX_VL,51h,8,dest,src\r
 938         end macro\r
 939 \r
 940         macro vsqrtps? dest*,src*&\r
 941                 AVX_512.single_source_instruction_bcst_er VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,51h,4,dest,src\r
 942         end macro\r
 943 \r
 944         macro vsqrtsd? dest*,src*,src2*&\r
 945                 AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,51h,8,dest,src,src2\r
 946         end macro\r
 947 \r
 948         macro vsqrtss? dest*,src*,src2*&\r
 949                 AVX_512.basic_instruction_er VEX_F3_0F_W0,EVEX_AS_VEX,51h,4,dest,src,src2\r
 950         end macro\r
 951 \r
 952         macro vshufpd? dest*,src*,src2*,aux*&\r
 953                 AVX_512.basic_instruction_bcst_imm8 VEX_66_0F_W0,EVEX_W1+EVEX_VL,0C6h,8,dest,src,src2,aux\r
 954         end macro\r
 955 \r
 956         macro vshufps? dest*,src*,src2*,aux*&\r
 957                 AVX_512.basic_instruction_bcst_imm8 VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,0C6h,4,dest,src,src2,aux\r
 958         end macro\r
 959 \r
 960         macro vbroadcastss? dest*,src*\r
 961                 AVX_512.parse_operand_k1z @dest,dest\r
 962                 AVX_512.parse_operand @src,src\r
 963                 if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
 964                         if (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not 4)\r
 965                                 err 'invalid operand size'\r
 966                         end if\r
 967                         @src2.memsize = 4\r
 968                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,18h,@src,@dest.mask,@dest.rm\r
 969                 else\r
 970                         err 'invalid combination of operands'\r
 971                 end if\r
 972         end macro\r
 973 \r
 974         macro vbroadcastsd? dest*,src*\r
 975                 AVX_512.parse_operand_k1z @dest,dest\r
 976                 AVX_512.parse_operand @src,src\r
 977                 if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
 978                         if @dest.size = 16 | (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not 8)\r
 979                                 err 'invalid operand size'\r
 980                         end if\r
 981                         @src.memsize = 8\r
 982                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_W1+EVEX_VL,19h,@src,@dest.mask,@dest.rm\r
 983                 else\r
 984                         err 'invalid combination of operands'\r
 985                 end if\r
 986         end macro\r
 987 \r
 988         iterate <instr,opcode,opcode_g,msize>, vpbroadcastd,58h,7Ch,4, vpbroadcastq,59h,7Ch,8\r
 989 \r
 990                 macro instr? dest*,src*\r
 991                         AVX_512.parse_operand_k1z @dest,dest\r
 992                         AVX_512.parse_operand @src,src\r
 993                         if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
 994                                 if (@src.type='mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not msize)\r
 995                                         err 'invalid operand size'\r
 996                                 end if\r
 997                                 @src.memsize = msize\r
 998                                 AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX,opcode,@src,@dest.mask,@dest.rm\r
 999                         else if @dest.type = 'mmreg' & @src.type = 'reg'\r
1000                                 if @src.size <> msize & (@src.size <> 4 | msize = 8)\r
1001                                         err 'invalid operand size'\r
1002                                 end if\r
1003                                 @src.memsize = msize\r
1004                                 if msize = 8\r
1005                                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode_g,@src,@dest.mask,@dest.rm\r
1006                                 else\r
1007                                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode_g,@src,@dest.mask,@dest.rm\r
1008                                 end if\r
1009                         else\r
1010                                 err 'invalid combination of operands'\r
1011                         end if\r
1012                 end macro\r
1013 \r
1014         end iterate\r
1015 \r
1016         iterate <instr,vex_mpw,opcode,msize>, vbroadcastf32x4,VEX_66_0F38_W0,1Ah,16, vbroadcastf64x4,VEX_66_0F38_W1,1Bh,32, \\r
1017                                               vbroadcasti32x4,VEX_66_0F38_W0,5Ah,16, vbroadcasti64x4,VEX_66_0F38_W1,5Bh,32\r
1018 \r
1019                 macro instr? dest*,src*\r
1020                         AVX_512.parse_operand_k1z @dest,dest\r
1021                         AVX_512.parse_operand @src,src\r
1022                         if @dest.type = 'mmreg' & @src.type = 'mem'\r
1023                                 if @dest.size <= msize | @src.size and not msize\r
1024                                         err 'invalid operand size'\r
1025                                 end if\r
1026                                 @src.memsize = msize\r
1027                                 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
1028                         else\r
1029                                 err 'invalid combination of operands'\r
1030                         end if\r
1031                 end macro\r
1032 \r
1033         end iterate\r
1034 \r
1035         iterate <instr,vex_mpw,opcode,unit>, vshuff32x4,VEX_66_0F3A_W0,23h,4, vshuff64x2,VEX_66_0F3A_W1,23h,4, \\r
1036                                              vshufi32x4,VEX_66_0F3A_W0,43h,4, vshufi64x2,VEX_66_0F3A_W1,43h,4\r
1037 \r
1038                 macro instr? dest*,src*,src2*,aux*\r
1039                         AVX_512.parse_operand_k1z @dest,dest\r
1040                         AVX_512.parse_operand @src,src\r
1041                         AVX_512.parse_operand_bcst @src2,src2,unit\r
1042                         x86.parse_operand @aux,aux\r
1043                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
1044                                 if @dest.size < 32 | @aux.size and not 1\r
1045                                         err 'invalid operand size'\r
1046                                 else if @src.size <> @dest.size | @src2.size and not @dest.size\r
1047                                         err 'operand sizes do not match'\r
1048                                 end if\r
1049                                 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1050                         else\r
1051                                 err 'invalid combination of operands'\r
1052                         end if\r
1053                 end macro\r
1054 \r
1055         end iterate\r
1056 \r
1057         macro vextractps? dest*,src*,aux*\r
1058                 AVX_512.parse_operand @dest,dest\r
1059                 AVX_512.parse_operand @src,src\r
1060                 x86.parse_operand @aux,aux\r
1061                 if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'\r
1062                         if @dest.size and not 4 | @src.size <> 16 | @aux.size and not 1\r
1063                                 err 'invalid operand size'\r
1064                         end if\r
1065                         @dest.memsize = 4\r
1066                         AVX_512.store_instruction 16,VEX_66_0F3A_W0,EVEX_AS_VEX,17h,@dest,0,@src.rm,,1,@aux.imm\r
1067                 else\r
1068                         err 'invalid combination of operands'\r
1069                 end if\r
1070         end macro\r
1071 \r
1072         macro vinsertps? dest*,src*,src2*,aux*\r
1073                 AVX_512.parse_operand @dest,dest\r
1074                 AVX_512.parse_operand @src,src\r
1075                 AVX_512.parse_operand @src2,src2\r
1076                 x86.parse_operand @aux,aux\r
1077                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mmreg' | @src2.type = 'mem') & @aux.type = 'imm'\r
1078                         if @dest.size <> 16 | @src.size <> 16 | (@src2.type = 'mmreg' & @src2.size <> 16) | (@src2.type = 'mem' & @src2.size and not 4) | @aux.size and not 1\r
1079                                 err 'invalid operand size'\r
1080                         end if\r
1081                         @src2.memsize = 4\r
1082                         AVX_512.store_instruction 16,VEX_66_0F3A_W0,EVEX_AS_VEX,21h,@src2,0,@dest.rm,@src.rm,1,@aux.imm\r
1083                 else\r
1084                         err 'invalid combination of operands'\r
1085                 end if\r
1086         end macro\r
1087 \r
1088         iterate <instr,vex_mpw,opcode,msize>, vextractf32x4,VEX_66_0F3A_W0,19h,16, vextractf64x4,VEX_66_0F3A_W1,1Bh,32, \\r
1089                                               vextracti32x4,VEX_66_0F3A_W0,39h,16, vextracti64x4,VEX_66_0F3A_W1,3Bh,32\r
1090 \r
1091                 macro instr? dest*,src*,aux*\r
1092                         AVX_512.parse_operand_k1z @dest,dest\r
1093                         AVX_512.parse_operand @src,src\r
1094                         x86.parse_operand @aux,aux\r
1095                         if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'\r
1096                                 if @dest.size and not msize | @src.size <= msize | @aux.size and not 1\r
1097                                         err 'invalid operand size'\r
1098                                 end if\r
1099                                 @dest.memsize = msize\r
1100                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm,,1,@aux.imm\r
1101                         else\r
1102                                 err 'invalid combination of operands'\r
1103                         end if\r
1104                 end macro\r
1105 \r
1106         end iterate\r
1107 \r
1108         iterate <instr,vex_mpw,opcode,msize>, vinsertf32x4,VEX_66_0F3A_W0,18h,16, vinsertf64x4,VEX_66_0F3A_W1,1Ah,32, \\r
1109                                               vinserti32x4,VEX_66_0F3A_W0,38h,16, vinserti64x4,VEX_66_0F3A_W1,3Ah,32\r
1110 \r
1111                 macro instr? dest*,src*,src2*,aux*\r
1112                         AVX_512.parse_operand_k1z @dest,dest\r
1113                         AVX_512.parse_operand @src,src\r
1114                         AVX_512.parse_operand @src2,src2\r
1115                         x86.parse_operand @aux,aux\r
1116                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mmreg' | @src2.type = 'mem') & @aux.type = 'imm'\r
1117                                 if @dest.size <= msize | @src.size <= msize | @src2.size and not msize | @aux.size and not 1\r
1118                                         err 'invalid operand size'\r
1119                                 end if\r
1120                                 @src2.memsize = msize\r
1121                                 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1122                         else\r
1123                                 err 'invalid combination of operands'\r
1124                         end if\r
1125                 end macro\r
1126 \r
1127         end iterate\r
1128 \r
1129         iterate <instr,vex_mpw,evex_mpw,unit>, vcmpps,VEX_0F_W0,VEX_0F_W0,4, vcmppd,VEX_66_0F_W0,VEX_66_0F_W1,8\r
1130 \r
1131                 macro instr? dest*,src*,src2*,aux*&\r
1132                         AVX_512.parse_operand_k1 @dest,dest\r
1133                         AVX_512.parse_operand @src,src\r
1134                         AVX_512.parse_operand_bcst @src2,src2,unit\r
1135                         match sae=,imm, aux\r
1136                                 AVX_512.parse_sae @src2,sae\r
1137                                 x86.parse_operand @aux,imm\r
1138                         else\r
1139                                 x86.parse_operand @aux,aux\r
1140                         end match\r
1141                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
1142                                 if @aux.size and not 1\r
1143                                         err 'invalid operand size'\r
1144                                 else if @src.size <> @dest.size | @src2.size and not @dest.size\r
1145                                         err 'operand sizes do not match'\r
1146                                 end if\r
1147                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_FORBIDDEN,0C2h,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1148                         else if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
1149                                 if @aux.size and not 1\r
1150                                         err 'invalid operand size'\r
1151                                 else if @src2.size and not @src.size\r
1152                                         err 'operand sizes do not match'\r
1153                                 end if\r
1154                                 AVX_512.store_instruction @src.size,evex_mpw,EVEX_REQUIRED+EVEX_VL,0C2h,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1155                         else\r
1156                                 err 'invalid combination of operands'\r
1157                         end if\r
1158                 end macro\r
1159 \r
1160         end iterate\r
1161 \r
1162         iterate <instr,vex_mpw,evex_mpw,unit>, vcmpss,VEX_F3_0F_W0,VEX_F3_0F_W0,4, vcmpsd,VEX_F2_0F_W0,VEX_F2_0F_W1,8\r
1163 \r
1164                 macro instr? dest*,src*,src2*,aux*&\r
1165                         AVX_512.parse_operand_k1 @dest,dest\r
1166                         AVX_512.parse_operand @src,src\r
1167                         AVX_512.parse_operand @src2,src2\r
1168                         match sae=,imm, aux\r
1169                                 AVX_512.parse_sae @src2,sae\r
1170                                 x86.parse_operand @aux,imm\r
1171                         else\r
1172                                 x86.parse_operand @aux,aux\r
1173                         end match\r
1174                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
1175                                 if @dest.size <> 16 | (@src2.type = 'mem' & @src2.size and not unit)\r
1176                                         err 'invalid operand size'\r
1177                                 else if @dest.size <> @src.size | (@src2.type = 'mmreg' & @src2.size <> @dest.size)\r
1178                                         err 'operand sizes do not match'\r
1179                                 end if\r
1180                                 @src2.memsize = unit\r
1181                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_FORBIDDEN,0C2h,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1182                         else if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
1183                                 if @src.size <> 16 | (@src2.type = 'mem' & @src2.size and not unit) | @aux.size and not 1\r
1184                                         err 'invalid operand size'\r
1185                                 else if @src2.type = 'mmreg' & @src2.size <> @src.size\r
1186                                         err 'operand sizes do not match'\r
1187                                 end if\r
1188                                 @src2.memsize = unit\r
1189                                 AVX_512.store_instruction @src.size,evex_mpw,EVEX_REQUIRED,0C2h,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
1190                         else\r
1191                                 err 'invalid combination of operands'\r
1192                         end if\r
1193                 end macro\r
1194 \r
1195         end iterate\r
1196 \r
1197         iterate <cond,code>, eq,0, lt,1, le,2, unord,3, neq,4, nlt,5, nle,6, ord,7, \\r
1198                              eq_uq,8, nge,9, ngt,0Ah, false,0Bh, neq_qq,0Ch, ge,0Dh, gt,0Eh, true,0Fh, \\r
1199                              eq_os,10h, lt_oq,11h, le_oq,12h, unord_s,13h, neq_us,14h, nlt_uq,15h, nle_uq,16h, ord_s,17h, \\r
1200                              eq_us,18h, nge_uq,19h, ngt_uq,1Ah, false_os,1Bh, neq_os,1Ch, ge_oq,1Dh, gt_oq,1Eh, true_us,1Fh\r
1201 \r
1202                 macro vcmp#cond#pd? dest*,src*,src2*&\r
1203                         vcmppd dest,src,src2,code\r
1204                 end macro\r
1205 \r
1206                 macro vcmp#cond#ps? dest*,src*,src2*&\r
1207                         vcmpps dest,src,src2,code\r
1208                 end macro\r
1209 \r
1210                 macro vcmp#cond#sd? dest*,src*,src2*&\r
1211                         vcmpsd dest,src,src2,code\r
1212                 end macro\r
1213 \r
1214                 macro vcmp#cond#ss? dest*,src*,src2*&\r
1215                         vcmpss dest,src,src2,code\r
1216                 end macro\r
1217 \r
1218         end iterate\r
1219 \r
1220         iterate <instr,vex_mpw,evex_f,opcode,unit>, vcomiss,VEX_0F_W0,EVEX_AS_VEX,2Fh,4, vcomisd,VEX_66_0F_W0,EVEX_W1,2Fh,8, vucomiss,VEX_0F_W0,EVEX_AS_VEX,2Eh,4, vucomisd,VEX_66_0F_W0,EVEX_W1,2Eh,8\r
1221 \r
1222                 macro instr? dest*,src_sae*&\r
1223                         AVX_512.parse_operand_k1z @dest,dest\r
1224                         match src=,sae, src_sae\r
1225                                 AVX_512.parse_operand @src,src\r
1226                                 AVX_512.parse_sae @src,sae\r
1227                         else\r
1228                                 AVX_512.parse_operand @src,src_sae\r
1229                         end match\r
1230                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1231                                 if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src.type = 'mem' & @src.size and not unit) )\r
1232                                         err 'invalid operand size'\r
1233                                 else if @src.size and not @dest.size & (unit = 0 | @src.type = 'mmreg')\r
1234                                         err 'operand sizes do not match'\r
1235                                 end if\r
1236                                 @src.memsize = unit\r
1237                                 AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
1238                         else\r
1239                                 err 'invalid combination of operands'\r
1240                         end if\r
1241                 end macro\r
1242 \r
1243         end iterate\r
1244 \r
1245         iterate <instr,opcode>, kandw,41h, kandnw,42h, knotw,44h, korw,45h, kxnorw,46h, kxorw,47h\r
1246 \r
1247                 macro instr? dest*,src*,src2*\r
1248                         AVX_512.parse_operand @dest,dest\r
1249                         AVX_512.parse_operand @src,src\r
1250                         AVX_512.parse_operand @src2,src2\r
1251                         if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'\r
1252                                 AVX.store_instruction 32,VEX_0F_W0,opcode,@src2,@dest.rm,@src.rm\r
1253                         else\r
1254                                 err 'invalid combination of operands'\r
1255                         end if\r
1256                 end macro\r
1257 \r
1258         end iterate\r
1259 \r
1260         iterate <instr,opcode>, knotw,44h, kortestw,98h\r
1261 \r
1262                 macro instr? dest*,src*\r
1263                         AVX_512.parse_operand @dest,dest\r
1264                         AVX_512.parse_operand @src,src\r
1265                         if @dest.type = 'maskreg' & @src.type = 'maskreg'\r
1266                                 AVX.store_instruction 16,VEX_0F_W0,opcode,@src,@dest.rm\r
1267                         else\r
1268                                 err 'invalid combination of operands'\r
1269                         end if\r
1270                 end macro\r
1271 \r
1272         end iterate\r
1273 \r
1274         macro kmovw? dest*,src*\r
1275                 AVX_512.parse_operand @dest,dest\r
1276                 AVX_512.parse_operand @src,src\r
1277                 if @dest.type = 'maskreg' & (@src.type = 'maskreg' | @src.type = 'mem')\r
1278                         if @src.type = 'mem' & @src.size and not 2\r
1279                                 err 'invalid operand size'\r
1280                         end if\r
1281                         AVX.store_instruction 16,VEX_0F_W0,90h,@src,@dest.rm\r
1282                 else if @dest.type = 'mem' & @src.type = 'maskreg'\r
1283                         if @dest.size and not 2\r
1284                                 err 'invalid operand size'\r
1285                         end if\r
1286                         AVX.store_instruction 16,VEX_0F_W0,91h,@dest,@src.rm\r
1287                 else if @dest.type = 'maskreg' & @src.type = 'reg'\r
1288                         if @src.size <> 4\r
1289                                 err 'invalid operand size'\r
1290                         end if\r
1291                         AVX.store_instruction 16,VEX_0F_W0,92h,@src,@dest.rm\r
1292                 else if @dest.type = 'reg' & @src.type = 'maskreg'\r
1293                         if @dest.size <> 4\r
1294                                 err 'invalid operand size'\r
1295                         end if\r
1296                         AVX.store_instruction 16,VEX_0F_W0,93h,@src,@dest.rm\r
1297                 else\r
1298                         err 'invalid combination of operands'\r
1299                 end if\r
1300         end macro\r
1301 \r
1302         iterate <instr,vex_mpw,opcode>, kshiftrw,VEX_66_0F3A_W1,30h, kshiftlw,VEX_66_0F3A_W1,32h\r
1303 \r
1304                 macro instr? dest*,src*,aux*\r
1305                         AVX_512.parse_operand @dest,dest\r
1306                         AVX_512.parse_operand @src,src\r
1307                         x86.parse_operand @aux,aux\r
1308                         if @dest.type = 'maskreg' & @src.type = 'maskreg' & @aux.type = 'imm'\r
1309                                 if @aux.size and not 1\r
1310                                         err 'invalid operand size'\r
1311                                 end if\r
1312                                 AVX.store_instruction 16,vex_mpw,opcode,@src,@dest.rm,,1,@aux.imm\r
1313                         else\r
1314                                 err 'invalid combination of operands'\r
1315                         end if\r
1316                 end macro\r
1317 \r
1318         end iterate\r
1319 \r
1320         macro kunpckbw? dest*,src*,src2*\r
1321                 AVX_512.parse_operand @dest,dest\r
1322                 AVX_512.parse_operand @src,src\r
1323                 AVX_512.parse_operand @src2,src2\r
1324                 if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'\r
1325                         AVX.store_instruction 32,VEX_66_0F_W0,4Bh,@src2,@dest.rm,@src.rm\r
1326                 else\r
1327                         err 'invalid combination of operands'\r
1328                 end if\r
1329         end macro\r
1330 \r
1331         iterate <instr,evex_f,opcode>, vcvtdq2pd,EVEX_AS_VEX+EVEX_VL,0E6h, vcvtudq2pd,EVEX_REQUIRED+EVEX_VL,7Ah\r
1332 \r
1333                 macro instr? dest*,src*\r
1334                         AVX_512.parse_operand_k1z @dest,dest\r
1335                         AVX_512.parse_operand_bcst @src,src,4\r
1336                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1337                                 if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)\r
1338                                         err 'invalid operand size'\r
1339                                 end if\r
1340                                 if @src.memsize = 0\r
1341                                         @src.memsize = @dest.size shr 1\r
1342                                 end if\r
1343                                 AVX_512.store_instruction @dest.size,VEX_F3_0F_W0,evex_f,opcode,@src,@dest.mask,@dest.rm\r
1344                         else\r
1345                                 err 'invalid combination of operands'\r
1346                         end if\r
1347                 end macro\r
1348 \r
1349         end iterate\r
1350 \r
1351         iterate <instr,vex_mpw,evex_f,opcode>, vcvtpd2dq,VEX_F2_0F_W0,EVEX_W1+EVEX_VL,0E6h, vcvtpd2ps,VEX_66_0F_W0,EVEX_W1+EVEX_VL,5Ah, vcvtpd2udq,VEX_0F_W1,EVEX_REQUIRED+EVEX_VL,79h\r
1352 \r
1353                 macro instr? dest*,src_er*&\r
1354                         AVX_512.parse_operand_k1z @dest,dest\r
1355                         match src=,er, src_er\r
1356                                 AVX_512.parse_operand @src,src\r
1357                                 AVX_512.parse_er @src,er\r
1358                         else\r
1359                                 AVX_512.parse_operand_bcst @src,src_er,8\r
1360                         end match\r
1361                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1362                                 if @src.size = 0\r
1363                                         if @dest.size = 16\r
1364                                                 err 'operand size not specified'\r
1365                                         else\r
1366                                                 @src.size = 64\r
1367                                         end if\r
1368                                 end if\r
1369                                 if (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size | @src.size > 64\r
1370                                         err 'invalid operand size'\r
1371                                 end if\r
1372                                 AVX_512.store_instruction @src.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
1373                         else\r
1374                                 err 'invalid combination of operands'\r
1375                         end if\r
1376                 end macro\r
1377 \r
1378         end iterate\r
1379 \r
1380         iterate <instr,vex_mpw,evex_f,opcode>, vcvtps2pd,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,5Ah\r
1381 \r
1382                 macro instr? dest*,src_sae*&\r
1383                         AVX_512.parse_operand_k1z @dest,dest\r
1384                         match src=,sae, src_sae\r
1385                                 AVX_512.parse_operand @src,src\r
1386                                 AVX_512.parse_sae @src,sae\r
1387                         else\r
1388                                 AVX_512.parse_operand_bcst @src,src_sae,4\r
1389                         end match\r
1390                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1391                                 if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)\r
1392                                         err 'invalid operand size'\r
1393                                 end if\r
1394                                 if @src.memsize = 0\r
1395                                         @src.memsize = @dest.size shr 1\r
1396                                 end if\r
1397                                 AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
1398                         else\r
1399                                 err 'invalid combination of operands'\r
1400                         end if\r
1401                 end macro\r
1402 \r
1403         end iterate\r
1404 \r
1405         iterate <instr,vex_mpw,evex_f,opcode>, vcvttpd2dq,VEX_66_0F_W0,EVEX_W1+EVEX_VL,0E6h, vcvttpd2udq,VEX_0F_W1,EVEX_REQUIRED+EVEX_VL,78h\r
1406 \r
1407                 macro instr? dest*,src_sae*&\r
1408                         AVX_512.parse_operand_k1z @dest,dest\r
1409                         match src=,sae, src_sae\r
1410                                 AVX_512.parse_operand @src,src\r
1411                                 AVX_512.parse_sae @src,sae\r
1412                         else\r
1413                                 AVX_512.parse_operand_bcst @src,src_sae,8\r
1414                         end match\r
1415                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1416                                 if @src.size = 0\r
1417                                         if @dest.size = 16\r
1418                                                 err 'operand size not specified'\r
1419                                         else\r
1420                                                 @src.size = 64\r
1421                                         end if\r
1422                                 end if\r
1423                                 if (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size | @src.size > 64\r
1424                                         err 'invalid operand size'\r
1425                                 end if\r
1426                                 AVX_512.store_instruction @src.size,vex_mpw,evex_f,opcode,@src,@dest.mask,@dest.rm\r
1427                         else\r
1428                                 err 'invalid combination of operands'\r
1429                         end if\r
1430                 end macro\r
1431 \r
1432         end iterate\r
1433 \r
1434         iterate <instr,vex_mpw,evex_f,opcode>, vcvtdq2ps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvtudq2ps,VEX_F2_0F_W0,EVEX_REQUIRED+EVEX_VL,7Ah, \\r
1435                                                vcvtps2dq,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvtps2udq,VEX_0F_W0,EVEX_REQUIRED+EVEX_VL,79h\r
1436 \r
1437                 macro instr? dest*,src*&\r
1438                         AVX_512.single_source_instruction_bcst_er vex_mpw,evex_f,opcode,4,dest,src\r
1439                 end macro\r
1440 \r
1441         end iterate\r
1442 \r
1443 \r
1444         iterate <instr,vex_mpw,evex_f,opcode>, vcvttps2dq,VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvttps2udq,VEX_0F_W0,EVEX_REQUIRED+EVEX_VL,78h\r
1445 \r
1446                 macro instr? dest*,src*&\r
1447                         AVX_512.single_source_instruction_bcst_sae vex_mpw,evex_f,opcode,4,dest,src\r
1448                 end macro\r
1449 \r
1450         end iterate\r
1451 \r
1452         macro vcvtph2ps? dest*,src_sae*&\r
1453                 AVX_512.parse_operand_k1z @dest,dest\r
1454                 match src=,sae, src_sae\r
1455                         AVX_512.parse_operand @src,src\r
1456                         AVX_512.parse_sae @src,sae\r
1457                 else\r
1458                         AVX_512.parse_operand @src,src_sae\r
1459                 end match\r
1460                 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1461                         if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)\r
1462                                 err 'invalid operand size'\r
1463                         end if\r
1464                         if @src.memsize = 0\r
1465                                 @src.memsize = @dest.size shr 1\r
1466                         end if\r
1467                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,13h,@src,@dest.mask,@dest.rm\r
1468                 else\r
1469                         err 'invalid combination of operands'\r
1470                 end if\r
1471         end macro\r
1472 \r
1473         macro vcvtps2ph? dest*,src*,aux*&\r
1474                 AVX_512.parse_operand_k1z @dest,dest\r
1475                 AVX_512.parse_operand @src,src\r
1476                 match sae=,imm, aux\r
1477                         AVX_512.parse_sae @src,sae\r
1478                         x86.parse_operand @aux,imm\r
1479                 else\r
1480                         x86.parse_operand @aux,aux\r
1481                 end match\r
1482                 if (@dest.type = 'mem' | @dest.type = 'mmreg') & @src.type = 'mmreg'\r
1483                         if (@dest.type = 'mem' & @dest.size and not (@src.size shr 1)) | (@dest.type = 'mmreg' & (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size)\r
1484                                 err 'invalid operand size'\r
1485                         end if\r
1486                         if @dest.memsize = 0\r
1487                                 @dest.memsize = @src.size shr 1\r
1488                         end if\r
1489                         AVX_512.store_instruction @src.size,VEX_66_0F3A_W0,EVEX_AS_VEX+EVEX_VL,1Dh,@dest,@dest.mask,@src.rm,,1,@aux.imm\r
1490                 else\r
1491                         err 'invalid combination of operands'\r
1492                 end if\r
1493         end macro\r
1494 \r
1495         iterate <instr,vex_mp,evex_f,opcode,msize>, vcvtsd2si,VEX_F2_0F,EVEX_AS_VEX,2Dh,8, vcvtss2si,VEX_F3_0F,EVEX_AS_VEX,2Dh,4, \\r
1496                                                     vcvtsd2usi,VEX_F2_0F,EVEX_REQUIRED,79h,8, vcvtss2usi,VEX_F3_0F,EVEX_REQUIRED,79h,4\r
1497 \r
1498                 macro instr? dest*,src_er*&\r
1499                         x86.parse_operand @dest,dest\r
1500                         match src=,er, src_er\r
1501                                 AVX_512.parse_operand @src,src\r
1502                                 AVX_512.parse_er @src,er,16\r
1503                         else\r
1504                                 AVX_512.parse_operand @src,src_er\r
1505                         end match\r
1506                         if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1507                                 if (@dest.size <> 4 & @dest.size <> 8) | (@src.type = 'mem' & @src.size and not msize) | (@src.type = 'mmreg' & @src.size <> 16)\r
1508                                         err 'invalid operand size'\r
1509                                 end if\r
1510                                 if @dest.size = 8\r
1511                                         if x86.mode < 64\r
1512                                                 err 'instruction requires long mode'\r
1513                                         end if\r
1514                                         AVX_512.store_instruction 16,vex_mp#_W1,evex_f,opcode,@src,0,@dest.rm\r
1515                                 else\r
1516                                         AVX_512.store_instruction 16,vex_mp#_W0,evex_f,opcode,@src,0,@dest.rm\r
1517                                 end if\r
1518                         else\r
1519                                 err 'invalid combination of operands'\r
1520                         end if\r
1521                 end macro\r
1522 \r
1523         end iterate\r
1524 \r
1525         iterate <instr,vex_mp,evex_f,opcode,msize>, vcvttsd2si,VEX_F2_0F,EVEX_AS_VEX,2Ch,8, vcvttss2si,VEX_F3_0F,EVEX_AS_VEX,2Ch,4, \\r
1526                                                     vcvttsd2usi,VEX_F2_0F,EVEX_REQUIRED,78h,8, vcvttss2usi,VEX_F3_0F,EVEX_REQUIRED,78h,4\r
1527 \r
1528                 macro instr? dest*,src_sae*&\r
1529                         x86.parse_operand @dest,dest\r
1530                         match src=,sae, src_sae\r
1531                                 AVX_512.parse_operand @src,src\r
1532                                 AVX_512.parse_sae @src,sae\r
1533                         else\r
1534                                 AVX_512.parse_operand @src,src_sae\r
1535                         end match\r
1536                         if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
1537                                 if (@dest.size <> 4 & @dest.size <> 8) | (@src.type = 'mem' & @src.size and not msize) | (@src.type = 'mmreg' & @src.size <> 16)\r
1538                                         err 'invalid operand size'\r
1539                                 end if\r
1540                                 if @dest.size = 8\r
1541                                         if x86.mode < 64\r
1542                                                 err 'instruction requires long mode'\r
1543                                         end if\r
1544                                         AVX_512.store_instruction 16,vex_mp#_W1,evex_f,opcode,@src,0,@dest.rm\r
1545                                 else\r
1546                                         AVX_512.store_instruction 16,vex_mp#_W0,evex_f,opcode,@src,0,@dest.rm\r
1547                                 end if\r
1548                         else\r
1549                                 err 'invalid combination of operands'\r
1550                         end if\r
1551                 end macro\r
1552 \r
1553         end iterate\r
1554 \r
1555         macro vcvtsd2ss? dest*,src*,src2*&\r
1556                 AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,5Ah,8,dest,src,src2\r
1557         end macro\r
1558 \r
1559         macro vcvtss2sd? dest*,src*,src2*&\r
1560                 AVX_512.basic_instruction_sae VEX_F3_0F_W0,EVEX_AS_VEX,5Ah,4,dest,src,src2\r
1561         end macro\r
1562 \r
1563         iterate <instr,evex_f,opcode>, vcvtsi2sd,EVEX_AS_VEX,2Ah, vcvtusi2sd,EVEX_REQUIRED,7Bh\r
1564 \r
1565                 macro vcvtsi2sd? dest*,src*,src_er*&\r
1566                         AVX_512.parse_operand @dest,dest\r
1567                         AVX_512.parse_operand @src,src\r
1568                         match src2=,er, src_er\r
1569                                 AVX_512.parse_operand @src2,src2\r
1570                                 AVX_512.parse_er @src2,er,8\r
1571                         else\r
1572                                 AVX_512.parse_operand @src2,src_er\r
1573                         end match\r
1574                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem')\r
1575                                 if @src.size = 0\r
1576                                         err ' operand size not specified'\r
1577                                 else if @dest.size <> 16 | @src.size <> 16 | (@src2.size <> 4 & @src2.size <> 8)\r
1578                                         err 'invalid operand size'\r
1579                                 end if\r
1580                                 if @src2.size = 8\r
1581                                         if x86.mode < 64\r
1582                                                 err 'instruction requires long mode'\r
1583                                         end if\r
1584                                         AVX_512.store_instruction 16,VEX_F2_0F_W1,evex_f,opcode,@src2,0,@dest.rm,@src.rm\r
1585                                 else\r
1586                                         AVX_512.store_instruction 16,VEX_F2_0F_W0,evex_f,opcode,@src2,0,@dest.rm,@src.rm\r
1587                                 end if\r
1588                         else\r
1589                                 err 'invalid combination of operands'\r
1590                         end if\r
1591                 end macro\r
1592 \r
1593         end iterate\r
1594 \r
1595         iterate <instr,evex_f,opcode>, vcvtsi2ss,EVEX_AS_VEX,2Ah, vcvtusi2ss,EVEX_REQUIRED,7Bh\r
1596 \r
1597                 macro vcvtsi2ss? dest*,src*,src_er*&\r
1598                         AVX_512.parse_operand @dest,dest\r
1599                         AVX_512.parse_operand @src,src\r
1600                         match src2=,er, src_er\r
1601                                 AVX_512.parse_operand @src2,src2\r
1602                                 AVX_512.parse_er @src2,er,@src2.size\r
1603                         else\r
1604                                 AVX_512.parse_operand @src2,src_er\r
1605                         end match\r
1606                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem')\r
1607                                 if @src.size = 0\r
1608                                         err ' operand size not specified'\r
1609                                 else if @dest.size <> 16 | @src.size <> 16 | (@src2.size <> 4 & @src2.size <> 8)\r
1610                                         err 'invalid operand size'\r
1611                                 end if\r
1612                                 if @src2.size = 8\r
1613                                         if x86.mode < 64\r
1614                                                 err 'instruction requires long mode'\r
1615                                         end if\r
1616                                         AVX_512.store_instruction 16,VEX_F3_0F_W1,evex_f,opcode,@src2,0,@dest.rm,@src.rm\r
1617                                 else\r
1618                                         AVX_512.store_instruction 16,VEX_F3_0F_W0,evex_f,opcode,@src2,0,@dest.rm,@src.rm\r
1619                                 end if\r
1620                         else\r
1621                                 err 'invalid combination of operands'\r
1622                         end if\r
1623                 end macro\r
1624 \r
1625         end iterate\r
1626 \r
1627         iterate <instr,vex_mpw,evex_f,opcode_rm,opcode_mr>, vmovapd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,28h,29h, vmovaps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,28h,29h, \\r
1628                                                             vmovupd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,10h,11h, vmovups,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,10h,11h, \\r
1629                                                             vmovdqa32,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, vmovdqa64,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, \\r
1630                                                             vmovdqu32,VEX_F3_0F_W0,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, vmovdqu64,VEX_F3_0F_W1,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh\r
1631 \r
1632                 macro instr? dest*,src*\r
1633                         AVX_512.parse_operand_k1z @dest,dest\r
1634                         AVX_512.parse_operand @src,src\r
1635                         if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
1636                                 if @src.size and not @dest.size\r
1637                                         err 'operand sizes do not match'\r
1638                                 end if\r
1639                                 AVX_512.store_instruction @dest.size,vex_mpw,evex_f,opcode_rm,@src,@dest.mask,@dest.rm\r
1640                         else if @dest.type = 'mem' & @src.type = 'mmreg'\r
1641                                 if @dest.size and not @src.size\r
1642                                         err 'operand sizes do not match'\r
1643                                 end if\r
1644                                 AVX_512.store_instruction @src.size,vex_mpw,evex_f,opcode_mr,@dest,@dest.mask,@src.rm\r
1645                         else\r
1646                                 err 'invalid combination of operands'\r
1647                         end if\r
1648                 end macro\r
1649 \r
1650         end iterate\r
1651 \r
1652         macro vmovd? dest*,src*\r
1653                 AVX_512.parse_operand @dest,dest\r
1654                 AVX_512.parse_operand @src,src\r
1655                 if @dest.type = 'mmreg' & (@src.type = 'reg' | @src.type = 'mem')\r
1656                         if @dest.size <> 16 | @src.size and not 4\r
1657                                 err 'invalid operand size'\r
1658                         end if\r
1659                         @src.memsize = 4\r
1660                         AVX_512.store_instruction 16,VEX_66_0F_W0,EVEX_AS_VEX,6Eh,@src,0,@dest.rm\r
1661                 else if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg'\r
1662                         if @dest.size and not 4 | @src.size <> 16\r
1663                                 err 'operand sizes do not match'\r
1664                         end if\r
1665                         @dest.memsize = 4\r
1666                         AVX_512.store_instruction 16,VEX_66_0F_W0,EVEX_AS_VEX,7Eh,@dest,0,@src.rm\r
1667                 else\r
1668                         err 'invalid combination of operands'\r
1669                 end if\r
1670         end macro\r
1671 \r
1672         macro vmovq? dest*,src*\r
1673                 AVX_512.parse_operand @dest,dest\r
1674                 AVX_512.parse_operand @src,src\r
1675                 if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
1676                         if @dest.size <> 16 | (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' and @src.size and not 8)\r
1677                                 err 'invalid operand size'\r
1678                         end if\r
1679                         @src.memsize = 8\r
1680                         AVX_512.store_instruction 16,VEX_F3_0F_W0,EVEX_W1,7Eh,@src,0,@dest.rm\r
1681                 else if @dest.type = 'mem' & @src.type = 'mmreg'\r
1682                         if @dest.size and not 8 | @src.size <> 16\r
1683                                 err 'invalid operand size'\r
1684                         end if\r
1685                         @dest.memsize = 8\r
1686                         AVX_512.store_instruction 16,VEX_66_0F_W0,EVEX_W1,0D6h,@dest,0,@src.rm\r
1687                 else if @dest.type = 'mmreg' & @src.type = 'reg'\r
1688                         if @dest.size <> 16 | @src.size <> 8\r
1689                                 err 'invalid operand size'\r
1690                         end if\r
1691                         if x86.mode < 64\r
1692                                 err 'instruction requires long mode'\r
1693                         end if\r
1694                         AVX_512.store_instruction 16,VEX_66_0F_W1,EVEX_W1,6Eh,@src,0,@dest.rm\r
1695                 else if @dest.type = 'reg' & @src.type = 'mmreg'\r
1696                         if @dest.size <> 8 | @src.size <> 16\r
1697                                 err 'invalid operand size'\r
1698                         end if\r
1699                         if x86.mode < 64\r
1700                                 err 'instruction requires long mode'\r
1701                         end if\r
1702                         AVX_512.store_instruction 16,VEX_66_0F_W1,EVEX_W1,7Eh,@dest,0,@src.rm\r
1703                 else\r
1704                         err 'invalid combination of operands'\r
1705                 end if\r
1706         end macro\r
1707 \r
1708         macro vmovddup? dest*,src*\r
1709                 AVX_512.parse_operand_k1z @dest,dest\r
1710                 AVX_512.parse_operand @src,src\r
1711                 if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
1712                         if @src.type = 'mem' & @dest.size = 16\r
1713                                 if @src.size and not 8\r
1714                                         err 'invalid operand size'\r
1715                                 end if\r
1716                                 @src.memsize = 8\r
1717                         else\r
1718                                 if @src.size and not @dest.size\r
1719                                         err 'operand sizes do not match'\r
1720                                 end if\r
1721                                 @src.memsize = @dest.size\r
1722                         end if\r
1723                         AVX_512.store_instruction @dest.size,VEX_F2_0F_W0,EVEX_W1+EVEX_VL,12h,@src,@dest.mask,@dest.rm\r
1724                 else\r
1725                         err 'invalid combination of operands'\r
1726                 end if\r
1727         end macro\r
1728 \r
1729         iterate <instr,opcode>, vmovhlps,12h, vmovlhps,16h\r
1730 \r
1731                 macro instr? dest*,src*,src2*\r
1732                         AVX_512.parse_operand @dest,dest\r
1733                         AVX_512.parse_operand @src,src\r
1734                         AVX_512.parse_operand @src2,src2\r
1735                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mmreg'\r
1736                                 if @dest.size <> 16\r
1737                                         err 'invalid operand size'\r
1738                                 else if @src.size <> @dest.size | @src2.size <> @dest.size\r
1739                                         err 'operand sizes do not match'\r
1740                                 end if\r
1741                                 AVX_512.store_instruction 16,VEX_0F_W0,EVEX_AS_VEX,opcode,@src2,0,@dest.rm,@src.rm\r
1742                         else\r
1743                                 err 'invalid combination of operands'\r
1744                         end if\r
1745                 end macro\r
1746 \r
1747         end iterate\r
1748 \r
1749         iterate <instr,vex_mpw,evex_f,opcode>, vmovhpd,VEX_66_0F_W0,EVEX_W1,16h, vmovhps,VEX_0F_W0,EVEX_AS_VEX,16h, vmovlpd,VEX_66_0F_W0,EVEX_W1,12h, vmovlps,VEX_0F_W0,EVEX_AS_VEX,12h\r
1750 \r
1751                 macro instr? dest*,src*,src2\r
1752                         AVX_512.parse_operand @dest,dest\r
1753                         AVX_512.parse_operand @src,src\r
1754                         match , src2\r
1755                                 if @dest.type = 'mem' & @src.type = 'mmreg'\r
1756                                         if @dest.size and not 8 | @src.size <> 16\r
1757                                                 err 'invalid operand size'\r
1758                                         end if\r
1759                                         @dest.memsize = 8\r
1760                                         AVX_512.store_instruction 16,vex_mpw,evex_f,opcode+1,@dest,0,@src.rm\r
1761                                 else\r
1762                                         err 'invalid combination of operands'\r
1763                                 end if\r
1764                         else\r
1765                                 AVX_512.parse_operand @src2,src2\r
1766                                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mem'\r
1767                                         if @dest.size <> 16 | @src.size <> 16 | @src2.size and not 8\r
1768                                                 err 'invalid operand size'\r
1769                                         end if\r
1770                                         @src2.memsize = 8\r
1771                                         AVX_512.store_instruction 16,vex_mpw,evex_f,opcode,@src2,0,@dest.rm,@src.rm\r
1772                                 else\r
1773                                         err 'invalid combination of operands'\r
1774                                 end if\r
1775                         end match\r
1776                 end macro\r
1777 \r
1778         end iterate\r
1779 \r
1780         iterate <instr,vex_mpw,evex_f,opcode>, vmovntdq,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,0E7h, vmovntpd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,2Bh, vmovntps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,2Bh\r
1781 \r
1782                 macro instr? dest*,src*\r
1783                         AVX_512.parse_operand @dest,dest\r
1784                         AVX_512.parse_operand @src,src\r
1785                         if @dest.type = 'mem' & @src.type = 'mmreg'\r
1786                                 if @dest.size and not @src.size\r
1787                                         err 'operand sizes do not match'\r
1788                                 end if\r
1789                                 AVX_512.store_instruction @src.size,vex_mpw,evex_f,opcode,@dest,0,@src.rm\r
1790                         else\r
1791                                 err 'invalid combination of operands'\r
1792                         end if\r
1793                 end macro\r
1794 \r
1795         end iterate\r
1796 \r
1797         macro vmovntdqa? dest*,src*\r
1798                 AVX_512.parse_operand @dest,dest\r
1799                 AVX_512.parse_operand @src,src\r
1800                 if @dest.type = 'mmreg' & @src.type = 'mem'\r
1801                         if @src.size and not @dest.size\r
1802                                 err 'operand sizes do not match'\r
1803                         end if\r
1804                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,2Ah,@src,0,@dest.rm\r
1805                 else\r
1806                         err 'invalid combination of operands'\r
1807                 end if\r
1808         end macro\r
1809 \r
1810         iterate <instr,vex_mpw,evex_f,msize>, vmovsd,VEX_F2_0F_W0,EVEX_W1,8, vmovss,VEX_F3_0F_W0,EVEX_AS_VEX,4\r
1811 \r
1812                 macro instr? dest*,src*,src2\r
1813                         AVX_512.parse_operand_k1z @dest,dest\r
1814                         AVX_512.parse_operand @src,src\r
1815                         match , src2\r
1816                                 if @dest.type = 'mmreg' & @src.type = 'mem'\r
1817                                         if @dest.size <> 16 | @src.size and not msize\r
1818                                                 err 'invalid operand size'\r
1819                                         end if\r
1820                                         @src.memsize = msize\r
1821                                         AVX_512.store_instruction 16,vex_mpw,evex_f,10h,@src,@dest.mask,@dest.rm\r
1822                                 else if @dest.type = 'mem' & @src.type = 'mmreg'\r
1823                                         if @dest.size and not msize | @src.size <> 16\r
1824                                                 err 'invalid operand size'\r
1825                                         end if\r
1826                                         @dest.memsize = msize\r
1827                                         AVX_512.store_instruction 16,vex_mpw,evex_f,11h,@dest,@dest.mask,@src.rm\r
1828                                 else\r
1829                                         err 'invalid combination of operands'\r
1830                                 end if\r
1831                         else\r
1832                                 AVX_512.parse_operand @src2,src2\r
1833                                 if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mmreg'\r
1834                                         if @dest.size <> 16 | @src.size <> 16 | @src2.size <> 16\r
1835                                                 err 'invalid operand size'\r
1836                                         end if\r
1837                                         AVX_512.store_instruction 16,vex_mpw,evex_f,10h,@src2,@dest.mask,@dest.rm,@src.rm\r
1838                                 else\r
1839                                         err 'invalid combination of operands'\r
1840                                 end if\r
1841                         end match\r
1842                 end macro\r
1843 \r
1844         end iterate\r
1845 \r
1846         macro vmovshdup? dest*,src*\r
1847                 AVX_512.single_source_instruction VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,16h,0,dest,src\r
1848         end macro\r
1849 \r
1850         macro vmovsldup? dest*,src*\r
1851                 AVX_512.single_source_instruction VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,12h,0,dest,src\r
1852         end macro\r
1853 \r
1854         iterate <instr,unit,evex_f,opcode_rrm,opcode_rri>, vpermilps,4,EVEX_AS_VEX+EVEX_VL,0Ch,4, vpermilpd,8,EVEX_W1+EVEX_VL,0Dh,5\r
1855 \r
1856                 macro instr? dest*,src*,src2*\r
1857                         AVX_512.parse_operand_k1z @dest,dest\r
1858                         AVX_512.parse_operand_bcst @src,src,unit\r
1859                         AVX_512.parse_operand_bcst @src2,src2,unit\r
1860                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
1861                                 if @src.size <> @dest.size | @src2.size and not @dest.size\r
1862                                         err 'operand sizes do not match'\r
1863                                 end if\r
1864                                 AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,evex_f,opcode_rrm,@src2,@dest.mask,@dest.rm,@src.rm\r
1865                         else if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @src2.type = 'imm'\r
1866                                 if @src2.size and not 1\r
1867                                         err 'invalid operand size'\r
1868                                 else if @src.size and not @dest.size\r
1869                                         err 'operand sizes do not match'\r
1870                                 end if\r
1871                                 AVX_512.store_instruction @dest.size,VEX_66_0F3A_W0,evex_f,opcode_rri,@src,@dest.mask,@dest.rm,,1,@src2.imm\r
1872                         else\r
1873                                 err 'invalid combination of operands'\r
1874                         end if\r
1875                 end macro\r
1876 \r
1877         end iterate\r
1878 \r
1879         iterate <instr,opcode>, vpaddd,0FEh, vpsubd,0FAh, vpunpckhdq,6Ah, vpunpckldq,62h\r
1880 \r
1881                 macro instr? dest*,src*,src2*\r
1882                         AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
1883                 end macro\r
1884 \r
1885         end iterate\r
1886 \r
1887         iterate <instr,opcode>, vpaddq,0D4h, vpmuludq,0F4h, vpsubq,0FBh, vpunpckhqdq,6Dh, vpunpcklqdq,6Ch\r
1888 \r
1889                 macro instr? dest*,src*,src2*\r
1890                         AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
1891                 end macro\r
1892 \r
1893         end iterate\r
1894 \r
1895         iterate <instr,opcode>, vpandd,0DBh, vpandnd,0DFh, vpord,0EBh, vpxord,0EFh\r
1896 \r
1897                 macro instr? dest*,src*,src2*\r
1898                         AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2\r
1899                 end macro\r
1900 \r
1901         end iterate\r
1902 \r
1903         iterate <instr,opcode>, vpandq,0DBh, vpandnq,0DFh, vporq,0EBh, vpxorq,0EFh\r
1904 \r
1905                 macro instr? dest*,src*,src2*\r
1906                         AVX_512.basic_instruction_bcst VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2\r
1907                 end macro\r
1908 \r
1909         end iterate\r
1910 \r
1911         iterate <instr,opcode>, vpmaxsd,3Dh, vpmaxud,3Fh, vpminsd,39h, vpminud,3Bh, vpmulld,40h\r
1912 \r
1913                 macro instr? dest*,src*,src2*\r
1914                         AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
1915                 end macro\r
1916 \r
1917         end iterate\r
1918 \r
1919         iterate <instr,opcode>, vpmuldq,28h\r
1920 \r
1921                 macro instr? dest*,src*,src2*\r
1922                         AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
1923                 end macro\r
1924 \r
1925         end iterate\r
1926 \r
1927         iterate <instr,opcode>, vpmuldq,28h, vpmaxsq,3Dh, vpmaxuq,3Fh, vpminsq,39h, vpminuq,3Bh, vpmullq,40h\r
1928 \r
1929                 macro instr? dest*,src*,src2*\r
1930                         AVX_512.basic_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2\r
1931                 end macro\r
1932 \r
1933         end iterate\r
1934 \r
1935         iterate <instr,opcode>, vpabsd,1Eh\r
1936 \r
1937                 macro instr? dest*,src*\r
1938                         AVX_512.single_source_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src\r
1939                 end macro\r
1940 \r
1941         end iterate\r
1942 \r
1943         iterate <instr,opcode>, vpabsq,1Fh\r
1944 \r
1945                 macro instr? dest*,src*\r
1946                         AVX_512.single_source_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src\r
1947                 end macro\r
1948 \r
1949         end iterate\r
1950 \r
1951         iterate <instr,vex_mpw>, vpshufd,VEX_66_0F_W0\r
1952 \r
1953                 macro instr? dest*,src*,aux*\r
1954                         AVX_512.parse_operand_k1z @dest,dest\r
1955                         AVX_512.parse_operand @src,src\r
1956                         x86.parse_operand @aux,aux\r
1957                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
1958                                 if @aux.size and not 1\r
1959                                         err 'invalid operand size'\r
1960                                 else if @src.size and not @dest.size\r
1961                                         err 'operand sizes do not match'\r
1962                                 end if\r
1963                                 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_AS_VEX+EVEX_VL,70h,@src,@dest.mask,@dest.rm,,1,@aux.imm\r
1964                         else\r
1965                                 err 'invalid combination of operands'\r
1966                         end if\r
1967                 end macro\r
1968 \r
1969         end iterate\r
1970 \r
1971         iterate <instr,opcode>, vpsllvd,47h, vpsrlvd,45h, vpsravd,46h\r
1972 \r
1973                 macro instr? dest*,src*,src2*\r
1974                         AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
1975                 end macro\r
1976 \r
1977         end iterate\r
1978 \r
1979         iterate <instr,evex_f,opcode>, vpsllvq,EVEX_AS_VEX+EVEX_VL,47h, vpsrlvq,EVEX_AS_VEX+EVEX_VL,45h, vpsravq,EVEX_REQUIRED+EVEX_VL,46h\r
1980 \r
1981                 macro instr? dest*,src*,src2*\r
1982                         AVX_512.basic_instruction_bcst VEX_66_0F38_W1,evex_f,opcode,8,dest,src,src2\r
1983                 end macro\r
1984 \r
1985         end iterate\r
1986 \r
1987         iterate <instr,unit,vex_mpw,opcode>, vpermi2d,4,VEX_66_0F38_W0,76h, vpermi2q,8,VEX_66_0F38_W1,76h, \\r
1988                                              vpermt2d,4,VEX_66_0F38_W0,7Eh, vpermt2q,8,VEX_66_0F38_W1,7Eh, \\r
1989                                              vprorvd,4,VEX_66_0F38_W0,14h, vprorvq,8,VEX_66_0F38_W1,14h, \\r
1990                                              vprolvd,4,VEX_66_0F38_W0,15h, vprolvq,8,VEX_66_0F38_W1,15h\r
1991 \r
1992                 macro instr? dest*,src*,src2*\r
1993                         AVX_512.basic_instruction_bcst vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src,src2\r
1994                 end macro\r
1995 \r
1996         end iterate\r
1997 \r
1998         iterate <instr,unit,vex_mpw,postbyte>, vprord,4,VEX_66_0F_W0,0, vprorq,8,VEX_66_0F_W1,0, vprold,4,VEX_66_0F_W0,1, vprolq,8,VEX_66_0F_W1,1\r
1999 \r
2000                 macro instr? dest*,src*,aux*\r
2001                         AVX_512.parse_operand_k1z @dest,dest\r
2002                         AVX_512.parse_operand_bcst @src,src,unit\r
2003                         x86.parse_operand @aux,aux\r
2004                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
2005                                 if @src.size and not @dest.size | @aux.size and not 1\r
2006                                         err 'operand sizes do not match'\r
2007                                 end if\r
2008                                 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,72h,@src,@dest.mask,postbyte,@dest.rm,1,@aux.imm\r
2009                         else\r
2010                                 err 'invalid combination of operands'\r
2011                         end if\r
2012                 end macro\r
2013 \r
2014         end iterate\r
2015 \r
2016         iterate <instr,opcode_rrm,opcode,postbyte>, vpslld,0F2h,72h,6, vpsrad,0E2h,72h,4, vpsrld,0D2h,72h,2\r
2017 \r
2018                 macro instr? dest*,src*,src2*\r
2019                         AVX_512.parse_operand_k1z @dest,dest\r
2020                         AVX_512.parse_operand @src2,src2\r
2021                         if @src2.type = 'imm'\r
2022                                 AVX_512.parse_operand_bcst @src,src,4\r
2023                         else\r
2024                                 AVX_512.parse_operand @src,src\r
2025                         end if\r
2026                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2027                                 @src2.memsize = 16\r
2028                                 if @src2.size and not @src2.memsize\r
2029                                         err 'invalid operand size'\r
2030                                 else if @src.size <> @dest.size\r
2031                                         err 'operand sizes do not match'\r
2032                                 end if\r
2033                                 AVX_512.store_instruction @dest.size,VEX_66_0F_W0,EVEX_AS_VEX,opcode_rrm,@src2,@dest.mask,@dest.rm,@src.rm\r
2034                         else if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem') & @src2.type = 'imm'\r
2035                                 if @src2.size and not 1\r
2036                                         err 'invalid operand size'\r
2037                                 else if @src.size <> @dest.size\r
2038                                         err 'operand sizes do not match'\r
2039                                 end if\r
2040                                 if @src.type = 'mem'\r
2041                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,postbyte,@dest.rm,1,@src2.imm\r
2042                                 else\r
2043                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,@src,@dest.mask,postbyte,@dest.rm,1,@src2.imm\r
2044                                 end if\r
2045                         else\r
2046                                 err 'invalid combination of operands'\r
2047                         end if\r
2048                 end macro\r
2049 \r
2050         end iterate\r
2051 \r
2052         iterate <instr,opcode_rrm,opcode,postbyte>, vpsllq,0F3h,73h,6, vpsraq,0E2h,72h,4, vpsrlq,0D3h,73h,2\r
2053 \r
2054                 macro instr? dest*,src*,src2*\r
2055                         AVX_512.parse_operand_k1z @dest,dest\r
2056                         AVX_512.parse_operand @src2,src2\r
2057                         if @src2.type = 'imm'\r
2058                                 AVX_512.parse_operand_bcst @src,src,8\r
2059                         else\r
2060                                 AVX_512.parse_operand @src,src\r
2061                         end if\r
2062                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2063                                 @src2.memsize = 16\r
2064                                 if @src2.size and not @src2.memsize\r
2065                                         err 'invalid operand size'\r
2066                                 else if @src.size <> @dest.size\r
2067                                         err 'operand sizes do not match'\r
2068                                 end if\r
2069                                 if `instr = 'vpsraq'\r
2070                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode_rrm,@src2,@dest.mask,@dest.rm,@src.rm\r
2071                                 else\r
2072                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode_rrm,@src2,@dest.mask,@dest.rm,@src.rm\r
2073                                 end if\r
2074                         else if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem') & @src2.type = 'imm'\r
2075                                 if @src2.size and not 1\r
2076                                         err 'invalid operand size'\r
2077                                 else if @src.size and not @dest.size\r
2078                                         err 'operand sizes do not match'\r
2079                                 end if\r
2080                                 if @src.type = 'mem' | `instr = 'vpsraq'\r
2081                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,postbyte,@dest.rm,1,@src2.imm\r
2082                                 else\r
2083                                         AVX_512.store_instruction @dest.size,VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,@src,@dest.mask,postbyte,@dest.rm,1,@src2.imm\r
2084                                 end if\r
2085                         else\r
2086                                 err 'invalid combination of operands'\r
2087                         end if\r
2088                 end macro\r
2089 \r
2090         end iterate\r
2091 \r
2092         iterate <instr,opcode>, vpcmpeqd,76h, vpcmpgtd,66h\r
2093 \r
2094                 macro instr? dest*,src*,src2*\r
2095                         AVX_512.parse_operand_k1 @dest,dest\r
2096                         AVX_512.parse_operand @src,src\r
2097                         AVX_512.parse_operand_bcst @src2,src2,4\r
2098                         if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2099                                 if @src2.size and not @src.size\r
2100                                         err 'operand sizes do not match'\r
2101                                 end if\r
2102                                 AVX_512.store_instruction @src.size,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2103                         else if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2104                                 if @src.size <> @dest.size | @src2.size and not @dest.size\r
2105                                         err 'operand sizes do not match'\r
2106                                 end if\r
2107                                 AVX_512.store_instruction @src.size,VEX_66_0F_W0,EVEX_FORBIDDEN,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2108                         else\r
2109                                 err 'invalid combination of operands'\r
2110                         end if\r
2111                 end macro\r
2112 \r
2113         end iterate\r
2114 \r
2115         iterate <instr,opcode>, vpcmpeqq,29h, vpcmpgtq,37h\r
2116 \r
2117                 macro instr? dest*,src*,src2*\r
2118                         AVX_512.parse_operand_k1 @dest,dest\r
2119                         AVX_512.parse_operand @src,src\r
2120                         AVX_512.parse_operand_bcst @src2,src2,8\r
2121                         if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2122                                 if @src2.size and not @src.size\r
2123                                         err 'operand sizes do not match'\r
2124                                 end if\r
2125                                 AVX_512.store_instruction @src.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2126                         else if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2127                                 if @src.size <> @dest.size | @src2.size and not @dest.size\r
2128                                         err 'operand sizes do not match'\r
2129                                 end if\r
2130                                 AVX_512.store_instruction @src.size,VEX_66_0F38_W0,EVEX_FORBIDDEN,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2131                         else\r
2132                                 err 'invalid combination of operands'\r
2133                         end if\r
2134                 end macro\r
2135 \r
2136         end iterate\r
2137 \r
2138         iterate <instr,unit,vex_mpw,opcode>, vptestnmd,4,VEX_F3_0F38_W0,27h, vptestnmq,8,VEX_F3_0F38_W1,27h, vptestmd,4,VEX_66_0F38_W0,27h, vptestmq,8,VEX_66_0F38_W1,27h\r
2139 \r
2140                 macro instr? dest*,src*,src2*\r
2141                         AVX_512.parse_operand_k1 @dest,dest\r
2142                         AVX_512.parse_operand @src,src\r
2143                         AVX_512.parse_operand_bcst @src2,src2,unit\r
2144                         if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2145                                 if @src2.size and not @src.size\r
2146                                         err 'operand sizes do not match'\r
2147                                 end if\r
2148                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2149                         else\r
2150                                 err 'invalid combination of operands'\r
2151                         end if\r
2152                 end macro\r
2153 \r
2154         end iterate\r
2155 \r
2156         iterate <instr,unit,vex_mpw,opcode>, vpcmpd,4,VEX_66_0F3A_W0,1Fh, vpcmpud,4,VEX_66_0F3A_W0,1Eh, vpcmpq,8,VEX_66_0F3A_W1,1Fh, vpcmpuq,8,VEX_66_0F3A_W1,1Eh\r
2157 \r
2158                 macro instr? dest*,src*,src2*,aux*\r
2159                         AVX_512.parse_operand_k1 @dest,dest\r
2160                         AVX_512.parse_operand @src,src\r
2161                         AVX_512.parse_operand_bcst @src2,src2,unit\r
2162                         x86.parse_operand @aux,aux\r
2163                         if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'\r
2164                                 if @src2.size and not @src.size | @aux.size and not 1\r
2165                                         err 'operand sizes do not match'\r
2166                                 end if\r
2167                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
2168                         else\r
2169                                 err 'invalid combination of operands'\r
2170                         end if\r
2171                 end macro\r
2172 \r
2173         end iterate\r
2174 \r
2175         iterate <instr,opcode,msize>, vpmovsxbd,21h,4, vpmovsxbq,22h,2, vpmovsxwd,23h,8, vpmovsxwq,24h,4, vpmovsxdq,25h,8, \\r
2176                                       vpmovzxbd,31h,4, vpmovzxbq,32h,2, vpmovzxwd,33h,8, vpmovzxwq,34h,4, vpmovzxdq,35h,8\r
2177 \r
2178                 macro instr? dest*,src*\r
2179                         AVX_512.parse_operand_k1z @dest,dest\r
2180                         AVX_512.parse_operand @src,src\r
2181                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
2182                                 @src.memsize = msize * (@dest.size shr 4)\r
2183                                 if (@src.type = 'mmreg' & @src.size <> (@src.memsize-1) and not 15 + 16) | (@src.type = 'mem' & @src.size and not @src.memsize)\r
2184                                         err 'invalid operand size'\r
2185                                 end if\r
2186                                 AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
2187                         else\r
2188                                 err 'invalid combination of operands'\r
2189                         end if\r
2190                 end macro\r
2191 \r
2192         end iterate\r
2193 \r
2194         iterate <instr,opcode>, vpermq,0, vpermpd,1\r
2195 \r
2196                 macro instr? dest*,src*,aux*\r
2197                         AVX_512.parse_operand_k1z @dest,dest\r
2198                         AVX_512.parse_operand_bcst @src,src,8\r
2199                         x86.parse_operand @aux,aux\r
2200                         if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
2201                                 if @dest.size < 32 | @aux.size and not 1\r
2202                                         err 'invalid operand size'\r
2203                                 else if @src.size and not @dest.size\r
2204                                         err 'operand sizes do not match'\r
2205                                 end if\r
2206                                 AVX_512.store_instruction @dest.size,VEX_66_0F3A_W1,EVEX_AS_VEX+EVEX_VL,opcode,@src,@dest.mask,@dest.rm,,1,@aux.imm\r
2207                         else\r
2208                                 err 'invalid combination of operands'\r
2209                         end if\r
2210                 end macro\r
2211 \r
2212         end iterate\r
2213 \r
2214         iterate <instr,opcode>, vpermd,36h, vpermps,16h\r
2215 \r
2216                 macro instr? dest*,src*,src2*\r
2217                         AVX_512.parse_operand_k1z @dest,dest\r
2218                         AVX_512.parse_operand @src,src\r
2219                         AVX_512.parse_operand_bcst @src2,src2,4\r
2220                         if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')\r
2221                                 if @dest.size < 32\r
2222                                         err 'invalid operand size'\r
2223                                 else if @src.size <> @dest.size | @src2.size and not @dest.size\r
2224                                         err 'operand sizes do not match'\r
2225                                 end if\r
2226                                 AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm\r
2227                         else\r
2228                                 err 'invalid combination of operands'\r
2229                         end if\r
2230                 end macro\r
2231 \r
2232         end iterate\r
2233 \r
2234         iterate <instr,lcode>, vfmaddsub,6, vfmsubadd,7, vfmaddsub,8, vfmsub,0Ah, vfnmadd,0Ch, vfnmsub,0Eh\r
2235 \r
2236                 iterate <order,hcode>, 132,90h, 213,0A0h, 231,0B0h\r
2237 \r
2238                         macro instr#order#pd? dest*,src*,src2*&\r
2239                                 AVX_512.basic_instruction_bcst_er VEX_66_0F38_W1,EVEX_AS_VEX+EVEX_VL,hcode+lcode,8,dest,src,src2\r
2240                         end macro\r
2241 \r
2242                         macro instr#order#ps? dest*,src*,src2*&\r
2243                                 AVX_512.basic_instruction_bcst_er VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,hcode+lcode,4,dest,src,src2\r
2244                         end macro\r
2245 \r
2246                         if lcode > 7\r
2247 \r
2248                                 macro instr#order#sd? dest*,src*,src2*&\r
2249                                         AVX_512.basic_instruction_er VEX_66_0F38_W1,EVEX_AS_VEX,hcode+lcode+1,8,dest,src,src2\r
2250                                 end macro\r
2251 \r
2252                                 macro instr#order#ss? dest*,src*,src2*&\r
2253                                         AVX_512.basic_instruction_er VEX_66_0F38_W0,EVEX_AS_VEX,hcode+lcode+1,4,dest,src,src2\r
2254                                 end macro\r
2255 \r
2256                         end if\r
2257 \r
2258                 end iterate\r
2259 \r
2260         end iterate\r
2261 \r
2262         iterate <instr,unit,vex_mpw,opcode>, valignd,4,VEX_66_0F3A_W0,3, vpternlogd,4,VEX_66_0F3A_W0,25h, vpternlogq,8,VEX_66_0F3A_W1,25h\r
2263 \r
2264                 macro instr? dest*,src*,src2*,aux*&\r
2265                         AVX_512.basic_instruction_bcst_imm8 vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src,src2,aux\r
2266                 end macro\r
2267 \r
2268         end iterate\r
2269 \r
2270         iterate <instr,opcode>, valignq,3\r
2271 \r
2272                 macro instr? dest*,src*,src2*,aux*&\r
2273                         AVX_512.basic_instruction_bcst_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2,aux\r
2274                 end macro\r
2275 \r
2276         end iterate\r
2277 \r
2278         iterate <instr,opcode>, vblendmps,65h, vpblendmd,64h\r
2279 \r
2280                 macro instr? dest*,src*,src2*&\r
2281                         AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2\r
2282                 end macro\r
2283 \r
2284         end iterate\r
2285 \r
2286         iterate <instr,opcode>, vblendmpd,65h, vpblendmq,64h\r
2287 \r
2288                 macro instr? dest*,src*,src2*&\r
2289                         AVX_512.basic_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2\r
2290                 end macro\r
2291 \r
2292         end iterate\r
2293 \r
2294         iterate <instr,unit,vex_mpw,opcode>, vrcp14ps,4,VEX_66_0F38_W0,4Ch, vrcp14pd,8,VEX_66_0F38_W1,4Ch, vrsqrt14ps,4,VEX_66_0F38_W0,4Eh, vrsqrt14pd,8,VEX_66_0F38_W1,4Eh\r
2295 \r
2296                 macro instr? dest*,src*&\r
2297                         AVX_512.single_source_instruction_bcst vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src\r
2298                 end macro\r
2299 \r
2300         end iterate\r
2301 \r
2302         iterate <instr,unit,vex_mpw,opcode>, vrcp14ss,4,VEX_66_0F38_W0,4Dh, vrcp14sd,8,VEX_66_0F38_W1,4Dh, vrsqrt14ss,4,VEX_66_0F38_W0,4Fh, vrsqrt14sd,8,VEX_66_0F38_W1,4Fh\r
2303 \r
2304                 macro instr? dest*,src*&\r
2305                         AVX_512.basic_instruction vex_mpw,EVEX_REQUIRED,opcode,unit,dest,src\r
2306                 end macro\r
2307 \r
2308         end iterate\r
2309 \r
2310         iterate <instr,vex_mpw,opcode>, vcompressps,VEX_66_0F_W0,8Ah, vcompresspd,VEX_66_0F_W1,8Ah, vpcompressd,VEX_66_0F38_W0,8Bh, vpcompressq,VEX_66_0F38_W1,8Bh\r
2311 \r
2312                 macro instr? dest*,src*\r
2313                         AVX_512.parse_operand_k1z @dest,dest\r
2314                         AVX_512.parse_operand @src,src\r
2315                         if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg'\r
2316                                 if @dest.size and not @src.size\r
2317                                         err 'operand sizes do not match'\r
2318                                 end if\r
2319                                 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm\r
2320                         else\r
2321                                 err 'invalid combination of operands'\r
2322                         end if\r
2323                 end macro\r
2324 \r
2325         end iterate\r
2326 \r
2327         iterate <instr,vex_mpw,opcode>, vexpandps,VEX_66_0F38_W0,88h, vexpandpd,VEX_66_0F38_W1,88h, vpexpandd,VEX_66_0F38_W0,89h, vpexpandq,VEX_66_0F38_W1,89h\r
2328 \r
2329                 macro instr? dest*,src*\r
2330                         AVX_512.single_source_instruction vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,0,dest,src\r
2331                 end macro\r
2332 \r
2333         end iterate\r
2334 \r
2335         iterate <instr,opcode>, fixupimm,54h\r
2336 \r
2337                 macro v#instr#pd? dest*,src*,src2*,aux*&\r
2338                         AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2,aux\r
2339                 end macro\r
2340 \r
2341                 macro v#instr#ps? dest*,src*,src2*,aux*&\r
2342                         AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2,aux\r
2343                 end macro\r
2344 \r
2345                 macro v#instr#sd? dest*,src*,src2*,aux*&\r
2346                         AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,opcode+1,8,dest,src,src2,aux\r
2347                 end macro\r
2348 \r
2349                 macro v#instr#ss? dest*,src*,src2*,aux*&\r
2350                         AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,opcode+1,4,dest,src,src2,aux\r
2351                 end macro\r
2352 \r
2353         end iterate\r
2354 \r
2355         iterate <instr,opcode>, getexp,42h\r
2356 \r
2357                 macro v#instr#pd? dest*,src*&\r
2358                         AVX_512.single_source_instruction_bcst_sae VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src\r
2359                 end macro\r
2360 \r
2361                 macro v#instr#ps? dest*,src*&\r
2362                         AVX_512.single_source_instruction_bcst_sae VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src\r
2363                 end macro\r
2364 \r
2365                 macro v#instr#sd? dest*,src*,src2*&\r
2366                         AVX_512.basic_instruction_sae VEX_66_0F38_W1,EVEX_REQUIRED,opcode+1,8,dest,src,src2\r
2367                 end macro\r
2368 \r
2369                 macro v#instr#ss? dest*,src*,src2*&\r
2370                         AVX_512.basic_instruction_sae VEX_66_0F38_W0,EVEX_REQUIRED,opcode+1,4,dest,src,src2\r
2371                 end macro\r
2372 \r
2373         end iterate\r
2374 \r
2375         iterate <instr,opcode_ps,opcode_pd,opcode_ss,opcode_sd>, getmant,26h,26h,27h,27h, rndscale,8,9,0Ah,0Bh\r
2376 \r
2377                 macro v#instr#pd? dest*,src*,aux*&\r
2378                         AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode_pd,8,dest,src,aux\r
2379                 end macro\r
2380 \r
2381                 macro v#instr#ps? dest*,src*,aux*&\r
2382                         AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,opcode_ps,4,dest,src,aux\r
2383                 end macro\r
2384 \r
2385                 macro v#instr#sd? dest*,src*,src2*,aux*&\r
2386                         AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,opcode_sd,8,dest,src,src2,aux\r
2387                 end macro\r
2388 \r
2389                 macro v#instr#ss? dest*,src*,src2*,aux*&\r
2390                         AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,opcode_ss,4,dest,src,src2,aux\r
2391                 end macro\r
2392 \r
2393         end iterate\r
2394 \r
2395         iterate <instr,unit,vex_mpw>, vscalefpd,8,VEX_66_0F38_W1, vscalefps,4,VEX_66_0F38_W0\r
2396 \r
2397                 macro instr? dest*,src*,src2*&\r
2398                         AVX_512.basic_instruction_bcst_er vex_mpw,EVEX_REQUIRED+EVEX_VL,2Ch,unit,dest,src,src2\r
2399                 end macro\r
2400 \r
2401         end iterate\r
2402 \r
2403         iterate <instr,unit,vex_mpw>, vscalefsd,8,VEX_66_0F38_W1, vscalefss,4,VEX_66_0F38_W0\r
2404 \r
2405                 macro instr? dest*,src*,src2*&\r
2406                         AVX_512.basic_instruction_er vex_mpw,EVEX_REQUIRED,2Dh,unit,dest,src,src2\r
2407                 end macro\r
2408 \r
2409         end iterate\r
2410 \r
2411         iterate <instr,ratio,opcode>, vpmovusdb,4,11h, vpmovsdb,4,21h, vpmovdb,4,31h, \\r
2412                                       vpmovusqb,8,12h, vpmovsqb,8,22h, vpmovqb,8,32h, \\r
2413                                       vpmovusdw,2,13h, vpmovsdw,2,23h, vpmovdw,2,33h, \\r
2414                                       vpmovusqw,4,14h, vpmovsqw,4,24h, vpmovqw,4,34h, \\r
2415                                       vpmovusqd,2,15h, vpmovsqd,2,25h, vpmovqd,2,35h\r
2416 \r
2417                 macro instr? dest*,src*\r
2418                         AVX_512.parse_operand_k1z @dest,dest\r
2419                         AVX_512.parse_operand @src,src\r
2420                         if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg'\r
2421                                 @dest.memsize = @src.size / ratio\r
2422                                 if (@dest.type = 'mmreg' & @dest.size <> (@dest.memsize-1) and not 15 + 16) | (@dest.type = 'mem' & @dest.size and not @dest.memsize)\r
2423                                         err 'invalid operand size'\r
2424                                 end if\r
2425                                 AVX_512.store_instruction @src.size,VEX_F3_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm\r
2426                         else\r
2427                                 err 'invalid combination of operands'\r
2428                         end if\r
2429                 end macro\r
2430 \r
2431         end iterate\r
2432 \r
2433         calminstruction AVX_512.parse_vsib_operand namespace, operand\r
2434 \r
2435                 local   size, type, segment_prefix\r
2436                 local   displacement, displacement_size, auto_relative\r
2437                 local   address, base_registers, index_registers\r
2438                 local   mode, mod, rm\r
2439                 local   scale, index, base\r
2440                 local   visize\r
2441 \r
2442                 local   i, pre, suf, sym\r
2443 \r
2444                 compute segment_prefix, 0\r
2445 \r
2446                 compute size, 0\r
2447                 compute displacement_size, 0\r
2448 \r
2449                 transform operand\r
2450 \r
2451                 match   pre suf, operand\r
2452                 jno     no_size_prefix\r
2453                 transform pre, x86\r
2454                 jno     no_size_prefix\r
2455                 match   :size, pre\r
2456                 jno     no_size_prefix\r
2457                 arrange operand, suf\r
2458               no_size_prefix:\r
2459 \r
2460                 match   [address], operand\r
2461                 jyes    memory_operand\r
2462                 match   =ptr? address, operand\r
2463                 jyes    memory_operand\r
2464 \r
2465                 jump    invalid_operand\r
2466 \r
2467           memory_operand:\r
2468                 compute type, 'mem'\r
2469 \r
2470                 match   segment:address, address\r
2471                 jno     segment_prefix_ok\r
2472                 check   segment eq 1 elementof segment & 1 metadataof segment relativeto x86.sreg\r
2473                 jno     invalid_operand\r
2474                 compute segment, 1 metadataof segment - x86.sreg\r
2475                 check   segment >= 4\r
2476                 jyes    segment_prefix_386\r
2477                 compute segment_prefix, 26h + segment shl 3\r
2478                 jump    segment_prefix_ok\r
2479               segment_prefix_386:\r
2480                 compute segment_prefix, 64h + segment-4\r
2481               segment_prefix_ok:\r
2482 \r
2483                 match   pre suf, address\r
2484                 jno     no_address_size_prefix\r
2485                 transform pre, x86\r
2486                 jno     no_address_size_prefix\r
2487                 match   :pre, pre\r
2488                 jno     no_address_size_prefix\r
2489                 arrange address, suf\r
2490                 check   pre = 4 | pre = 8\r
2491                 jno     invalid_address_size\r
2492                 compute mode, pre shl 3\r
2493               no_address_size_prefix:\r
2494 \r
2495                 compute mode, 0\r
2496                 compute scale, 0\r
2497                 compute index, 0\r
2498                 compute base, 0\r
2499                 compute auto_relative, 0\r
2500 \r
2501                 check   size\r
2502                 jyes    size_override\r
2503                 compute size, sizeof address\r
2504               size_override:\r
2505 \r
2506                 compute address, address\r
2507                 compute base_registers, 0\r
2508                 compute index_registers, 0\r
2509                 compute i, 1\r
2510               extract_registers:\r
2511                 check   i > elementsof address\r
2512                 jyes    registers_extracted\r
2513                 check   i metadataof address relativeto SSE.reg | i metadataof address relativeto AVX.reg | 1 metadataof (i metadataof address) relativeto AVX_512.reg\r
2514                 jyes    index_term\r
2515                 check   i metadataof address relativeto x86.r32 | i metadataof address relativeto x86.r64\r
2516                 jno     next_term\r
2517                 compute base_registers, base_registers + i elementof address * i scaleof address\r
2518                 jump    next_term\r
2519               index_term:\r
2520                 compute index_registers, index_registers + i elementof address * i scaleof address\r
2521               next_term:\r
2522                 compute i, i+1\r
2523                 jump    extract_registers\r
2524               registers_extracted:\r
2525                 compute displacement, address - base_registers - index_registers\r
2526                 compute auto_relative, 0\r
2527 \r
2528                 check   elementsof index_registers = 1\r
2529                 jno     invalid_address\r
2530                 compute scale, 1 scaleof index_registers\r
2531                 compute index, 0 scaleof (1 metadataof index_registers)\r
2532                 check   scale > 2 & scale <> 4 & scale <> 8\r
2533                 jyes    invalid_address\r
2534                 check   1 metadataof index_registers relativeto SSE.reg\r
2535                 jyes    xmm_index\r
2536                 check   1 metadataof index_registers relativeto AVX.reg\r
2537                 jyes    ymm_index\r
2538                 compute visize, 1 metadataof (1 metadataof index_registers) - AVX_512.reg\r
2539                 jump    index_ok\r
2540               ymm_index:\r
2541                 compute visize, 32\r
2542                 jump    index_ok\r
2543               xmm_index:\r
2544                 compute visize, 16\r
2545               index_ok:\r
2546 \r
2547                 compute rm, 4\r
2548                 check   elementsof base_registers = 1 & 1 scaleof base_registers = 1\r
2549                 jyes    base_and_index\r
2550                 check   elementsof base_registers = 0\r
2551                 jno     invalid_address\r
2552                 compute base, 5\r
2553                 compute displacement_size, 4\r
2554                 compute mod, 0\r
2555                 compute mode, x86.mode\r
2556                 check   mode > 16\r
2557                 jyes    export_address\r
2558                 compute mode, 32\r
2559                 jump    export_address\r
2560               base_and_index:\r
2561                 compute base, 0 scaleof (1 metadataof base_registers)\r
2562                 check   mode & mode <> 0 scaleof (1 metadataof (1 metadataof base_registers)) shl 3\r
2563                 jyes    invalid_address\r
2564                 compute mode, 0 scaleof (1 metadataof (1 metadataof base_registers)) shl 3\r
2565 \r
2566               setup_displacement:\r
2567                 check   displacement relativeto 0\r
2568                 jno     displacement_32bit\r
2569                 check   displacement = 0 & rm and 111b <> 5 & (rm <> 4 | base and 111b <> 5)\r
2570                 jyes    displacement_empty\r
2571                 check   displacement < 80h & displacement >= -80h\r
2572                 jyes    displacement_8bit\r
2573                 check   displacement - 1 shl mode >= -80h & displacement < 1 shl mode\r
2574                 jyes    displacement_8bit_wrap\r
2575               displacement_32bit:\r
2576                 compute displacement_size, 4\r
2577                 compute mod, 2\r
2578                 jump    export_address\r
2579               displacement_8bit_wrap:\r
2580                 compute displacement, displacement - 1 shl mode\r
2581               displacement_8bit:\r
2582                 compute displacement_size, 1\r
2583                 compute mod, 1\r
2584                 jump    export_address\r
2585               index_only:\r
2586                 compute displacement_size, 4\r
2587                 compute mod, 0\r
2588                 jump    export_address\r
2589               displacement_empty:\r
2590                 compute displacement_size, 0\r
2591                 compute mod, 0\r
2592 \r
2593           export_address:\r
2594 \r
2595                 arrange sym, namespace.=address\r
2596                 publish sym, address\r
2597 \r
2598                 arrange sym, namespace.=scale\r
2599                 publish sym, scale\r
2600 \r
2601                 arrange sym, namespace.=index\r
2602                 publish sym, index\r
2603 \r
2604                 arrange sym, namespace.=base\r
2605                 publish sym, base\r
2606 \r
2607                 arrange sym, namespace.=auto_relative\r
2608                 publish sym, auto_relative\r
2609 \r
2610                 arrange sym, namespace.=displacement\r
2611                 publish sym, displacement\r
2612 \r
2613                 arrange sym, namespace.=mode\r
2614                 publish sym, mode\r
2615 \r
2616                 arrange sym, namespace.=mod\r
2617                 publish sym, mod\r
2618 \r
2619                 arrange sym, namespace.=rm\r
2620                 publish sym, rm\r
2621 \r
2622                 arrange sym, namespace.=type\r
2623                 publish sym, type\r
2624 \r
2625                 arrange sym, namespace.=size\r
2626                 publish sym, size\r
2627 \r
2628                 arrange sym, namespace.=visize\r
2629                 publish sym, visize\r
2630 \r
2631                 arrange sym, namespace.=displacement_size\r
2632                 publish sym, displacement_size\r
2633 \r
2634                 arrange sym, namespace.=segment_prefix\r
2635                 publish sym, segment_prefix\r
2636 \r
2637                 compute i, 0\r
2638 \r
2639                 arrange sym, namespace.=mask\r
2640                 publish sym, i\r
2641 \r
2642                 arrange sym, namespace.=evex_b\r
2643                 publish sym, i\r
2644 \r
2645                 arrange sym, namespace.=memsize\r
2646                 publish sym, i\r
2647 \r
2648                 exit\r
2649 \r
2650           invalid_operand:\r
2651                 asmcmd  =err 'invalid operand'\r
2652                 exit\r
2653           invalid_address:\r
2654                 asmcmd  =err 'invalid address'\r
2655                 exit\r
2656           invalid_address_size:\r
2657                 asmcmd  =err 'invalid address size'\r
2658                 exit\r
2659 \r
2660         end calminstruction\r
2661 \r
2662         calminstruction AVX_512.parse_vsib_operand_k1 namespace,operand\r
2663 \r
2664                 local   k1, mask, sym\r
2665                 transform operand\r
2666                 match   operand {k1}, operand\r
2667                 jyes    k1\r
2668                 asmcmd  =AVX_512.=parse_vsib_operand namespace, operand\r
2669                 exit\r
2670             k1:\r
2671                 asmcmd  =AVX_512.=parse_vsib_operand namespace, operand\r
2672                 arrange sym, namespace.=type\r
2673                 check   k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0\r
2674                 jno     invalid_mask\r
2675                 compute mask, 1 metadataof k1 - AVX_512.maskreg\r
2676                 arrange sym, namespace.=mask\r
2677                 publish sym, mask\r
2678                 exit\r
2679             invalid_mask:\r
2680                 asmcmd  =err 'invalid mask'\r
2681 \r
2682         end calminstruction\r
2683 \r
2684         iterate <instr,opcode,asize>, vpgatherdd,90h,4, vpgatherqd,91h,8, vgatherdps,92h,4, vgatherqps,93h,8\r
2685 \r
2686                 macro instr? dest*,src*,aux\r
2687                         match , aux\r
2688                                 AVX_512.parse_operand_k1 @dest,dest\r
2689                                 AVX_512.parse_vsib_operand @src,src\r
2690                                 if @dest.type = 'mmreg' & @dest.mask & @src.type = 'mem'\r
2691                                         if @src.size and not 4 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize)\r
2692                                                 err 'invalid operand size'\r
2693                                         else if @dest.rm = @src.index\r
2694                                                 err 'disallowed combination of registers'\r
2695                                         end if\r
2696                                         @src.memsize = 4\r
2697                                         AVX_512.store_instruction @src.visize,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm,@src.index and 10000b\r
2698                                 else\r
2699                                         err 'invalid combination of operands'\r
2700                                 end if\r
2701                         else\r
2702                                 AVX.parse_operand @dest,dest\r
2703                                 AVX.parse_vsib_operand @src,src\r
2704                                 AVX.parse_operand @aux,aux\r
2705                                 if @dest.type = 'mmreg' & @src.type = 'mem' & @aux.type = 'mmreg'\r
2706                                         if @src.size and not 4 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize)\r
2707                                                 err 'invalid operand size'\r
2708                                         else if @aux.size <> @dest.size\r
2709                                                 err 'operand sizes do not match'\r
2710                                         else if @dest.rm = @aux.rm | @dest.rm = @src.index | @aux.rm = @src.index\r
2711                                                 err 'disallowed combination of registers'\r
2712                                         end if\r
2713                                         AVX.store_instruction @src.visize,VEX_66_0F38_W0,opcode,@src,@dest.rm,@aux.rm\r
2714                                 else\r
2715                                         err 'invalid combination of operands'\r
2716                                 end if\r
2717                         end match\r
2718                 end macro\r
2719 \r
2720         end iterate\r
2721 \r
2722         iterate <instr,opcode,asize>, vpgatherdq,90h,4, vpgatherqq,91h,8, vgatherdpd,92h,4, vgatherqpd,93h,8\r
2723 \r
2724                 macro instr? dest*,src*,aux\r
2725                         match , aux\r
2726                                 AVX_512.parse_operand_k1 @dest,dest\r
2727                                 AVX_512.parse_vsib_operand @src,src\r
2728                                 if @dest.type = 'mmreg' & @dest.mask & @src.type = 'mem'\r
2729                                         if @src.size and not 8 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize * 2) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize * 2)\r
2730                                                 err 'invalid operand size'\r
2731                                         else if @dest.rm = @src.index\r
2732                                                 err 'disallowed combination of registers'\r
2733                                         end if\r
2734                                         @src.memsize = 8\r
2735                                         AVX_512.store_instruction @dest.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm,@src.index and 10000b\r
2736                                 else\r
2737                                         err 'invalid combination of operands'\r
2738                                 end if\r
2739                         else\r
2740                                 AVX.parse_operand @dest,dest\r
2741                                 AVX.parse_vsib_operand @src,src\r
2742                                 AVX.parse_operand @aux,aux\r
2743                                 if @dest.type = 'mmreg' & @src.type = 'mem' & @aux.type = 'mmreg'\r
2744                                         if @src.size and not 8 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize * 2) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize * 2)\r
2745                                                 err 'invalid operand size'\r
2746                                         else if @aux.size <> @dest.size\r
2747                                                 err 'operand sizes do not match'\r
2748                                         else if @dest.rm = @aux.rm | @dest.rm = @src.index | @aux.rm = @src.index\r
2749                                                 err 'disallowed combination of registers'\r
2750                                         end if\r
2751                                         AVX.store_instruction @dest.size,VEX_66_0F38_W1,opcode,@src,@dest.rm,@aux.rm\r
2752                                 else\r
2753                                         err 'invalid combination of operands'\r
2754                                 end if\r
2755                         end match\r
2756                 end macro\r
2757 \r
2758         end iterate\r
2759 \r
2760         iterate <instr,opcode,asize>, vpscatterdd,0A0h,4, vpscatterqd,0A1h,8, vscatterdps,0A2h,4, vscatterqps,0A3h,8\r
2761 \r
2762                 macro instr? dest*,src*\r
2763                         AVX_512.parse_vsib_operand_k1 @dest,dest\r
2764                         AVX_512.parse_operand @src,src\r
2765                         if @dest.type = 'mem' & @dest.mask & @src.type = 'mmreg'\r
2766                                 if @dest.size and not 4 | (@src.size > 16 & @src.size * (asize shr 2) > @dest.visize) | (@dest.visize > 16 & @src.size * (asize shr 2) < @dest.visize)\r
2767                                         err 'invalid operand size'\r
2768                                 else if @src.rm = @dest.index\r
2769                                         err 'disallowed combination of registers'\r
2770                                 end if\r
2771                                 @dest.memsize = 4\r
2772                                 AVX_512.store_instruction @dest.visize,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm,@dest.index and 10000b\r
2773                         else\r
2774                                 err 'invalid combination of operands'\r
2775                         end if\r
2776                 end macro\r
2777 \r
2778         end iterate\r
2779 \r
2780         iterate <instr,opcode,asize>, vpscatterdq,0A0h,4, vpscatterqq,0A1h,8, vscatterdpd,0A2h,4, vscatterqpd,0A3h,8\r
2781 \r
2782                 macro instr? dest*,src*\r
2783                         AVX_512.parse_vsib_operand_k1 @dest,dest\r
2784                         AVX_512.parse_operand @src,src\r
2785                         if @dest.type = 'mem' & @dest.mask & @src.type = 'mmreg'\r
2786                                 if @dest.size and not 8 | (@src.size > 16 & @src.size * (asize shr 2) > @dest.visize * 2) | (@dest.visize > 16 & @src.size * (asize shr 2) < @dest.visize * 2)\r
2787                                         err 'invalid operand size'\r
2788                                 else if @src.rm = @dest.index\r
2789                                         err 'disallowed combination of registers'\r
2790                                 end if\r
2791                                 @dest.memsize = 8\r
2792                                 AVX_512.store_instruction @src.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm,@dest.index and 10000b\r
2793                         else\r
2794                                 err 'invalid combination of operands'\r
2795                         end if\r
2796                 end macro\r
2797 \r
2798         end iterate\r
2799 \r
2800 end if\r