| blob | 162987deb293d1241406e862367f536397a644df |
1 \r
2 if ~ defined AVX_512\r
3 \r
4 include 'avx512f.inc'\r
5 \r
6 end if\r
7 \r
8 iterate <instr,opcode>, kandb,41h, kandnb,42h, knotb,44h, korb,45h, kxnorb,46h, kxorb,47h, kaddb,4Ah\r
9 \r
10 macro instr? dest*,src*,src2*\r
11 AVX_512.parse_operand @dest,dest\r
12 AVX_512.parse_operand @src,src\r
13 AVX_512.parse_operand @src2,src2\r
14 if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'\r
15 AVX.store_instruction 32,VEX_66_0F_W0,opcode,@src2,@dest.rm,@src.rm\r
16 else\r
17 err 'invalid combination of operands'\r
18 end if\r
19 end macro\r
20 \r
21 end iterate\r
22 \r
23 iterate <instr,opcode>, knotb,44h, kortestb,98h, ktestb,99h\r
24 \r
25 macro instr? dest*,src*\r
26 AVX_512.parse_operand @dest,dest\r
27 AVX_512.parse_operand @src,src\r
28 if @dest.type = 'maskreg' & @src.type = 'maskreg'\r
29 AVX.store_instruction 16,VEX_66_0F_W0,opcode,@src,@dest.rm\r
30 else\r
31 err 'invalid combination of operands'\r
32 end if\r
33 end macro\r
34 \r
35 end iterate\r
36 \r
37 macro kmovb? dest*,src*\r
38 AVX_512.parse_operand @dest,dest\r
39 AVX_512.parse_operand @src,src\r
40 if @dest.type = 'maskreg' & (@src.type = 'maskreg' | @src.type = 'mem')\r
41 if @src.type = 'mem' & @src.size and not 1\r
42 err 'invalid operand size'\r
43 end if\r
44 AVX.store_instruction 16,VEX_66_0F_W0,90h,@src,@dest.rm\r
45 else if @dest.type = 'mem' & @src.type = 'maskreg'\r
46 if @dest.size and not 1\r
47 err 'invalid operand size'\r
48 end if\r
49 AVX.store_instruction 16,VEX_66_0F_W0,91h,@dest,@src.rm\r
50 else if @dest.type = 'maskreg' & @src.type = 'reg'\r
51 if @src.size <> 4\r
52 err 'invalid operand size'\r
53 end if\r
54 AVX.store_instruction 16,VEX_66_0F_W0,92h,@src,@dest.rm\r
55 else if @dest.type = 'reg' & @src.type = 'maskreg'\r
56 if @dest.size <> 4\r
57 err 'invalid operand size'\r
58 end if\r
59 AVX.store_instruction 16,VEX_66_0F_W0,93h,@src,@dest.rm\r
60 else\r
61 err 'invalid combination of operands'\r
62 end if\r
63 end macro\r
64 \r
65 macro kaddw? dest*,src*,src2*\r
66 AVX_512.parse_operand @dest,dest\r
67 AVX_512.parse_operand @src,src\r
68 AVX_512.parse_operand @src2,src2\r
69 if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'\r
70 AVX.store_instruction 32,VEX_0F_W0,opcode,@src2,@dest.rm,@src.rm\r
71 else\r
72 err 'invalid combination of operands'\r
73 end if\r
74 end macro\r
75 \r
76 macro ktestw? dest*,src*\r
77 AVX_512.parse_operand @dest,dest\r
78 AVX_512.parse_operand @src,src\r
79 if @dest.type = 'maskreg' & @src.type = 'maskreg'\r
80 AVX.store_instruction 16,VEX_0F_W0,opcode,@src,@dest.rm\r
81 else\r
82 err 'invalid combination of operands'\r
83 end if\r
84 end macro\r
85 \r
86 iterate <instr,vex_mpw,opcode>, kshiftrb,VEX_66_0F3A_W0,30h, kshiftlb,VEX_66_0F3A_W0,32h\r
87 \r
88 macro instr? dest*,src*,aux*\r
89 AVX_512.parse_operand @dest,dest\r
90 AVX_512.parse_operand @src,src\r
91 x86.parse_operand @aux,aux\r
92 if @dest.type = 'maskreg' & @src.type = 'maskreg' & @aux.type = 'imm'\r
93 if @aux.size and not 1\r
94 err 'invalid operand size'\r
95 end if\r
96 AVX.store_instruction 16,vex_mpw,opcode,@src,@dest.rm,,1,@aux.imm\r
97 else\r
98 err 'invalid combination of operands'\r
99 end if\r
100 end macro\r
101 \r
102 end iterate\r
103 \r
104 iterate <instr,opcode>, and,54h, andn,55h, or,56h, xor,57h\r
105 \r
106 macro v#instr#pd? dest*,src*,src2*&\r
107 AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2\r
108 end macro\r
109 \r
110 macro v#instr#ps? dest*,src*,src2*&\r
111 AVX_512.basic_instruction_bcst VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2\r
112 end macro\r
113 \r
114 end iterate\r
115 \r
116 iterate <instr,opcode>, vbroadcastf32x2,19h, vbroadcasti32x2,59h\r
117 \r
118 macro instr? dest*,src*\r
119 AVX_512.parse_operand_k1z @dest,dest\r
120 AVX_512.parse_operand @src,src\r
121 if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')\r
122 if @dest.size = 16 | (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not 8)\r
123 err 'invalid operand size'\r
124 end if\r
125 @src.memsize = 8\r
126 AVX_512.store_instruction @dest.size,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
127 else\r
128 err 'invalid combination of operands'\r
129 end if\r
130 end macro\r
131 \r
132 end iterate\r
133 \r
134 iterate <instr,vex_mpw,opcode,msize>, vbroadcastf32x8,VEX_66_0F38_W0,1Bh,32, vbroadcastf64x2,VEX_66_0F38_W1,1Ah,16, \\r
135 vbroadcasti32x8,VEX_66_0F38_W0,5Bh,32, vbroadcasti64x2,VEX_66_0F38_W1,5Ah,16\r
136 \r
137 macro instr? dest*,src*\r
138 AVX_512.parse_operand_k1z @dest,dest\r
139 AVX_512.parse_operand @src,src\r
140 if @dest.type = 'mmreg' & @src.type = 'mem'\r
141 if @dest.size <= msize | @src.size and not msize\r
142 err 'invalid operand size'\r
143 end if\r
144 @src.memsize = msize\r
145 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
146 else\r
147 err 'invalid combination of operands'\r
148 end if\r
149 end macro\r
150 \r
151 end iterate\r
152 \r
153 iterate <instr,vex_mpw,opcode>, vcvtpd2qq,VEX_66_0F_W1,7Bh, vcvtpd2uqq,VEX_66_0F_W1,79h, \\r
154 vcvtqq2pd,VEX_F3_0F_W1,0E6h, vcvtuqq2pd,VEX_F3_0F_W1,7Ah\r
155 \r
156 macro instr? dest*,src*&\r
157 AVX_512.single_source_instruction_bcst_er vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src\r
158 end macro\r
159 \r
160 end iterate\r
161 \r
162 iterate <instr,vex_mpw,opcode>, vcvttpd2qq,VEX_66_0F_W1,7Ah, vcvttpd2uqq,VEX_66_0F_W1,78h\r
163 \r
164 macro instr? dest*,src*&\r
165 AVX_512.single_source_instruction_bcst_sae vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src\r
166 end macro\r
167 \r
168 end iterate\r
169 \r
170 iterate <instr,vex_mpw,opcode>, vcvtps2qq,VEX_66_0F_W0,7Bh, vcvtps2uqq,VEX_66_0F_W0,79h\r
171 \r
172 macro instr? dest*,src_er*&\r
173 AVX_512.parse_operand_k1z @dest,dest\r
174 match src=,er, src_er\r
175 AVX_512.parse_operand @src,src\r
176 AVX_512.parse_er @src,er,32\r
177 else\r
178 AVX_512.parse_operand_bcst @src,src_er,4\r
179 end match\r
180 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
181 if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)\r
182 err 'invalid operand size'\r
183 end if\r
184 if @src.memsize = 0\r
185 @src.memsize = @dest.size shr 1\r
186 end if\r
187 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
188 else\r
189 err 'invalid combination of operands'\r
190 end if\r
191 end macro\r
192 \r
193 end iterate\r
194 \r
195 iterate <instr,vex_mpw,opcode>, vcvtqq2ps,VEX_0F_W1,5Bh, vcvtuqq2ps,VEX_F2_0F_W1,7Ah\r
196 \r
197 macro instr? dest*,src_er*&\r
198 AVX_512.parse_operand_k1z @dest,dest\r
199 match src=,er, src_er\r
200 AVX_512.parse_operand @src,src\r
201 AVX_512.parse_er @src,er\r
202 else\r
203 AVX_512.parse_operand_bcst @src,src_er,8\r
204 end match\r
205 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
206 if @src.size = 0\r
207 if @dest.size = 16\r
208 err 'operand size not specified'\r
209 else\r
210 @src.size = 64\r
211 end if\r
212 end if\r
213 if (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size | @src.size > 64\r
214 err 'invalid operand size'\r
215 end if\r
216 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
217 else\r
218 err 'invalid combination of operands'\r
219 end if\r
220 end macro\r
221 \r
222 end iterate\r
223 \r
224 iterate <instr,vex_mpw,opcode>, vcvttps2qq,VEX_66_0F_W0,7Ah, vcvttps2uqq,VEX_66_0F_W0,78h\r
225 \r
226 macro instr? dest*,src_sae*&\r
227 AVX_512.parse_operand_k1z @dest,dest\r
228 match src=,sae, src_sae\r
229 AVX_512.parse_operand @src,src\r
230 AVX_512.parse_sae @src,sae\r
231 else\r
232 AVX_512.parse_operand_bcst @src,src_sae,4\r
233 end match\r
234 if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')\r
235 if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)\r
236 err 'invalid operand size'\r
237 end if\r
238 if @src.memsize = 0\r
239 @src.memsize = @dest.size shr 1\r
240 end if\r
241 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,@dest.mask,@dest.rm\r
242 else\r
243 err 'invalid combination of operands'\r
244 end if\r
245 end macro\r
246 \r
247 end iterate\r
248 \r
249 iterate <instr,vex_mpw,opcode,msize>, vextractf32x8,VEX_66_0F3A_W0,1Bh,32, vextractf64x2,VEX_66_0F3A_W1,19h,16, \\r
250 vextracti32x8,VEX_66_0F3A_W0,3Bh,32, vextracti64x2,VEX_66_0F3A_W1,39h,16\r
251 \r
252 macro instr? dest*,src*,aux*\r
253 AVX_512.parse_operand_k1z @dest,dest\r
254 AVX_512.parse_operand @src,src\r
255 x86.parse_operand @aux,aux\r
256 if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'\r
257 if @dest.size and not msize | @src.size <= msize | @aux.size and not 1\r
258 err 'invalid operand size'\r
259 end if\r
260 @dest.memsize = msize\r
261 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest,@dest.mask,@src.rm,,1,@aux.imm\r
262 else\r
263 err 'invalid combination of operands'\r
264 end if\r
265 end macro\r
266 \r
267 end iterate\r
268 \r
269 iterate <instr,vex_mpw,opcode,msize>, vinsertf32x8,VEX_66_0F3A_W0,1Ah,32, vinsertf64x2,VEX_66_0F3A_W1,18h,16, \\r
270 vinserti32x8,VEX_66_0F3A_W0,3Ah,32, vinserti64x2,VEX_66_0F3A_W1,38h,16\r
271 \r
272 macro instr? dest*,src*,src2*,aux*\r
273 AVX_512.parse_operand_k1z @dest,dest\r
274 AVX_512.parse_operand @src,src\r
275 AVX_512.parse_operand @src2,src2\r
276 x86.parse_operand @aux,aux\r
277 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mmreg' | @src2.type = 'mem') & @aux.type = 'imm'\r
278 if @dest.size <= msize | @src.size <= msize | @src2.size and not msize | @aux.size and not 1\r
279 err 'invalid operand size'\r
280 end if\r
281 @src2.memsize = msize\r
282 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src2,@dest.mask,@dest.rm,@src.rm,1,@aux.imm\r
283 else\r
284 err 'invalid combination of operands'\r
285 end if\r
286 end macro\r
287 \r
288 end iterate\r
289 \r
290 iterate <instr,unit,vex_mpw>, vfpclasspd,8,VEX_66_0F3A_W1, vfpclassps,4,VEX_66_0F3A_W0\r
291 \r
292 macro instr? dest*,src*,aux*\r
293 AVX_512.parse_operand_k1 @dest,dest\r
294 AVX_512.parse_operand_bcst @src,src,unit\r
295 x86.parse_operand @aux,aux\r
296 if @dest.type = 'maskreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
297 if @src.size = 0\r
298 err 'operand size not specified'\r
299 else if (@src.size <> 16 & @src.size <> 32 & @src.size <> 64) | @aux.size and not 1\r
300 err 'invalid operand size'\r
301 end if\r
302 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,66h,@src,@dest.mask,@dest.rm,,1,@aux.imm\r
303 else\r
304 err 'invalid combination of operands'\r
305 end if\r
306 end macro\r
307 \r
308 end iterate\r
309 \r
310 iterate <instr,unit,vex_mpw>, vfpclasssd,8,VEX_66_0F3A_W1, vfpclassss,4,VEX_66_0F3A_W0\r
311 \r
312 macro instr? dest*,src*,aux*\r
313 AVX_512.parse_operand_k1 @dest,dest\r
314 AVX_512.parse_operand @src,src\r
315 x86.parse_operand @aux,aux\r
316 if @dest.type = 'maskreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'\r
317 if (@src.type = 'mem' & @src.size and not unit) | (@src.type = 'mmreg' & @src.size <> 16) | @aux.size and not 1\r
318 err 'invalid operand size'\r
319 end if\r
320 @src.memsize = 16\r
321 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED,67h,@src,@dest.mask,@dest.rm,,1,@aux.imm\r
322 else\r
323 err 'invalid combination of operands'\r
324 end if\r
325 end macro\r
326 \r
327 end iterate\r
328 \r
329 macro vpextrd? dest*,src*,aux*\r
330 AVX_512.parse_operand @dest,dest\r
331 AVX_512.parse_operand @src,src\r
332 x86.parse_operand @aux,aux\r
333 if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'\r
334 if (@dest.type = 'reg' & @dest.size <> 4 & (x86.mode < 64 | @dest.size <> 8)) | (@dest.type = 'mem' & @dest.size and not 4) | @src.size <> 16 | @aux.size and not 1\r
335 err 'invalid operand size'\r
336 end if\r
337 @dest.memsize = 4\r
338 AVX_512.store_instruction 16,VEX_66_0F3A_W0,EVEX_AS_VEX,16h,@dest,0,@src.rm,,1,@aux.imm\r
339 else\r
340 err 'invalid combination of operands'\r
341 end if\r
342 end macro\r
343 \r
344 macro vpinsrd? dest*,src*,src2*,aux*\r
345 AVX_512.parse_operand @dest,dest\r
346 AVX_512.parse_operand @src,src\r
347 AVX_512.parse_operand @src2,src2\r
348 x86.parse_operand @aux,aux\r
349 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem') & @aux.type = 'imm'\r
350 if @dest.size <> 16 | @src.size <> 16 | (@src2.type = 'reg' & @src2.size <> 4) | (@src2.type = 'mem' & @src2.size and not 4) | @aux.size and not 1\r
351 err 'invalid operand size'\r
352 end if\r
353 @src2.memsize = 4\r
354 AVX_512.store_instruction 16,VEX_66_0F3A_W0,EVEX_AS_VEX,22h,@src2,0,@dest.rm,@src.rm,1,@aux.imm\r
355 else\r
356 err 'invalid combination of operands'\r
357 end if\r
358 end macro\r
359 \r
360 macro vpextrq? dest*,src*,aux*\r
361 AVX_512.parse_operand @dest,dest\r
362 AVX_512.parse_operand @src,src\r
363 x86.parse_operand @aux,aux\r
364 if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'\r
365 if @dest.size and not 8 | @src.size <> 16 | @aux.size and not 1\r
366 err 'invalid operand size'\r
367 end if\r
368 if x86.mode < 64\r
369 err 'instruction requires long mode'\r
370 end if\r
371 @dest.memsize = 8\r
372 AVX_512.store_instruction 16,VEX_66_0F3A_W1,EVEX_AS_VEX,16h,@dest,0,@src.rm,,1,@aux.imm\r
373 else\r
374 err 'invalid combination of operands'\r
375 end if\r
376 end macro\r
377 \r
378 macro vpinsrq? dest*,src*,src2*,aux*\r
379 AVX_512.parse_operand @dest,dest\r
380 AVX_512.parse_operand @src,src\r
381 x86.parse_operand @src2,src2\r
382 x86.parse_operand @aux,aux\r
383 if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem') & @aux.type = 'imm'\r
384 if @dest.size <> 16 | @src.size <> 16 | @src2.size and not 8 | @aux.size and not 1\r
385 err 'invalid operand size'\r
386 end if\r
387 if x86.mode < 64\r
388 err 'instruction requires long mode'\r
389 end if\r
390 @src2.memsize = 8\r
391 AVX_512.store_instruction 16,VEX_66_0F3A_W1,EVEX_AS_VEX,22h,@src2,0,@dest.rm,@src.rm,1,@aux.imm\r
392 else\r
393 err 'invalid combination of operands'\r
394 end if\r
395 end macro\r
396 \r
397 macro vpmullq? dest*,src*,src2*\r
398 AVX_512.basic_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,40h,8,dest,src,src2\r
399 end macro\r
400 \r
401 iterate <instr,vex_mpw,opcode>, vpmovm2d,VEX_F3_0F38_W0,38h, vpmovm2q,VEX_F3_0F38_W1,38h\r
402 \r
403 macro instr? dest*,src*\r
404 AVX_512.parse_operand @dest,dest\r
405 AVX_512.parse_operand @src,src\r
406 if @dest.type = 'mmreg' & @src.type = 'maskreg'\r
407 AVX_512.store_instruction @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,0,@dest.rm\r
408 else\r
409 err 'invalid combination of operands'\r
410 end if\r
411 end macro\r
412 \r
413 end iterate\r
414 \r
415 iterate <instr,vex_mpw,opcode>, vpmovd2m,VEX_F3_0F38_W0,39h, vpmovq2m,VEX_F3_0F38_W1,39h\r
416 \r
417 macro instr? dest*,src*\r
418 AVX_512.parse_operand @dest,dest\r
419 AVX_512.parse_operand @src,src\r
420 if @dest.type = 'maskreg' & @src.type = 'mmreg'\r
421 AVX_512.store_instruction @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@src,0,@dest.rm\r
422 else\r
423 err 'invalid combination of operands'\r
424 end if\r
425 end macro\r
426 \r
427 end iterate\r
428 \r
429 iterate <instr,opcode>, range,50h\r
430 \r
431 macro v#instr#pd? dest*,src*,src2*,aux*&\r
432 AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2,aux\r
433 end macro\r
434 \r
435 macro v#instr#ps? dest*,src*,src2*,aux*&\r
436 AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2,aux\r
437 end macro\r
438 \r
439 macro v#instr#sd? dest*,src*,src2*,aux*&\r
440 AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,opcode+1,8,dest,src,src2,aux\r
441 end macro\r
442 \r
443 macro v#instr#ss? dest*,src*,src2*,aux*&\r
444 AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,opcode+1,4,dest,src,src2,aux\r
445 end macro\r
446 \r
447 end iterate\r
448 \r
449 macro vreducepd? dest*,src*,aux*&\r
450 AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,56h,8,dest,src,aux\r
451 end macro\r
452 \r
453 macro vreduceps? dest*,src*,aux*&\r
454 AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,56h,4,dest,src,aux\r
455 end macro\r
456 \r
457 macro vreducesd? dest*,src*,src2*,aux*&\r
458 AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,57h,8,dest,src,src2,aux\r
459 end macro\r
460 \r
461 macro vreducess? dest*,src*,src2*,aux*&\r
462 AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,57h,4,dest,src,src2,aux\r
463 end macro\r