4 macro andn? dest*,src*,src2*
\r
5 x86.parse_operand @dest,dest
\r
6 x86.parse_operand @src,src
\r
7 x86.parse_operand @src2,src2
\r
8 if @dest.type = 'reg' & @src.type = 'reg' & (@src2.type = 'mem' | @src2.type = 'reg')
\r
10 err 'invalid operand size'
\r
11 else if @src.size <> @dest.size | @src2.size and not @dest.size
\r
12 err 'operand sizes do not match'
\r
16 err 'instruction requires long mode'
\r
18 AVX.store_instruction 16,VEX_0F38_W1,0F2h,@src2,@dest.rm,@src.rm
\r
20 AVX.store_instruction 16,VEX_0F38_W0,0F2h,@src2,@dest.rm,@src.rm
\r
23 err 'invalid combination of operands'
\r
27 macro bextr? dest*,src*,src2*
\r
28 x86.parse_operand @dest,dest
\r
29 x86.parse_operand @src,src
\r
30 x86.parse_operand @src2,src2
\r
31 if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'reg') & @src2.type = 'reg'
\r
33 err 'invalid operand size'
\r
34 else if @src.size and not @dest.size | @src2.size <> @dest.size
\r
35 err 'operand sizes do not match'
\r
39 err 'instruction requires long mode'
\r
41 AVX.store_instruction 16,VEX_0F38_W1,0F7h,@src,@dest.rm,@src2.rm
\r
43 AVX.store_instruction 16,VEX_0F38_W0,0F7h,@src,@dest.rm,@src2.rm
\r
46 err 'invalid combination of operands'
\r
50 iterate <instr,opcode,postbyte>, blsi,0F3h,3, blmsk,0F3h,2, blsr,0F3h,1
\r
52 macro instr? dest*,src*
\r
53 x86.parse_operand @dest,dest
\r
54 x86.parse_operand @src,src
\r
55 if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'reg')
\r
57 err 'invalid operand size'
\r
58 else if @src.size and not @dest.size
\r
59 err 'operand sizes do not match'
\r
63 err 'instruction requires long mode'
\r
65 AVX.store_instruction 16,VEX_0F38_W1,opcode,@src,postbyte,@dest.rm
\r
67 AVX.store_instruction 16,VEX_0F38_W0,opcode,@src,postbyte,@dest.rm
\r
70 err 'invalid combination of operands'
\r
76 iterate <instr,opcode>, lzcnt,0BDh, tzcnt,0BCh
\r
78 macro instr? dest*,src*
\r
79 x86.parse_operand @dest,dest
\r
80 x86.parse_operand @src,src
\r
81 if @dest.type = 'reg' & ( @src.type = 'reg' | @src.type = 'mem' )
\r
82 if @src.size and not @dest.size
\r
83 err 'operand sizes do not match'
\r
85 @src.opcode_prefix = 0F3h
\r
87 x86.select_operand_prefix @src,@dest.size
\r
88 x86.store_instruction <0Fh,opcode>,@src,@dest.rm
\r
90 err 'invalid operand size'
\r
93 err 'invalid combination of operands'
\r