Add USB PID/VID pair to JTAG configuration.
[fpc-iii.git] / hardware / fpc-iii.pro
blob07d804f357b1f83f3351f80e3a625ed520cd8538
1 update=Thu 23 Jan 2020 10:28:29 PM MST
2 version=1
3 last_client=kicad
4 [general]
5 version=1
6 RootSch=
7 BoardNm=
8 [cvpcb]
9 version=1
10 NetIExt=net
11 [eeschema]
12 version=1
13 LibDir=
14 [eeschema/libraries]
15 [schematic_editor]
16 version=1
17 PageLayoutDescrFile=fpc-iii.kicad_wks
18 PlotDirectoryName=
19 SubpartIdSeparator=0
20 SubpartFirstId=65
21 NetFmtName=
22 SpiceAjustPassiveValues=0
23 LabSize=50
24 ERC_TestSimilarLabels=1
25 [pcbnew]
26 version=1
27 PageLayoutDescrFile=fpc-iii.kicad_wks
28 LastNetListRead=
29 CopperLayerCount=4
30 BoardThickness=1.6
31 AllowMicroVias=0
32 AllowBlindVias=0
33 RequireCourtyardDefinitions=0
34 ProhibitOverlappingCourtyards=1
35 MinTrackWidth=0.125
36 MinViaDiameter=0.4
37 MinViaDrill=0.2
38 MinMicroViaDiameter=0.2
39 MinMicroViaDrill=0.09999999999999999
40 MinHoleToHole=0.25
41 TrackWidth1=0.15
42 TrackWidth2=0.125
43 TrackWidth3=0.15
44 TrackWidth4=0.2
45 TrackWidth5=0.3
46 TrackWidth6=0.8
47 ViaDiameter1=0.4
48 ViaDrill1=0.2
49 ViaDiameter2=0.4
50 ViaDrill2=0.2
51 ViaDiameter3=0.5
52 ViaDrill3=0.25
53 dPairWidth1=0.2
54 dPairGap1=0.25
55 dPairViaGap1=0.25
56 dPairWidth2=0.125
57 dPairGap2=0.1
58 dPairViaGap2=0.25
59 SilkLineWidth=0.12
60 SilkTextSizeV=1
61 SilkTextSizeH=1
62 SilkTextSizeThickness=0.15
63 SilkTextItalic=0
64 SilkTextUpright=1
65 CopperLineWidth=0.2
66 CopperTextSizeV=1.5
67 CopperTextSizeH=1.5
68 CopperTextThickness=0.3
69 CopperTextItalic=0
70 CopperTextUpright=1
71 EdgeCutLineWidth=0.05
72 CourtyardLineWidth=0.05
73 OthersLineWidth=0.15
74 OthersTextSizeV=1
75 OthersTextSizeH=1
76 OthersTextSizeThickness=0.15
77 OthersTextItalic=0
78 OthersTextUpright=1
79 SolderMaskClearance=0.051
80 SolderMaskMinWidth=0.25
81 SolderPasteClearance=0
82 SolderPasteRatio=-0
83 [pcbnew/Layer.F.Cu]
84 Name=F.Cu
85 Type=0
86 Enabled=1
87 [pcbnew/Layer.In1.Cu]
88 Name=In1.Cu
89 Type=1
90 Enabled=1
91 [pcbnew/Layer.In2.Cu]
92 Name=In2.Cu
93 Type=1
94 Enabled=1
95 [pcbnew/Layer.In3.Cu]
96 Name=In3.Cu
97 Type=0
98 Enabled=0
99 [pcbnew/Layer.In4.Cu]
100 Name=In4.Cu
101 Type=0
102 Enabled=0
103 [pcbnew/Layer.In5.Cu]
104 Name=In5.Cu
105 Type=0
106 Enabled=0
107 [pcbnew/Layer.In6.Cu]
108 Name=In6.Cu
109 Type=0
110 Enabled=0
111 [pcbnew/Layer.In7.Cu]
112 Name=In7.Cu
113 Type=0
114 Enabled=0
115 [pcbnew/Layer.In8.Cu]
116 Name=In8.Cu
117 Type=0
118 Enabled=0
119 [pcbnew/Layer.In9.Cu]
120 Name=In9.Cu
121 Type=0
122 Enabled=0
123 [pcbnew/Layer.In10.Cu]
124 Name=In10.Cu
125 Type=0
126 Enabled=0
127 [pcbnew/Layer.In11.Cu]
128 Name=In11.Cu
129 Type=0
130 Enabled=0
131 [pcbnew/Layer.In12.Cu]
132 Name=In12.Cu
133 Type=0
134 Enabled=0
135 [pcbnew/Layer.In13.Cu]
136 Name=In13.Cu
137 Type=0
138 Enabled=0
139 [pcbnew/Layer.In14.Cu]
140 Name=In14.Cu
141 Type=0
142 Enabled=0
143 [pcbnew/Layer.In15.Cu]
144 Name=In15.Cu
145 Type=0
146 Enabled=0
147 [pcbnew/Layer.In16.Cu]
148 Name=In16.Cu
149 Type=0
150 Enabled=0
151 [pcbnew/Layer.In17.Cu]
152 Name=In17.Cu
153 Type=0
154 Enabled=0
155 [pcbnew/Layer.In18.Cu]
156 Name=In18.Cu
157 Type=0
158 Enabled=0
159 [pcbnew/Layer.In19.Cu]
160 Name=In19.Cu
161 Type=0
162 Enabled=0
163 [pcbnew/Layer.In20.Cu]
164 Name=In20.Cu
165 Type=0
166 Enabled=0
167 [pcbnew/Layer.In21.Cu]
168 Name=In21.Cu
169 Type=0
170 Enabled=0
171 [pcbnew/Layer.In22.Cu]
172 Name=In22.Cu
173 Type=0
174 Enabled=0
175 [pcbnew/Layer.In23.Cu]
176 Name=In23.Cu
177 Type=0
178 Enabled=0
179 [pcbnew/Layer.In24.Cu]
180 Name=In24.Cu
181 Type=0
182 Enabled=0
183 [pcbnew/Layer.In25.Cu]
184 Name=In25.Cu
185 Type=0
186 Enabled=0
187 [pcbnew/Layer.In26.Cu]
188 Name=In26.Cu
189 Type=0
190 Enabled=0
191 [pcbnew/Layer.In27.Cu]
192 Name=In27.Cu
193 Type=0
194 Enabled=0
195 [pcbnew/Layer.In28.Cu]
196 Name=In28.Cu
197 Type=0
198 Enabled=0
199 [pcbnew/Layer.In29.Cu]
200 Name=In29.Cu
201 Type=0
202 Enabled=0
203 [pcbnew/Layer.In30.Cu]
204 Name=In30.Cu
205 Type=0
206 Enabled=0
207 [pcbnew/Layer.B.Cu]
208 Name=B.Cu
209 Type=0
210 Enabled=1
211 [pcbnew/Layer.B.Adhes]
212 Enabled=1
213 [pcbnew/Layer.F.Adhes]
214 Enabled=1
215 [pcbnew/Layer.B.Paste]
216 Enabled=1
217 [pcbnew/Layer.F.Paste]
218 Enabled=1
219 [pcbnew/Layer.B.SilkS]
220 Enabled=1
221 [pcbnew/Layer.F.SilkS]
222 Enabled=1
223 [pcbnew/Layer.B.Mask]
224 Enabled=1
225 [pcbnew/Layer.F.Mask]
226 Enabled=1
227 [pcbnew/Layer.Dwgs.User]
228 Enabled=1
229 [pcbnew/Layer.Cmts.User]
230 Enabled=1
231 [pcbnew/Layer.Eco1.User]
232 Enabled=1
233 [pcbnew/Layer.Eco2.User]
234 Enabled=1
235 [pcbnew/Layer.Edge.Cuts]
236 Enabled=1
237 [pcbnew/Layer.Margin]
238 Enabled=1
239 [pcbnew/Layer.B.CrtYd]
240 Enabled=1
241 [pcbnew/Layer.F.CrtYd]
242 Enabled=1
243 [pcbnew/Layer.B.Fab]
244 Enabled=1
245 [pcbnew/Layer.F.Fab]
246 Enabled=1
247 [pcbnew/Layer.Rescue]
248 Enabled=0
249 [pcbnew/Netclasses]
250 [pcbnew/Netclasses/Default]
251 Name=Default
252 Clearance=0.1
253 TrackWidth=0.15
254 ViaDiameter=0.4
255 ViaDrill=0.2
256 uViaDiameter=0.3
257 uViaDrill=0.1
258 dPairWidth=0.2
259 dPairGap=0.25
260 dPairViaGap=0.25
261 [pcbnew/Netclasses/1]
262 Name=DDR
263 Clearance=0.1
264 TrackWidth=0.15
265 ViaDiameter=0.4
266 ViaDrill=0.2
267 uViaDiameter=0.3
268 uViaDrill=0.1
269 dPairWidth=0.125
270 dPairGap=0.1
271 dPairViaGap=0.25
272 [pcbnew/Netclasses/2]
273 Name=Ethernet
274 Clearance=0.1
275 TrackWidth=0.15
276 ViaDiameter=0.4
277 ViaDrill=0.2
278 uViaDiameter=0.3
279 uViaDrill=0.1
280 dPairWidth=0.125
281 dPairGap=0.1
282 dPairViaGap=0.25
283 [pcbnew/Netclasses/3]
284 Name=TMDS
285 Clearance=0.1
286 TrackWidth=0.15
287 ViaDiameter=0.4
288 ViaDrill=0.2
289 uViaDiameter=0.3
290 uViaDrill=0.1
291 dPairWidth=0.125
292 dPairGap=0.1
293 dPairViaGap=0.25
294 [pcbnew/Netclasses/4]
295 Name=USB
296 Clearance=0.1
297 TrackWidth=0.15
298 ViaDiameter=0.4
299 ViaDrill=0.2
300 uViaDiameter=0.3
301 uViaDrill=0.1
302 dPairWidth=0.2
303 dPairGap=0.18
304 dPairViaGap=0.25