usr.sbin/bhyve/vga.h

   1 /*-
   2  * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef _VGA_H_
  30 #define _VGA_H_
  31
  32 #define VGA_IOPORT_START                0x3c0
  33 #define VGA_IOPORT_END                  0x3df
  34
  35 /* General registers */
  36 #define GEN_INPUT_STS0_PORT             0x3c2
  37 #define GEN_FEATURE_CTRL_PORT           0x3ca
  38 #define GEN_MISC_OUTPUT_PORT            0x3cc
  39 #define GEN_INPUT_STS1_MONO_PORT        0x3ba
  40 #define GEN_INPUT_STS1_COLOR_PORT       0x3da
  41 #define  GEN_IS1_VR                     0x08    /* Vertical retrace */
  42 #define  GEN_IS1_DE                     0x01    /* Display enable not */
  43
  44 /* Attribute controller registers. */
  45 #define ATC_IDX_PORT                    0x3c0
  46 #define ATC_DATA_PORT                   0x3c1
  47
  48 #define ATC_IDX_MASK                    0x1f
  49 #define ATC_PALETTE0                    0
  50 #define ATC_PALETTE15                   15
  51 #define ATC_MODE_CONTROL                16
  52 #define  ATC_MC_IPS                     0x80    /* Internal palette size */
  53 #define  ATC_MC_GA                      0x01    /* Graphics/alphanumeric */
  54 #define ATC_OVERSCAN_COLOR              17
  55 #define ATC_COLOR_PLANE_ENABLE          18
  56 #define ATC_HORIZ_PIXEL_PANNING         19
  57 #define ATC_COLOR_SELECT                20
  58 #define  ATC_CS_C67                     0x0c    /* Color select bits 6+7 */
  59 #define  ATC_CS_C45                     0x03    /* Color select bits 4+5 */
  60
  61 /* Sequencer registers. */
  62 #define SEQ_IDX_PORT                    0x3c4
  63 #define SEQ_DATA_PORT                   0x3c5
  64
  65 #define SEQ_RESET                       0
  66 #define SEQ_RESET_ASYNC                 0x1
  67 #define SEQ_RESET_SYNC                  0x2
  68 #define SEQ_CLOCKING_MODE               1
  69 #define  SEQ_CM_SO                      0x20    /* Screen off */
  70 #define  SEQ_CM_89                      0x01    /* 8/9 dot clock */
  71 #define SEQ_MAP_MASK                    2
  72 #define SEQ_CHAR_MAP_SELECT             3
  73 #define  SEQ_CMS_SAH                    0x20    /* Char map A bit 2 */
  74 #define  SEQ_CMS_SAH_SHIFT              5
  75 #define  SEQ_CMS_SA                     0x0c    /* Char map A bits 0+1 */
  76 #define  SEQ_CMS_SA_SHIFT               2
  77 #define  SEQ_CMS_SBH                    0x10    /* Char map B bit 2 */
  78 #define  SEQ_CMS_SBH_SHIFT              4
  79 #define  SEQ_CMS_SB                     0x03    /* Char map B bits 0+1 */
  80 #define  SEQ_CMS_SB_SHIFT               0
  81 #define SEQ_MEMORY_MODE                 4
  82 #define  SEQ_MM_C4                      0x08    /* Chain 4 */
  83 #define  SEQ_MM_OE                      0x04    /* Odd/even */
  84 #define  SEQ_MM_EM                      0x02    /* Extended memory */
  85
  86 /* Graphics controller registers. */
  87 #define GC_IDX_PORT                     0x3ce
  88 #define GC_DATA_PORT                    0x3cf
  89
  90 #define GC_SET_RESET                    0
  91 #define GC_ENABLE_SET_RESET             1
  92 #define GC_COLOR_COMPARE                2
  93 #define GC_DATA_ROTATE                  3
  94 #define GC_READ_MAP_SELECT              4
  95 #define GC_MODE                         5
  96 #define  GC_MODE_OE                     0x10    /* Odd/even */
  97 #define  GC_MODE_C4                     0x04    /* Chain 4 */
  98
  99 #define GC_MISCELLANEOUS                6
 100 #define  GC_MISC_GM                     0x01    /* Graphics/alphanumeric */
 101 #define  GC_MISC_MM                     0x0c    /* memory map */
 102 #define  GC_MISC_MM_SHIFT       2
 103 #define GC_COLOR_DONT_CARE              7
 104 #define GC_BIT_MASK                     8
 105
 106 /* CRT controller registers. */
 107 #define CRTC_IDX_MONO_PORT              0x3b4
 108 #define CRTC_DATA_MONO_PORT             0x3b5
 109 #define CRTC_IDX_COLOR_PORT             0x3d4
 110 #define CRTC_DATA_COLOR_PORT            0x3d5
 111
 112 #define CRTC_HORIZ_TOTAL                0
 113 #define CRTC_HORIZ_DISP_END             1
 114 #define CRTC_START_HORIZ_BLANK          2
 115 #define CRTC_END_HORIZ_BLANK            3
 116 #define CRTC_START_HORIZ_RETRACE        4
 117 #define CRTC_END_HORIZ_RETRACE          5
 118 #define CRTC_VERT_TOTAL                 6
 119 #define CRTC_OVERFLOW                   7
 120 #define  CRTC_OF_VRS9                   0x80    /* VRS bit 9 */
 121 #define  CRTC_OF_VRS9_SHIFT             7
 122 #define  CRTC_OF_VDE9                   0x40    /* VDE bit 9 */
 123 #define  CRTC_OF_VDE9_SHIFT             6
 124 #define  CRTC_OF_VRS8                   0x04    /* VRS bit 8 */
 125 #define  CRTC_OF_VRS8_SHIFT             2
 126 #define  CRTC_OF_VDE8                   0x02    /* VDE bit 8 */
 127 #define  CRTC_OF_VDE8_SHIFT             1
 128 #define CRTC_PRESET_ROW_SCAN            8
 129 #define CRTC_MAX_SCAN_LINE              9
 130 #define  CRTC_MSL_MSL                   0x1f
 131 #define CRTC_CURSOR_START               10
 132 #define  CRTC_CS_CO                     0x20    /* Cursor off */
 133 #define  CRTC_CS_CS                     0x1f    /* Cursor start */
 134 #define CRTC_CURSOR_END                 11
 135 #define  CRTC_CE_CE                     0x1f    /* Cursor end */
 136 #define CRTC_START_ADDR_HIGH            12
 137 #define CRTC_START_ADDR_LOW             13
 138 #define CRTC_CURSOR_LOC_HIGH            14
 139 #define CRTC_CURSOR_LOC_LOW             15
 140 #define CRTC_VERT_RETRACE_START         16
 141 #define CRTC_VERT_RETRACE_END           17
 142 #define  CRTC_VRE_MASK                  0xf
 143 #define CRTC_VERT_DISP_END              18
 144 #define CRTC_OFFSET                     19
 145 #define CRTC_UNDERLINE_LOC              20
 146 #define CRTC_START_VERT_BLANK           21
 147 #define CRTC_END_VERT_BLANK             22
 148 #define CRTC_MODE_CONTROL               23
 149 #define  CRTC_MC_TE                     0x80    /* Timing enable */
 150 #define CRTC_LINE_COMPARE               24
 151
 152 /* DAC registers */
 153 #define DAC_MASK                        0x3c6
 154 #define DAC_IDX_RD_PORT                 0x3c7
 155 #define DAC_IDX_WR_PORT                 0x3c8
 156 #define DAC_DATA_PORT                   0x3c9
 157
 158 void    *vga_init(int io_only);
 159
 160 #endif /* _VGA_H_ */