2 * Copyright (c) 2007 Yahoo!, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 static const char rcsid
[] =
36 #include <sys/types.h>
40 #include <sys/agpio.h>
41 #include <sys/pciio.h>
43 #include <dev/agp/agpreg.h>
44 #include <dev/pci/pcireg.h>
49 cap_power(int fd
, struct pci_conf
*p
, uint8_t ptr
)
53 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_POWER_CAP
, 2);
54 status
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_POWER_STATUS
, 2);
55 printf("powerspec %d supports D0%s%s D3 current D%d",
57 cap
& PCIM_PCAP_D1SUPP
? " D1" : "",
58 cap
& PCIM_PCAP_D2SUPP
? " D2" : "",
59 status
& PCIM_PSTAT_DMASK
);
63 cap_agp(int fd
, struct pci_conf
*p
, uint8_t ptr
)
65 uint32_t status
, command
;
67 status
= read_config(fd
, &p
->pc_sel
, ptr
+ AGP_STATUS
, 4);
68 command
= read_config(fd
, &p
->pc_sel
, ptr
+ AGP_CAPID
, 4);
70 if (AGP_MODE_GET_MODE_3(status
)) {
72 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V3_RATE_8x
)
74 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V3_RATE_4x
)
77 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_4x
)
79 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_2x
)
81 if (AGP_MODE_GET_RATE(status
) & AGP_MODE_V2_RATE_1x
)
84 if (AGP_MODE_GET_SBA(status
))
86 if (AGP_MODE_GET_AGP(command
)) {
87 printf("enabled at ");
88 if (AGP_MODE_GET_MODE_3(command
)) {
90 switch (AGP_MODE_GET_RATE(command
)) {
91 case AGP_MODE_V3_RATE_8x
:
94 case AGP_MODE_V3_RATE_4x
:
99 switch (AGP_MODE_GET_RATE(command
)) {
100 case AGP_MODE_V2_RATE_4x
:
103 case AGP_MODE_V2_RATE_2x
:
106 case AGP_MODE_V2_RATE_1x
:
110 if (AGP_MODE_GET_SBA(command
))
117 cap_vpd(int fd
, struct pci_conf
*p
, uint8_t ptr
)
124 cap_msi(int fd
, struct pci_conf
*p
, uint8_t ptr
)
129 ctrl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSI_CTRL
, 2);
130 msgnum
= 1 << ((ctrl
& PCIM_MSICTRL_MMC_MASK
) >> 1);
131 printf("MSI supports %d message%s%s%s ", msgnum
,
132 (msgnum
== 1) ? "" : "s",
133 (ctrl
& PCIM_MSICTRL_64BIT
) ? ", 64 bit" : "",
134 (ctrl
& PCIM_MSICTRL_VECTOR
) ? ", vector masks" : "");
135 if (ctrl
& PCIM_MSICTRL_MSI_ENABLE
) {
136 msgnum
= 1 << ((ctrl
& PCIM_MSICTRL_MME_MASK
) >> 4);
137 printf("enabled with %d message%s", msgnum
,
138 (msgnum
== 1) ? "" : "s");
143 cap_pcix(int fd
, struct pci_conf
*p
, uint8_t ptr
)
146 int comma
, max_splits
, max_burst_read
;
148 status
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIXR_STATUS
, 4);
150 if (status
& PCIXM_STATUS_64BIT
)
152 if ((p
->pc_hdr
& PCIM_HDRTYPE
) == 1)
156 if (status
& PCIXM_STATUS_133CAP
) {
157 printf("%s 133MHz", comma
? "," : "");
160 if (status
& PCIXM_STATUS_266CAP
) {
161 printf("%s 266MHz", comma
? "," : "");
164 if (status
& PCIXM_STATUS_533CAP
) {
165 printf("%s 533MHz", comma
? "," : "");
168 if ((p
->pc_hdr
& PCIM_HDRTYPE
) == 1)
170 switch (status
& PCIXM_STATUS_MAX_READ
) {
171 case PCIXM_STATUS_MAX_READ_512
:
172 max_burst_read
= 512;
174 case PCIXM_STATUS_MAX_READ_1024
:
175 max_burst_read
= 1024;
177 case PCIXM_STATUS_MAX_READ_2048
:
178 max_burst_read
= 2048;
180 case PCIXM_STATUS_MAX_READ_4096
:
181 max_burst_read
= 4096;
184 switch (status
& PCIXM_STATUS_MAX_SPLITS
) {
185 case PCIXM_STATUS_MAX_SPLITS_1
:
188 case PCIXM_STATUS_MAX_SPLITS_2
:
191 case PCIXM_STATUS_MAX_SPLITS_3
:
194 case PCIXM_STATUS_MAX_SPLITS_4
:
197 case PCIXM_STATUS_MAX_SPLITS_8
:
200 case PCIXM_STATUS_MAX_SPLITS_12
:
203 case PCIXM_STATUS_MAX_SPLITS_16
:
206 case PCIXM_STATUS_MAX_SPLITS_32
:
210 printf("%s %d burst read, %d split transaction%s", comma
? "," : "",
211 max_burst_read
, max_splits
, max_splits
== 1 ? "" : "s");
215 cap_ht(int fd
, struct pci_conf
*p
, uint8_t ptr
)
220 command
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_HT_COMMAND
, 2);
222 if ((command
& 0xe000) == PCIM_HTCAP_SLAVE
)
224 else if ((command
& 0xe000) == PCIM_HTCAP_HOST
)
227 switch (command
& PCIM_HTCMD_CAP_MASK
) {
228 case PCIM_HTCAP_SWITCH
:
231 case PCIM_HTCAP_INTERRUPT
:
234 case PCIM_HTCAP_REVISION_ID
:
235 printf("revision ID");
237 case PCIM_HTCAP_UNITID_CLUMPING
:
238 printf("unit ID clumping");
240 case PCIM_HTCAP_EXT_CONFIG_SPACE
:
241 printf("extended config space");
243 case PCIM_HTCAP_ADDRESS_MAPPING
:
244 printf("address mapping");
246 case PCIM_HTCAP_MSI_MAPPING
:
247 printf("MSI %saddress window %s at 0x",
248 command
& PCIM_HTCMD_MSI_FIXED
? "fixed " : "",
249 command
& PCIM_HTCMD_MSI_ENABLE
? "enabled" :
251 if (command
& PCIM_HTCMD_MSI_FIXED
)
254 reg
= read_config(fd
, &p
->pc_sel
,
255 ptr
+ PCIR_HTMSI_ADDRESS_HI
, 4);
258 reg
= read_config(fd
, &p
->pc_sel
,
259 ptr
+ PCIR_HTMSI_ADDRESS_LO
, 4);
263 case PCIM_HTCAP_DIRECT_ROUTE
:
264 printf("direct route");
266 case PCIM_HTCAP_VCSET
:
269 case PCIM_HTCAP_RETRY_MODE
:
270 printf("retry mode");
272 case PCIM_HTCAP_X86_ENCODING
:
273 printf("X86 encoding");
276 printf("unknown %02x", command
);
282 cap_vendor(int fd
, struct pci_conf
*p
, uint8_t ptr
)
286 length
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_VENDOR_LENGTH
, 1);
287 printf("vendor (length %d)", length
);
288 if (p
->pc_vendor
== 0x8086) {
292 version
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_VENDOR_DATA
,
294 printf(" Intel cap %d version %d", version
>> 4, version
& 0xf);
295 if (version
>> 4 == 1 && length
== 12) {
296 /* Feature Detection */
301 fvec
= read_config(fd
, &p
->pc_sel
, ptr
+
302 PCIR_VENDOR_DATA
+ 5, 4);
303 printf("\n\t\t features:");
304 if (fvec
& (1 << 0)) {
308 fvec
= read_config(fd
, &p
->pc_sel
, ptr
+
309 PCIR_VENDOR_DATA
+ 1, 4);
310 if (fvec
& (1 << 21)) {
311 printf("%s Quick Resume", comma
? "," : "");
314 if (fvec
& (1 << 18)) {
315 printf("%s SATA RAID-5", comma
? "," : "");
318 if (fvec
& (1 << 9)) {
319 printf("%s Mobile", comma
? "," : "");
322 if (fvec
& (1 << 7)) {
323 printf("%s 6 PCI-e x1 slots", comma
? "," : "");
326 printf("%s 4 PCI-e x1 slots", comma
? "," : "");
329 if (fvec
& (1 << 5)) {
330 printf("%s SATA RAID-0/1/10", comma
? "," : "");
333 if (fvec
& (1 << 3)) {
334 printf("%s SATA AHCI", comma
? "," : "");
342 cap_debug(int fd
, struct pci_conf
*p
, uint8_t ptr
)
346 debug_port
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_DEBUG_PORT
, 2);
347 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port
&
348 PCIM_DEBUG_PORT_OFFSET
, PCIR_BAR(debug_port
>> 13));
352 cap_subvendor(int fd
, struct pci_conf
*p
, uint8_t ptr
)
356 id
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_SUBVENDCAP_ID
, 4);
357 printf("PCI Bridge card=0x%08x", id
);
361 cap_express(int fd
, struct pci_conf
*p
, uint8_t ptr
)
365 flags
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_EXPRESS_FLAGS
, 2);
366 printf("PCI-Express %d ", flags
& PCIM_EXP_FLAGS_VERSION
);
367 switch (flags
& PCIM_EXP_FLAGS_TYPE
) {
368 case PCIM_EXP_TYPE_ENDPOINT
:
371 case PCIM_EXP_TYPE_LEGACY_ENDPOINT
:
372 printf("legacy endpoint");
374 case PCIM_EXP_TYPE_ROOT_PORT
:
377 case PCIM_EXP_TYPE_UPSTREAM_PORT
:
378 printf("upstream port");
380 case PCIM_EXP_TYPE_DOWNSTREAM_PORT
:
381 printf("downstream port");
383 case PCIM_EXP_TYPE_PCI_BRIDGE
:
384 printf("PCI bridge");
387 printf("type %d", (flags
& PCIM_EXP_FLAGS_TYPE
) >> 8);
390 if (flags
& PCIM_EXP_FLAGS_IRQ
)
391 printf(" IRQ %d", (flags
& PCIM_EXP_FLAGS_IRQ
) >> 17);
395 cap_msix(int fd
, struct pci_conf
*p
, uint8_t ptr
)
399 int msgnum
, table_bar
, pba_bar
;
401 ctrl
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_CTRL
, 2);
402 msgnum
= (ctrl
& PCIM_MSIXCTRL_TABLE_SIZE
) + 1;
403 val
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_TABLE
, 4);
404 table_bar
= PCIR_BAR(val
& PCIM_MSIX_BIR_MASK
);
405 val
= read_config(fd
, &p
->pc_sel
, ptr
+ PCIR_MSIX_PBA
, 4);
406 pba_bar
= PCIR_BAR(val
& PCIM_MSIX_BIR_MASK
);
407 printf("MSI-X supports %d message%s ", msgnum
,
408 (msgnum
== 1) ? "" : "s");
409 if (table_bar
== pba_bar
)
410 printf("in map 0x%x", table_bar
);
412 printf("in maps 0x%x and 0x%x", table_bar
, pba_bar
);
413 if (ctrl
& PCIM_MSIXCTRL_MSIX_ENABLE
)
418 list_caps(int fd
, struct pci_conf
*p
)
423 /* Are capabilities present for this device? */
424 cmd
= read_config(fd
, &p
->pc_sel
, PCIR_STATUS
, 2);
425 if (!(cmd
& PCIM_STATUS_CAPPRESENT
))
428 switch (p
->pc_hdr
& PCIM_HDRTYPE
) {
434 ptr
= PCIR_CAP_PTR_2
;
437 errx(1, "list_caps: bad header type");
440 /* Walk the capability list. */
441 ptr
= read_config(fd
, &p
->pc_sel
, ptr
, 1);
442 while (ptr
!= 0 && ptr
!= 0xff) {
443 cap
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_ID
, 1);
444 printf(" cap %02x[%02x] = ", cap
, ptr
);
447 cap_power(fd
, p
, ptr
);
459 cap_pcix(fd
, p
, ptr
);
465 cap_vendor(fd
, p
, ptr
);
468 cap_debug(fd
, p
, ptr
);
471 cap_subvendor(fd
, p
, ptr
);
474 cap_express(fd
, p
, ptr
);
477 cap_msix(fd
, p
, ptr
);
484 ptr
= read_config(fd
, &p
->pc_sel
, ptr
+ PCICAP_NEXTPTR
, 1);