sys/powerpc/fpu/fpu_arith.h

   1 /*      $NetBSD: fpu_arith.h,v 1.4 2005/12/24 20:07:28 perry Exp $ */
   2 /* $FreeBSD$ */
   3
   4 /*
   5  * Copyright (c) 1992, 1993
   6  *      The Regents of the University of California.  All rights reserved.
   7  *
   8  * This software was developed by the Computer Systems Engineering group
   9  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  10  * contributed to Berkeley.
  11  *
  12  * All advertising materials mentioning features or use of this software
  13  * must display the following acknowledgement:
  14  *      This product includes software developed by the University of
  15  *      California, Lawrence Berkeley Laboratory.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions
  19  * are met:
  20  * 1. Redistributions of source code must retain the above copyright
  21  *    notice, this list of conditions and the following disclaimer.
  22  * 2. Redistributions in binary form must reproduce the above copyright
  23  *    notice, this list of conditions and the following disclaimer in the
  24  *    documentation and/or other materials provided with the distribution.
  25  * 3. Neither the name of the University nor the names of its contributors
  26  *    may be used to endorse or promote products derived from this software
  27  *    without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  30  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  31  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  32  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  33  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  37  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  38  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  39  * SUCH DAMAGE.
  40  *
  41  *      @(#)fpu_arith.h 8.1 (Berkeley) 6/11/93
  42  */
  43
  44 /*
  45  * Extended-precision arithmetic.
  46  *
  47  * We hold the notion of a `carry register', which may or may not be a
  48  * machine carry bit or register.  On the SPARC, it is just the machine's
  49  * carry bit.
  50  *
  51  * In the worst case, you can compute the carry from x+y as
  52  *      (unsigned)(x + y) < (unsigned)x
  53  * and from x+y+c as
  54  *      ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0)
  55  * for example.
  56  */
  57
  58
  59 #ifndef FPE_USE_ASM
  60
  61 /* set up for extended-precision arithemtic */
  62 #define FPU_DECL_CARRY quad_t fpu_carry, fpu_tmp;
  63
  64 /*
  65  * We have three kinds of add:
  66  *      add with carry:                                   r = x + y + c
  67  *      add (ignoring current carry) and set carry:     c'r = x + y + 0
  68  *      add with carry and set carry:                   c'r = x + y + c
  69  * The macros use `C' for `use carry' and `S' for `set carry'.
  70  * Note that the state of the carry is undefined after ADDC and SUBC,
  71  * so if all you have for these is `add with carry and set carry',
  72  * that is OK.
  73  *
  74  * The same goes for subtract, except that we compute x - y - c.
  75  *
  76  * Finally, we have a way to get the carry into a `regular' variable,
  77  * or set it from a value.  SET_CARRY turns 0 into no-carry, nonzero
  78  * into carry; GET_CARRY sets its argument to 0 or 1.
  79  */
  80 #define FPU_ADDC(r, x, y) \
  81         (r) = (x) + (y) + (!!fpu_carry)
  82 #define FPU_ADDS(r, x, y) \
  83         { \
  84                 fpu_tmp = (quad_t)(x) + (quad_t)(y); \
  85                 (r) = (u_int)fpu_tmp; \
  86                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
  87         }
  88 #define FPU_ADDCS(r, x, y) \
  89         { \
  90                 fpu_tmp = (quad_t)(x) + (quad_t)(y) + (!!fpu_carry); \
  91                 (r) = (u_int)fpu_tmp; \
  92                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
  93         }
  94 #define FPU_SUBC(r, x, y) \
  95         (r) = (x) - (y) - (!!fpu_carry)
  96 #define FPU_SUBS(r, x, y) \
  97         { \
  98                 fpu_tmp = (quad_t)(x) - (quad_t)(y); \
  99                 (r) = (u_int)fpu_tmp; \
 100                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
 101         }
 102 #define FPU_SUBCS(r, x, y) \
 103         { \
 104                 fpu_tmp = (quad_t)(x) - (quad_t)(y) - (!!fpu_carry); \
 105                 (r) = (u_int)fpu_tmp; \
 106                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
 107         }
 108
 109 #define FPU_GET_CARRY(r) (r) = (!!fpu_carry)
 110 #define FPU_SET_CARRY(v) fpu_carry = ((v) != 0)
 111
 112 #else
 113 /* set up for extended-precision arithemtic */
 114 #define FPU_DECL_CARRY
 115
 116 /*
 117  * We have three kinds of add:
 118  *      add with carry:                                   r = x + y + c
 119  *      add (ignoring current carry) and set carry:     c'r = x + y + 0
 120  *      add with carry and set carry:                   c'r = x + y + c
 121  * The macros use `C' for `use carry' and `S' for `set carry'.
 122  * Note that the state of the carry is undefined after ADDC and SUBC,
 123  * so if all you have for these is `add with carry and set carry',
 124  * that is OK.
 125  *
 126  * The same goes for subtract, except that we compute x - y - c.
 127  *
 128  * Finally, we have a way to get the carry into a `regular' variable,
 129  * or set it from a value.  SET_CARRY turns 0 into no-carry, nonzero
 130  * into carry; GET_CARRY sets its argument to 0 or 1.
 131  */
 132 #define FPU_ADDC(r, x, y) \
 133         __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 134 #define FPU_ADDS(r, x, y) \
 135         __asm volatile("addc %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 136 #define FPU_ADDCS(r, x, y) \
 137         __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 138 #define FPU_SUBC(r, x, y) \
 139         __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 140 #define FPU_SUBS(r, x, y) \
 141         __asm volatile("subfc %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 142 #define FPU_SUBCS(r, x, y) \
 143         __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 144
 145 #define FPU_GET_CARRY(r) __asm volatile("li %0,0; addie %0,%0,0" : "=r"(r))
 146 /* This one needs to destroy a temp register. */
 147 #define FPU_SET_CARRY(v) do { int __tmp;                                \
 148                 __asm volatile("addic %0,%0,-1" : "r"(__tmp) : "r"(v)); \
 149         } while (0)
 150
 151 #define FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */
 152 #endif