stand/common/isapnp.h

   1 /*
   2  * Copyright (c) 1996, Sujal M. Patel
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Sujal M. Patel
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #ifndef _I386_ISA_PNP_H_
  34 #define _I386_ISA_PNP_H_
  35
  36 /* Maximum Number of PnP Devices.  8 should be plenty */
  37 #define MAX_PNP_CARDS 8
  38 /*
  39  * the following is the maximum number of PnP Logical devices that
  40  * userconfig can handle.
  41  */
  42 #define MAX_PNP_LDN     20
  43
  44 /* Static ports to access PnP state machine */
  45 #ifndef _KERNEL
  46 #define _PNP_ADDRESS            0x279
  47 #define _PNP_WRITE_DATA         0xa79
  48 #endif
  49
  50 /* PnP Registers.  Write to ADDRESS and then use WRITE/READ_DATA */
  51 #define SET_RD_DATA             0x00
  52         /***
  53         Writing to this location modifies the address of the port used for
  54         reading from the Plug and Play ISA cards.   Bits[7:0] become I/O
  55         read port address bits[9:2].  Reads from this register are ignored.
  56         ***/
  57
  58 #define SERIAL_ISOLATION        0x01
  59         /***
  60         A read to this register causes a Plug and Play cards in the Isolation
  61         state to compare one bit of the boards ID.
  62         This register is read only.
  63         ***/
  64
  65 #define CONFIG_CONTROL          0x02
  66         /***
  67         Bit[2]  Reset CSN to 0
  68         Bit[1]  Return to the Wait for Key state
  69         Bit[0]  Reset all logical devices and restore configuration
  70                 registers to their power-up values.
  71
  72         A write to bit[0] of this register performs a reset function on
  73         all logical devices.  This resets the contents of configuration
  74         registers to  their default state.  All card's logical devices
  75         enter their default state and the CSN is preserved.
  76
  77         A write to bit[1] of this register causes all cards to enter the
  78         Wait for Key state but all CSNs are preserved and logical devices
  79         are not affected.
  80
  81         A write to bit[2] of this register causes all cards to reset their
  82         CSN to zero .
  83
  84         This register is write-only.  The values are not sticky, that is,
  85         hardware will automatically clear them and there is no need for
  86         software to clear the bits.
  87         ***/
  88
  89 #define WAKE                    0x03
  90         /***
  91         A write to this port will cause all cards that have a CSN that
  92         matches the write data[7:0] to go from the Sleep state to the either
  93         the Isolation state if the write data for this command is zero or
  94         the Config state if the write data is not zero.  Additionally, the
  95         pointer to the byte-serial device is reset.  This register is
  96         writeonly.
  97         ***/
  98
  99 #define RESOURCE_DATA           0x04
 100         /***
 101         A read from this address reads the next byte of resource information.
 102         The Status register must be polled until bit[0] is set before this
 103         register may be read.  This register is read only.
 104         ***/
 105
 106 #define STATUS                  0x05
 107         /***
 108         Bit[0] when set indicates it is okay to read the next data byte
 109         from the Resource Data register.  This register is readonly.
 110         ***/
 111
 112 #define SET_CSN                 0x06
 113         /***
 114         A write to this port sets a card's CSN.  The CSN is a value uniquely
 115         assigned to each ISA card after the serial identification process
 116         so that each card may be individually selected during a Wake[CSN]
 117         command. This register is read/write.
 118         ***/
 119
 120 #define SET_LDN                 0x07
 121         /***
 122         Selects the current logical device.  All reads and writes of memory,
 123         I/O, interrupt and DMA configuration information access the registers
 124         of the logical device written here.  In addition, the I/O Range
 125         Check and Activate  commands operate only on the selected logical
 126         device.  This register is read/write. If a card has only 1 logical
 127         device, this location should be a read-only value of 0x00.
 128         ***/
 129
 130 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
 131 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
 132
 133 #define ACTIVATE                0x30
 134         /***
 135         For each logical device there is one activate register that controls
 136         whether or not the logical device is active on the ISA bus.  Bit[0],
 137         if set, activates the logical device.  Bits[7:1] are reserved and
 138         must return 0 on reads.  This is a read/write register. Before a
 139         logical device is activated, I/O range check must be disabled.
 140         ***/
 141
 142 #define IO_RANGE_CHECK          0x31
 143         /***
 144         This register is used to perform a conflict check on the I/O port
 145         range programmed for use by a logical device.
 146
 147         Bit[7:2]  Reserved and must return 0 on reads
 148         Bit[1]    Enable I/O Range check, if set then I/O Range Check
 149         is enabled. I/O range check is only valid when the logical
 150         device is inactive.
 151
 152         Bit[0], if set, forces the logical device to respond to I/O reads
 153         of the logical device's assigned I/O range with a 0x55 when I/O
 154         range check is in operation.  If clear, the logical device drives
 155         0xAA.  This register is read/write.
 156         ***/
 157
 158 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
 159 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
 160
 161 #define MEM_CONFIG              0x40
 162         /***
 163         Four memory resource registers per range, four ranges.
 164         Fill with 0 if no ranges are enabled.
 165
 166         Offset 0:       RW Memory base address bits[23:16]
 167         Offset 1:       RW Memory base address bits[15:8]
 168         Offset 2:       Memory control
 169             Bit[1] specifies 8/16-bit control.  This bit is set to indicate
 170             16-bit memory, and cleared to indicate 8-bit memory.
 171             Bit[0], if cleared, indicates the next field can be used as a range
 172             length for decode (implies range length and base alignment of memory
 173             descriptor are equal).
 174             Bit[0], if set, indicates the next field is the upper limit for
 175             the address. -  - Bit[0] is read-only.
 176         Offset 3:       RW upper limit or range len, bits[23:16]
 177         Offset 4:       RW upper limit or range len, bits[15:8]
 178         Offset 5-Offset 7: filler, unused.
 179         ***/
 180
 181 #define IO_CONFIG_BASE          0x60
 182         /***
 183         Eight ranges, two bytes per range.
 184         Offset 0:               I/O port base address bits[15:8]
 185         Offset 1:               I/O port base address bits[7:0]
 186         ***/
 187
 188 #define IRQ_CONFIG              0x70
 189         /***
 190         Two entries, two bytes per entry.
 191         Offset 0:       RW interrupt level (1..15, 0=unused).
 192         Offset 1:       Bit[1]: level(1:hi, 0:low),
 193                         Bit[0]: type (1:level, 0:edge)
 194                 byte 1 can be readonly if 1 type of int is used.
 195         ***/
 196
 197 #define DRQ_CONFIG              0x74
 198         /***
 199         Two entries, one byte per entry. Bits[2:0] select
 200         which DMA channel is in use for DMA 0.  Zero selects DMA channel
 201         0, seven selects DMA channel 7. DMA channel 4, the cascade channel
 202         is used to indicate no DMA channel is active.
 203         ***/
 204
 205 /*** 32-bit memory accesses are at 0x76 ***/
 206
 207 /* Macros to parse Resource IDs */
 208 #define PNP_RES_TYPE(a)         (a >> 7)
 209 #define PNP_SRES_NUM(a)         (a >> 3)
 210 #define PNP_SRES_LEN(a)         (a & 0x07)
 211 #define PNP_LRES_NUM(a)         (a & 0x7f)
 212
 213 /* Small Resource Item names */
 214 #define PNP_VERSION             0x1
 215 #define LOG_DEVICE_ID           0x2
 216 #define COMP_DEVICE_ID          0x3
 217 #define IRQ_FORMAT              0x4
 218 #define DMA_FORMAT              0x5
 219 #define START_DEPEND_FUNC       0x6
 220 #define END_DEPEND_FUNC         0x7
 221 #define IO_PORT_DESC            0x8
 222 #define FIXED_IO_PORT_DESC      0x9
 223 #define SM_RES_RESERVED         0xa-0xd
 224 #define SM_VENDOR_DEFINED       0xe
 225 #define END_TAG                 0xf
 226
 227 /* Large Resource Item names */
 228 #define MEMORY_RANGE_DESC       0x1
 229 #define ID_STRING_ANSI          0x2
 230 #define ID_STRING_UNICODE       0x3
 231 #define LG_VENDOR_DEFINED       0x4
 232 #define _32BIT_MEM_RANGE_DESC   0x5
 233 #define _32BIT_FIXED_LOC_DESC   0x6
 234 #define LG_RES_RESERVED         0x7-0x7f
 235
 236 /*
 237  * pnp_cinfo contains Configuration Information. They are used
 238  * to communicate to the device driver the actual configuration
 239  * of the device, and also by the userconfig menu to let the
 240  * operating system override any configuration set by the bios.
 241  *
 242  */
 243 struct pnp_cinfo {
 244         u_int vendor_id;        /* board id */
 245         u_int serial;           /* Board's Serial Number */
 246         u_long flags;           /* OS-reserved flags */
 247         u_char csn;             /* assigned Card Select Number */
 248         u_char ldn;             /* Logical Device Number */
 249         u_char enable;          /* pnp enable */
 250         u_char override;        /* override bios parms (in userconfig) */
 251         u_char irq[2];          /* IRQ Number */
 252         u_char irq_type[2];     /* IRQ Type */
 253         u_char drq[2];
 254         u_short port[8];        /* The Base Address of the Port */
 255         struct {
 256                 u_long base;    /* Memory Base Address */
 257                 int control;    /* Memory Control Register */
 258                 u_long range;   /* Memory Range *OR* Upper Limit */
 259         } mem[4];
 260 };
 261
 262 #ifdef _KERNEL
 263
 264 struct pnp_device {
 265     char *pd_name;
 266     char * (*pd_probe ) (u_long csn, u_long vendor_id);
 267     void (*pd_attach ) (u_long csn, u_long vend_id, char * name,
 268         struct isa_device *dev);
 269     u_long      *pd_count;
 270     u_int *imask ;
 271 };
 272
 273 struct _pnp_id {
 274     u_long vendor_id;
 275     u_long serial;
 276     u_char checksum;
 277 } ;
 278
 279 struct pnp_dlist_node {
 280     struct pnp_device *pnp;
 281     struct isa_device dev;
 282     struct pnp_dlist_node *next;
 283 };
 284
 285 typedef struct _pnp_id pnp_id;
 286 extern struct pnp_dlist_node *pnp_device_list;
 287 extern pnp_id pnp_devices[MAX_PNP_CARDS];
 288 extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN];
 289 extern int pnp_overrides_valid;
 290
 291 /*
 292  * these two functions are for use in drivers
 293  */
 294 int read_pnp_parms(struct pnp_cinfo *d, int ldn);
 295 int write_pnp_parms(struct pnp_cinfo *d, int ldn);
 296 int enable_pnp_card(void);
 297
 298 /*
 299  * used by autoconfigure to actually probe and attach drivers
 300  */
 301 void pnp_configure(void);
 302
 303 #endif /* _KERNEL */
 304
 305 #endif /* !_I386_ISA_PNP_H_ */