sys/arm/ti/ti_sdmareg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2011
   5  *      Ben Gray <ben.r.gray@gmail.com>.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29 #ifndef __TI_SDMAREG_H__
  30 #define __TI_SDMAREG_H__
  31
  32 /**
  33  * The number of DMA channels possible on the controller.
  34  */
  35 #define NUM_DMA_CHANNELS        32
  36 #define NUM_DMA_IRQS            4
  37
  38 /**
  39  * Register offsets
  40  */
  41 #define DMA4_REVISION                            0x0000
  42 #define DMA4_IRQSTATUS_L(j)                     (0x0008 + ((j) * 0x4))
  43 #define DMA4_IRQENABLE_L(j)                     (0x0018 + ((j) * 0x4))
  44 #define DMA4_SYSSTATUS                           0x0028
  45 #define DMA4_OCP_SYSCONFIG                       0x002C
  46 #define DMA4_CAPS_0                              0x0064
  47 #define DMA4_CAPS_2                              0x006C
  48 #define DMA4_CAPS_3                              0x0070
  49 #define DMA4_CAPS_4                              0x0074
  50 #define DMA4_GCR                                 0x0078
  51 #define DMA4_CCR(i)                             (0x0080 + ((i) * 0x60))
  52 #define DMA4_CLNK_CTRL(i)                       (0x0084 + ((i) * 0x60))
  53 #define DMA4_CICR(i)                            (0x0088 + ((i) * 0x60))
  54 #define DMA4_CSR(i)                             (0x008C + ((i) * 0x60))
  55 #define DMA4_CSDP(i)                            (0x0090 + ((i) * 0x60))
  56 #define DMA4_CEN(i)                             (0x0094 + ((i) * 0x60))
  57 #define DMA4_CFN(i)                             (0x0098 + ((i) * 0x60))
  58 #define DMA4_CSSA(i)                            (0x009C + ((i) * 0x60))
  59 #define DMA4_CDSA(i)                            (0x00A0 + ((i) * 0x60))
  60 #define DMA4_CSE(i)                             (0x00A4 + ((i) * 0x60))
  61 #define DMA4_CSF(i)                             (0x00A8 + ((i) * 0x60))
  62 #define DMA4_CDE(i)                             (0x00AC + ((i) * 0x60))
  63 #define DMA4_CDF(i)                             (0x00B0 + ((i) * 0x60))
  64 #define DMA4_CSAC(i)                            (0x00B4 + ((i) * 0x60))
  65 #define DMA4_CDAC(i)                            (0x00B8 + ((i) * 0x60))
  66 #define DMA4_CCEN(i)                            (0x00BC + ((i) * 0x60))
  67 #define DMA4_CCFN(i)                            (0x00C0 + ((i) * 0x60))
  68 #define DMA4_COLOR(i)                           (0x00C4 + ((i) * 0x60))
  69
  70 /* The following register are only defined on OMAP44xx (and newer?) */
  71 #define DMA4_CDP(i)                             (0x00D0 + ((i) * 0x60))
  72 #define DMA4_CNDP(i)                            (0x00D4 + ((i) * 0x60))
  73 #define DMA4_CCDN(i)                            (0x00D8 + ((i) * 0x60))
  74
  75 /**
  76  * Various register field settings
  77  */
  78 #define DMA4_CSDP_DATA_TYPE(x)                  (((x) & 0x3) << 0)
  79 #define DMA4_CSDP_SRC_BURST_MODE(x)             (((x) & 0x3) << 7)
  80 #define DMA4_CSDP_DST_BURST_MODE(x)             (((x) & 0x3) << 14)
  81 #define DMA4_CSDP_SRC_ENDIANISM(x)              (((x) & 0x1) << 21)
  82 #define DMA4_CSDP_DST_ENDIANISM(x)              (((x) & 0x1) << 19)
  83 #define DMA4_CSDP_WRITE_MODE(x)                 (((x) & 0x3) << 16)
  84 #define DMA4_CSDP_SRC_PACKED(x)                 (((x) & 0x1) << 6)
  85 #define DMA4_CSDP_DST_PACKED(x)                 (((x) & 0x1) << 13)
  86
  87 #define DMA4_CCR_DST_ADDRESS_MODE(x)            (((x) & 0x3) << 14)
  88 #define DMA4_CCR_SRC_ADDRESS_MODE(x)            (((x) & 0x3) << 12)
  89 #define DMA4_CCR_READ_PRIORITY(x)               (((x) & 0x1) << 6)
  90 #define DMA4_CCR_WRITE_PRIORITY(x)              (((x) & 0x1) << 26)
  91 #define DMA4_CCR_SYNC_TRIGGER(x)                ((((x) & 0x60) << 14) \
  92                                                  | ((x) & 0x1f))
  93 #define DMA4_CCR_FRAME_SYNC(x)                  (((x) & 0x1) << 5)
  94 #define DMA4_CCR_BLOCK_SYNC(x)                  (((x) & 0x1) << 18)
  95 #define DMA4_CCR_SEL_SRC_DST_SYNC(x)            (((x) & 0x1) << 24)
  96
  97 #define DMA4_CCR_PACKET_TRANS                   (DMA4_CCR_FRAME_SYNC(1) | \
  98                                                  DMA4_CCR_BLOCK_SYNC(1) )
  99
 100 #define DMA4_CSR_DROP                           (1UL << 1)
 101 #define DMA4_CSR_HALF                           (1UL << 2)
 102 #define DMA4_CSR_FRAME                          (1UL << 3)
 103 #define DMA4_CSR_LAST                           (1UL << 4)
 104 #define DMA4_CSR_BLOCK                          (1UL << 5)
 105 #define DMA4_CSR_SYNC                           (1UL << 6)
 106 #define DMA4_CSR_PKT                            (1UL << 7)
 107 #define DMA4_CSR_TRANS_ERR                      (1UL << 8)
 108 #define DMA4_CSR_SECURE_ERR                     (1UL << 9)
 109 #define DMA4_CSR_SUPERVISOR_ERR                 (1UL << 10)
 110 #define DMA4_CSR_MISALIGNED_ADRS_ERR            (1UL << 11)
 111 #define DMA4_CSR_DRAIN_END                      (1UL << 12)
 112 #define DMA4_CSR_CLEAR_MASK                     (0xffe)
 113
 114 #define DMA4_CICR_DROP_IE                       (1UL << 1)
 115 #define DMA4_CICR_HALF_IE                       (1UL << 2)
 116 #define DMA4_CICR_FRAME_IE                      (1UL << 3)
 117 #define DMA4_CICR_LAST_IE                       (1UL << 4)
 118 #define DMA4_CICR_BLOCK_IE                      (1UL << 5)
 119 #define DMA4_CICR_PKT_IE                        (1UL << 7)
 120 #define DMA4_CICR_TRANS_ERR_IE                  (1UL << 8)
 121 #define DMA4_CICR_SECURE_ERR_IE                 (1UL << 9)
 122 #define DMA4_CICR_SUPERVISOR_ERR_IE             (1UL << 10)
 123 #define DMA4_CICR_MISALIGNED_ADRS_ERR_IE        (1UL << 11)
 124 #define DMA4_CICR_DRAIN_IE                      (1UL << 12)
 125
 126 /**
 127  *      The following H/W revision values were found be experimentation, TI don't
 128  *      publish the revision numbers.  The TRM says "TI internal Data".
 129  */
 130 #define DMA4_OMAP3_REV                          0x00000040
 131 #define DMA4_OMAP4_REV                          0x00010900
 132
 133 #endif  /* __TI_SDMAREG_H__ */