sys/arm64/include/pte.h

   1 /*-
   2  * Copyright (c) 2014 Andrew Turner
   3  * Copyright (c) 2014-2015 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * This software was developed by Andrew Turner under
   7  * sponsorship from the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 #ifdef __arm__
  32 #include <arm/pte.h>
  33 #else /* !__arm__ */
  34
  35 #ifndef _MACHINE_PTE_H_
  36 #define _MACHINE_PTE_H_
  37
  38 #ifndef LOCORE
  39 typedef uint64_t        pd_entry_t;             /* page directory entry */
  40 typedef uint64_t        pt_entry_t;             /* page table entry */
  41 #endif
  42
  43 /* Table attributes */
  44 #define TATTR_MASK              UINT64_C(0xfff8000000000000)
  45 #define TATTR_AP_TABLE_MASK     (3UL << 61)
  46 #define TATTR_AP_TABLE_RO       (2UL << 61)
  47 #define TATTR_AP_TABLE_NO_EL0   (1UL << 61)
  48 #define TATTR_UXN_TABLE         (1UL << 60)
  49 #define TATTR_PXN_TABLE         (1UL << 59)
  50 /* Bits 58:51 are ignored */
  51
  52 /* Block and Page attributes */
  53 #define ATTR_MASK_H             UINT64_C(0xfffc000000000000)
  54 #define ATTR_MASK_L             UINT64_C(0x0000000000000fff)
  55 #define ATTR_MASK               (ATTR_MASK_H | ATTR_MASK_L)
  56
  57 /* Bits 58:55 are reserved for software */
  58 #define ATTR_SW_UNUSED1         (1UL << 58)
  59 #define ATTR_SW_NO_PROMOTE      (1UL << 57)
  60 #define ATTR_SW_MANAGED         (1UL << 56)
  61 #define ATTR_SW_WIRED           (1UL << 55)
  62
  63 #define ATTR_S1_UXN             (1UL << 54)
  64 #define ATTR_S1_PXN             (1UL << 53)
  65 #define ATTR_S1_XN              (ATTR_S1_PXN | ATTR_S1_UXN)
  66
  67 #define ATTR_S2_XN(x)           ((x) << 53)
  68 #define  ATTR_S2_XN_MASK        ATTR_S2_XN(3UL)
  69 #define  ATTR_S2_XN_NONE        0UL     /* Allow execution at EL0 & EL1 */
  70 #define  ATTR_S2_XN_EL1         1UL     /* Allow execution at EL0 */
  71 #define  ATTR_S2_XN_ALL         2UL     /* No execution */
  72 #define  ATTR_S2_XN_EL0         3UL     /* Allow execution at EL1 */
  73
  74 #define ATTR_CONTIGUOUS         (1UL << 52)
  75 #define ATTR_DBM                (1UL << 51)
  76 #define ATTR_S1_GP              (1UL << 50)
  77
  78 /*
  79  * Largest possible output address field for a level 3 page. Block
  80  * entries will use fewer low address bits, but these are res0 so
  81  * should be safe to include.
  82  *
  83  * This is also safe to use for the next-level table address for
  84  * table entries as they encode a physical address in the same way.
  85  */
  86 #if PAGE_SIZE == PAGE_SIZE_4K
  87 #define ATTR_ADDR               UINT64_C(0x0003fffffffff000)
  88 #elif PAGE_SIZE == PAGE_SIZE_16K
  89 #define ATTR_ADDR               UINT64_C(0x0003ffffffffc000)
  90 #else
  91 #error Unsupported page size
  92 #endif
  93
  94 #define ATTR_S1_nG              (1 << 11)
  95 #define ATTR_AF                 (1 << 10)
  96 /* When TCR_EL1.DS == 0 */
  97 #define ATTR_SH(x)              ((x) << 8)
  98 #define  ATTR_SH_MASK           ATTR_SH(3)
  99 #define  ATTR_SH_NS             0               /* Non-shareable */
 100 #define  ATTR_SH_OS             2               /* Outer-shareable */
 101 #define  ATTR_SH_IS             3               /* Inner-shareable */
 102 /* When TCR_EL1.DS == 1 */
 103 #define ATTR_OA_51_50_SHIFT     8
 104 #define ATTR_OA_51_50_MASK      (3 << ATTR_OA_51_50_SHIFT)
 105 #define ATTR_OA_51_50_DELTA     (50 - 8)        /* Delta from address to pte */
 106
 107 #define ATTR_S1_AP_RW_BIT       (1 << 7)
 108 #define ATTR_S1_AP(x)           ((x) << 6)
 109 #define  ATTR_S1_AP_MASK        ATTR_S1_AP(3)
 110 #define  ATTR_S1_AP_RW          (0 << 1)
 111 #define  ATTR_S1_AP_RO          (1 << 1)
 112 #define  ATTR_S1_AP_USER        (1 << 0)
 113 #define ATTR_S1_NS              (1 << 5)
 114 #define ATTR_S1_IDX(x)          ((x) << 2)
 115 #define ATTR_S1_IDX_MASK        (7 << 2)
 116
 117 #define ATTR_S2_S2AP(x)         ((x) << 6)
 118 #define  ATTR_S2_S2AP_MASK      3
 119 #define  ATTR_S2_S2AP_READ      1
 120 #define  ATTR_S2_S2AP_WRITE     2
 121
 122 #define ATTR_S2_MEMATTR(x)              ((x) << 2)
 123 #define  ATTR_S2_MEMATTR_MASK           ATTR_S2_MEMATTR(0xf)
 124 #define  ATTR_S2_MEMATTR_DEVICE_nGnRnE  0x0
 125 #define  ATTR_S2_MEMATTR_NC             0xf
 126 #define  ATTR_S2_MEMATTR_WT             0xa
 127 #define  ATTR_S2_MEMATTR_WB             0xf
 128
 129 #define ATTR_DESCR_MASK         3
 130 #define ATTR_DESCR_VALID        1
 131 #define ATTR_DESCR_TYPE_MASK    2
 132 #define ATTR_DESCR_TYPE_TABLE   2
 133 #define ATTR_DESCR_TYPE_PAGE    2
 134 #define ATTR_DESCR_TYPE_BLOCK   0
 135
 136 /*
 137  * Superpage promotion requires that the bits specified by the following
 138  * mask all be identical in the constituent PTEs.
 139  */
 140 #define ATTR_PROMOTE    (ATTR_MASK & ~(ATTR_CONTIGUOUS | ATTR_AF))
 141
 142 /* Read the output address or next-level table address from a PTE */
 143 #define PTE_TO_PHYS(x)          ({                                      \
 144         pt_entry_t _pte = (x);                                          \
 145         vm_paddr_t _pa;                                                 \
 146         _pa = _pte & ATTR_ADDR;                                         \
 147         if (pmap_lpa_enabled)                                           \
 148                 _pa |= (_pte & ATTR_OA_51_50_MASK) << ATTR_OA_51_50_DELTA; \
 149         _pa;                                                            \
 150 })
 151
 152 /*
 153  * Convert a physical address to an output address or next-level
 154  * table address in a PTE
 155  */
 156 #define PHYS_TO_PTE(x)          ({                                      \
 157         vm_paddr_t _pa = (x);                                           \
 158         pt_entry_t _pte;                                                \
 159         _pte = _pa & ATTR_ADDR;                                         \
 160         if (pmap_lpa_enabled)                                           \
 161                 _pte |= (_pa >> ATTR_OA_51_50_DELTA) & ATTR_OA_51_50_MASK; \
 162         _pte;                                                           \
 163 })
 164
 165 #if PAGE_SIZE == PAGE_SIZE_4K
 166 #define L0_SHIFT        39
 167 #define L1_SHIFT        30
 168 #define L2_SHIFT        21
 169 #define L3_SHIFT        12
 170 #elif PAGE_SIZE == PAGE_SIZE_16K
 171 #define L0_SHIFT        47
 172 #define L1_SHIFT        36
 173 #define L2_SHIFT        25
 174 #define L3_SHIFT        14
 175 #else
 176 #error Unsupported page size
 177 #endif
 178
 179 /* Level 0 table, 512GiB/128TiB per entry */
 180 #define L0_SIZE         (UINT64_C(1) << L0_SHIFT)
 181 #define L0_OFFSET       (L0_SIZE - 1ul)
 182 #define L0_INVAL        0x0 /* An invalid address */
 183         /* 0x1 Level 0 doesn't support block translation */
 184         /* 0x2 also marks an invalid address */
 185 #define L0_TABLE        0x3 /* A next-level table */
 186
 187 /* Level 1 table, 1GiB/64GiB per entry */
 188 #define L1_SIZE         (UINT64_C(1) << L1_SHIFT)
 189 #define L1_OFFSET       (L1_SIZE - 1)
 190 #define L1_INVAL        L0_INVAL
 191 #define L1_BLOCK        0x1
 192 #define L1_TABLE        L0_TABLE
 193
 194 /* Level 2 table, 2MiB/32MiB per entry */
 195 #define L2_SIZE         (UINT64_C(1) << L2_SHIFT)
 196 #define L2_OFFSET       (L2_SIZE - 1)
 197 #define L2_INVAL        L1_INVAL
 198 #define L2_BLOCK        0x1
 199 #define L2_TABLE        L1_TABLE
 200
 201 /* Level 3 table, 4KiB/16KiB per entry */
 202 #define L3_SIZE         (1 << L3_SHIFT)
 203 #define L3_OFFSET       (L3_SIZE - 1)
 204 #define L3_INVAL        0x0
 205         /* 0x1 is reserved */
 206         /* 0x2 also marks an invalid address */
 207 #define L3_PAGE         0x3
 208
 209 /*
 210  * A substantial portion of this is to make sure that we can cope with 4K
 211  * framebuffers in early boot, assuming a common 4K resolution @ 32-bit depth.
 212  */
 213 #define PMAP_MAPDEV_EARLY_SIZE  (L2_SIZE * 20)
 214
 215 #if PAGE_SIZE == PAGE_SIZE_4K
 216 #define L0_ENTRIES_SHIFT 9
 217 #define Ln_ENTRIES_SHIFT 9
 218 #elif PAGE_SIZE == PAGE_SIZE_16K
 219 #define L0_ENTRIES_SHIFT 1
 220 #define Ln_ENTRIES_SHIFT 11
 221 #else
 222 #error Unsupported page size
 223 #endif
 224
 225 #define L0_ENTRIES      (1 << L0_ENTRIES_SHIFT)
 226 #define L0_ADDR_MASK    (L0_ENTRIES - 1)
 227
 228 #define Ln_ENTRIES      (1 << Ln_ENTRIES_SHIFT)
 229 #define Ln_ADDR_MASK    (Ln_ENTRIES - 1)
 230 #define Ln_TABLE_MASK   ((1 << 12) - 1)
 231
 232 /*
 233  * The number of contiguous Level 3 entries (with ATTR_CONTIGUOUS set) that
 234  * can be coalesced into a single TLB entry
 235  */
 236 #if PAGE_SIZE == PAGE_SIZE_4K
 237 #define L2C_ENTRIES     16
 238 #define L3C_ENTRIES     16
 239 #elif PAGE_SIZE == PAGE_SIZE_16K
 240 #define L2C_ENTRIES     32
 241 #define L3C_ENTRIES     128
 242 #else
 243 #error Unsupported page size
 244 #endif
 245
 246 #define L2C_SIZE        (L2C_ENTRIES * L2_SIZE)
 247 #define L2C_OFFSET      (L2C_SIZE - 1)
 248
 249 #define L3C_SIZE        (L3C_ENTRIES * L3_SIZE)
 250 #define L3C_OFFSET      (L3C_SIZE - 1)
 251
 252 #define pmap_l0_index(va)       (((va) >> L0_SHIFT) & L0_ADDR_MASK)
 253 #define pmap_l1_index(va)       (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
 254 #define pmap_l2_index(va)       (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
 255 #define pmap_l3_index(va)       (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
 256
 257 #endif /* !_MACHINE_PTE_H_ */
 258
 259 /* End of pte.h */
 260
 261 #endif /* !__arm__ */