sys/dev/qcom_clk/qcom_clk_branch2.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #ifndef __QCOM_CLK_BRANCH2_H__
  29 #define __QCOM_CLK_BRANCH2_H__
  30
  31 #include "qcom_clk_freqtbl.h"
  32
  33 /* halt is 1 */
  34 #define QCOM_CLK_BRANCH2_BRANCH_HALT            0
  35
  36 /* halt is inverted (ie, 0) */
  37 #define QCOM_CLK_BRANCH2_BRANCH_HALT_INVERTED   1
  38
  39 /* Don't check the bit, just delay */
  40 #define QCOM_CLK_BRANCH2_BRANCH_HALT_DELAY      2
  41
  42 /* Don't check the halt bit at all */
  43 #define QCOM_CLK_BRANCH2_BRANCH_HALT_SKIP       3
  44
  45 /* Flags */
  46 #define QCOM_CLK_BRANCH2_FLAGS_CRITICAL         0x1
  47 #define QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT  0x2
  48
  49 struct qcom_clk_branch2_def {
  50         struct clknode_init_def clkdef;
  51
  52         uint32_t flags;
  53
  54         uint32_t enable_offset; /* enable register*/
  55         uint32_t enable_shift;  /* enable bit shift */
  56
  57         uint32_t hwcg_reg;      /* hw clock gate register */
  58         uint32_t hwcg_bit;
  59         uint32_t halt_reg;      /* halt register */
  60
  61         uint32_t halt_check_type;
  62         bool halt_check_voted;  /* whether to delay when waiting */
  63 };
  64
  65 extern  int qcom_clk_branch2_register(struct clkdom *clkdom,
  66             struct qcom_clk_branch2_def *clkdef);
  67
  68 #endif  /* __QCOM_CLK_BRANCH2_H__ */