sys/dev/vmware/vmxnet3/if_vmxreg.h

   1 /*-
   2  * Copyright (c) 2013 Tsubai Masanari
   3  *
   4  * Permission to use, copy, modify, and distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  * $OpenBSD: src/sys/dev/pci/if_vmxreg.h,v 1.2 2013/06/12 01:07:33 uebayasi Exp $
  17  */
  18
  19 #ifndef _IF_VMXREG_H
  20 #define _IF_VMXREG_H
  21
  22 struct UPT1_TxStats {
  23         uint64_t        TSO_packets;
  24         uint64_t        TSO_bytes;
  25         uint64_t        ucast_packets;
  26         uint64_t        ucast_bytes;
  27         uint64_t        mcast_packets;
  28         uint64_t        mcast_bytes;
  29         uint64_t        bcast_packets;
  30         uint64_t        bcast_bytes;
  31         uint64_t        error;
  32         uint64_t        discard;
  33 } __packed;
  34
  35 struct UPT1_RxStats {
  36         uint64_t        LRO_packets;
  37         uint64_t        LRO_bytes;
  38         uint64_t        ucast_packets;
  39         uint64_t        ucast_bytes;
  40         uint64_t        mcast_packets;
  41         uint64_t        mcast_bytes;
  42         uint64_t        bcast_packets;
  43         uint64_t        bcast_bytes;
  44         uint64_t        nobuffer;
  45         uint64_t        error;
  46 } __packed;
  47
  48 /* Interrupt moderation levels */
  49 #define UPT1_IMOD_NONE          0       /* No moderation */
  50 #define UPT1_IMOD_HIGHEST       7       /* Least interrupts */
  51 #define UPT1_IMOD_ADAPTIVE      8       /* Adaptive interrupt moderation */
  52
  53 /* Hardware features */
  54 #define UPT1_F_CSUM     0x0001          /* Rx checksum verification */
  55 #define UPT1_F_RSS      0x0002          /* Receive side scaling */
  56 #define UPT1_F_VLAN     0x0004          /* VLAN tag stripping */
  57 #define UPT1_F_LRO      0x0008          /* Large receive offloading */
  58
  59 #define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8)     /* Interrupt mask */
  60 #define VMXNET3_BAR0_TXH(q)     (0x600 + (q) * 8)       /* Tx head */
  61 #define VMXNET3_BAR0_RXH1(q)    (0x800 + (q) * 8)       /* Ring1 Rx head */
  62 #define VMXNET3_BAR0_RXH2(q)    (0xA00 + (q) * 8)       /* Ring2 Rx head */
  63 #define VMXNET3_BAR1_VRRS       0x000   /* VMXNET3 revision report selection */
  64 #define VMXNET3_BAR1_UVRS       0x008   /* UPT version report selection */
  65 #define VMXNET3_BAR1_DSL        0x010   /* Driver shared address low */
  66 #define VMXNET3_BAR1_DSH        0x018   /* Driver shared address high */
  67 #define VMXNET3_BAR1_CMD        0x020   /* Command */
  68 #define VMXNET3_BAR1_MACL       0x028   /* MAC address low */
  69 #define VMXNET3_BAR1_MACH       0x030   /* MAC address high */
  70 #define VMXNET3_BAR1_INTR       0x038   /* Interrupt status */
  71 #define VMXNET3_BAR1_EVENT      0x040   /* Event status */
  72
  73 #define VMXNET3_CMD_ENABLE      0xCAFE0000      /* Enable VMXNET3 */
  74 #define VMXNET3_CMD_DISABLE     0xCAFE0001      /* Disable VMXNET3 */
  75 #define VMXNET3_CMD_RESET       0xCAFE0002      /* Reset device */
  76 #define VMXNET3_CMD_SET_RXMODE  0xCAFE0003      /* Set interface flags */
  77 #define VMXNET3_CMD_SET_FILTER  0xCAFE0004      /* Set address filter */
  78 #define VMXNET3_CMD_VLAN_FILTER 0xCAFE0005      /* Set VLAN filter */
  79 #define VMXNET3_CMD_GET_STATUS  0xF00D0000      /* Get queue errors */
  80 #define VMXNET3_CMD_GET_STATS   0xF00D0001      /* Get queue statistics */
  81 #define VMXNET3_CMD_GET_LINK    0xF00D0002      /* Get link status */
  82 #define VMXNET3_CMD_GET_MACL    0xF00D0003      /* Get MAC address low */
  83 #define VMXNET3_CMD_GET_MACH    0xF00D0004      /* Get MAC address high */
  84 #define VMXNET3_CMD_GET_INTRCFG 0xF00D0008      /* Get interrupt config */
  85
  86 #define VMXNET3_DMADESC_ALIGN   128
  87 #define VMXNET3_INIT_GEN        1
  88
  89 struct vmxnet3_txdesc {
  90         uint64_t        addr;
  91
  92         uint32_t        len:14;
  93         uint32_t        gen:1;          /* Generation */
  94         uint32_t        pad1:1;
  95         uint32_t        dtype:1;        /* Descriptor type */
  96         uint32_t        pad2:1;
  97         uint32_t        offload_pos:14; /* Offloading position */
  98
  99         uint32_t        hlen:10;        /* Header len */
 100         uint32_t        offload_mode:2; /* Offloading mode */
 101         uint32_t        eop:1;          /* End of packet */
 102         uint32_t        compreq:1;      /* Completion request */
 103         uint32_t        pad3:1;
 104         uint32_t        vtag_mode:1;    /* VLAN tag insertion mode */
 105         uint32_t        vtag:16;        /* VLAN tag */
 106 } __packed;
 107
 108 /* Offloading modes */
 109 #define VMXNET3_OM_NONE 0
 110 #define VMXNET3_OM_CSUM 2
 111 #define VMXNET3_OM_TSO  3
 112
 113 struct vmxnet3_txcompdesc {
 114         uint32_t        eop_idx:12;     /* EOP index in Tx ring */
 115         uint32_t        pad1:20;
 116
 117         uint32_t        pad2:32;
 118         uint32_t        pad3:32;
 119
 120         uint32_t        rsvd:24;
 121         uint32_t        type:7;
 122         uint32_t        gen:1;
 123 } __packed;
 124
 125 struct vmxnet3_rxdesc {
 126         uint64_t        addr;
 127
 128         uint32_t        len:14;
 129         uint32_t        btype:1;        /* Buffer type */
 130         uint32_t        dtype:1;        /* Descriptor type */
 131         uint32_t        rsvd:15;
 132         uint32_t        gen:1;
 133
 134         uint32_t        pad1:32;
 135 } __packed;
 136
 137 /* Buffer types */
 138 #define VMXNET3_BTYPE_HEAD      0       /* Head only */
 139 #define VMXNET3_BTYPE_BODY      1       /* Body only */
 140
 141 struct vmxnet3_rxcompdesc {
 142         uint32_t        rxd_idx:12;     /* Rx descriptor index */
 143         uint32_t        pad1:2;
 144         uint32_t        eop:1;          /* End of packet */
 145         uint32_t        sop:1;          /* Start of packet */
 146         uint32_t        qid:10;
 147         uint32_t        rss_type:4;
 148         uint32_t        no_csum:1;      /* No checksum calculated */
 149         uint32_t        pad2:1;
 150
 151         uint32_t        rss_hash:32;    /* RSS hash value */
 152
 153         uint32_t        len:14;
 154         uint32_t        error:1;
 155         uint32_t        vlan:1;         /* 802.1Q VLAN frame */
 156         uint32_t        vtag:16;        /* VLAN tag */
 157
 158         uint32_t        csum:16;
 159         uint32_t        csum_ok:1;      /* TCP/UDP checksum ok */
 160         uint32_t        udp:1;
 161         uint32_t        tcp:1;
 162         uint32_t        ipcsum_ok:1;    /* IP checksum OK */
 163         uint32_t        ipv6:1;
 164         uint32_t        ipv4:1;
 165         uint32_t        fragment:1;     /* IP fragment */
 166         uint32_t        fcs:1;          /* Frame CRC correct */
 167         uint32_t        type:7;
 168         uint32_t        gen:1;
 169 } __packed;
 170
 171 #define VMXNET3_RCD_RSS_TYPE_NONE       0
 172 #define VMXNET3_RCD_RSS_TYPE_IPV4       1
 173 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4    2
 174 #define VMXNET3_RCD_RSS_TYPE_IPV6       3
 175 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6    4
 176
 177 #define VMXNET3_REV1_MAGIC      0XBABEFEE1
 178
 179 #define VMXNET3_GOS_UNKNOWN     0x00
 180 #define VMXNET3_GOS_LINUX       0x04
 181 #define VMXNET3_GOS_WINDOWS     0x08
 182 #define VMXNET3_GOS_SOLARIS     0x0C
 183 #define VMXNET3_GOS_FREEBSD     0x10
 184 #define VMXNET3_GOS_PXE         0x14
 185
 186 #define VMXNET3_GOS_32BIT       0x01
 187 #define VMXNET3_GOS_64BIT       0x02
 188
 189 #define VMXNET3_MAX_TX_QUEUES   8
 190 #define VMXNET3_MAX_RX_QUEUES   16
 191 #define VMXNET3_MAX_INTRS \
 192     (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
 193
 194 #define VMXNET3_ICTRL_DISABLE_ALL       0x01
 195
 196 #define VMXNET3_RXMODE_UCAST    0x01
 197 #define VMXNET3_RXMODE_MCAST    0x02
 198 #define VMXNET3_RXMODE_BCAST    0x04
 199 #define VMXNET3_RXMODE_ALLMULTI 0x08
 200 #define VMXNET3_RXMODE_PROMISC  0x10
 201
 202 #define VMXNET3_EVENT_RQERROR   0x01
 203 #define VMXNET3_EVENT_TQERROR   0x02
 204 #define VMXNET3_EVENT_LINK      0x04
 205 #define VMXNET3_EVENT_DIC       0x08
 206 #define VMXNET3_EVENT_DEBUG     0x10
 207
 208 #define VMXNET3_MIN_MTU         60
 209 #define VMXNET3_MAX_MTU         9000
 210
 211 /* Interrupt mask mode. */
 212 #define VMXNET3_IMM_AUTO        0x00
 213 #define VMXNET3_IMM_ACTIVE      0x01
 214 #define VMXNET3_IMM_LAZY        0x02
 215
 216 /* Interrupt type. */
 217 #define VMXNET3_IT_AUTO         0x00
 218 #define VMXNET3_IT_LEGACY       0x01
 219 #define VMXNET3_IT_MSI          0x02
 220 #define VMXNET3_IT_MSIX         0x03
 221
 222 struct vmxnet3_driver_shared {
 223         uint32_t        magic;
 224         uint32_t        pad1;
 225
 226         /* Misc. control */
 227         uint32_t        version;                /* Driver version */
 228         uint32_t        guest;                  /* Guest OS */
 229         uint32_t        vmxnet3_revision;       /* Supported VMXNET3 revision */
 230         uint32_t        upt_version;            /* Supported UPT version */
 231         uint64_t        upt_features;
 232         uint64_t        driver_data;
 233         uint64_t        queue_shared;
 234         uint32_t        driver_data_len;
 235         uint32_t        queue_shared_len;
 236         uint32_t        mtu;
 237         uint16_t        nrxsg_max;
 238         uint8_t         ntxqueue;
 239         uint8_t         nrxqueue;
 240         uint32_t        reserved1[4];
 241
 242         /* Interrupt control */
 243         uint8_t         automask;
 244         uint8_t         nintr;
 245         uint8_t         evintr;
 246         uint8_t         modlevel[VMXNET3_MAX_INTRS];
 247         uint32_t        ictrl;
 248         uint32_t        reserved2[2];
 249
 250         /* Receive filter parameters */
 251         uint32_t        rxmode;
 252         uint16_t        mcast_tablelen;
 253         uint16_t        pad2;
 254         uint64_t        mcast_table;
 255         uint32_t        vlan_filter[4096 / 32];
 256
 257         struct {
 258                 uint32_t version;
 259                 uint32_t len;
 260                 uint64_t paddr;
 261         }               rss, pm, plugin;
 262
 263         uint32_t        event;
 264         uint32_t        reserved3[5];
 265 } __packed;
 266
 267 struct vmxnet3_txq_shared {
 268         /* Control */
 269         uint32_t        npending;
 270         uint32_t        intr_threshold;
 271         uint64_t        reserved1;
 272
 273         /* Config */
 274         uint64_t        cmd_ring;
 275         uint64_t        data_ring;
 276         uint64_t        comp_ring;
 277         uint64_t        driver_data;
 278         uint64_t        reserved2;
 279         uint32_t        cmd_ring_len;
 280         uint32_t        data_ring_len;
 281         uint32_t        comp_ring_len;
 282         uint32_t        driver_data_len;
 283         uint8_t         intr_idx;
 284         uint8_t         pad1[7];
 285
 286         /* Queue status */
 287         uint8_t         stopped;
 288         uint8_t         pad2[3];
 289         uint32_t        error;
 290
 291         struct          UPT1_TxStats stats;
 292
 293         uint8_t         pad3[88];
 294 } __packed;
 295
 296 struct vmxnet3_rxq_shared {
 297         uint8_t         update_rxhead;
 298         uint8_t         pad1[7];
 299         uint64_t        reserved1;
 300
 301         uint64_t        cmd_ring[2];
 302         uint64_t        comp_ring;
 303         uint64_t        driver_data;
 304         uint64_t        reserved2;
 305         uint32_t        cmd_ring_len[2];
 306         uint32_t        comp_ring_len;
 307         uint32_t        driver_data_len;
 308         uint8_t         intr_idx;
 309         uint8_t         pad2[7];
 310
 311         uint8_t         stopped;
 312         uint8_t         pad3[3];
 313         uint32_t        error;
 314
 315         struct          UPT1_RxStats stats;
 316
 317         uint8_t         pad4[88];
 318 } __packed;
 319
 320 #define UPT1_RSS_HASH_TYPE_NONE         0x00
 321 #define UPT1_RSS_HASH_TYPE_IPV4         0x01
 322 #define UPT1_RSS_HASH_TYPE_TCP_IPV4     0x02
 323 #define UPT1_RSS_HASH_TYPE_IPV6         0x04
 324 #define UPT1_RSS_HASH_TYPE_TCP_IPV6     0x08
 325
 326 #define UPT1_RSS_HASH_FUNC_NONE         0x00
 327 #define UPT1_RSS_HASH_FUNC_TOEPLITZ     0x01
 328
 329 #define UPT1_RSS_MAX_KEY_SIZE           40
 330 #define UPT1_RSS_MAX_IND_TABLE_SIZE     128
 331
 332 struct vmxnet3_rss_shared {
 333         uint16_t                hash_type;
 334         uint16_t                hash_func;
 335         uint16_t                hash_key_size;
 336         uint16_t                ind_table_size;
 337         uint8_t                 hash_key[UPT1_RSS_MAX_KEY_SIZE];
 338         uint8_t                 ind_table[UPT1_RSS_MAX_IND_TABLE_SIZE];
 339 } __packed;
 340
 341 #endif /* _IF_VMXREG_H */