sys/powerpc/include/hid.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $
  29  */
  30
  31 #ifndef _POWERPC_HID_H_
  32 #define _POWERPC_HID_H_
  33
  34 /* Hardware Implementation Dependent registers for the PowerPC */
  35 #define HID0_RADIX      0x0080000000000000      /* Enable Radix page tables (POWER9) */
  36
  37 #define HID0_EMCP       0x80000000  /* Enable machine check pin */
  38 #define HID0_DBP        0x40000000  /* Disable 60x bus parity generation */
  39 #define HID0_EBA        0x20000000  /* Enable 60x bus address parity checking */
  40 #define HID0_EBD        0x10000000  /* Enable 60x bus data parity checking */
  41 #define HID0_BCLK       0x08000000  /* CLK_OUT clock type selection */
  42 #define HID0_EICE       0x04000000  /* Enable ICE output */
  43 #define HID0_ECLK       0x02000000  /* CLK_OUT clock type selection */
  44 #define HID0_PAR        0x01000000  /* Disable precharge of ARTRY */
  45 #define HID0_STEN       0x01000000  /* Software table search enable (7450) */
  46 #define HID0_DEEPNAP    0x01000000  /* Enable deep nap mode (970) */
  47 #define HID0_HBATEN     0x00800000  /* High BAT enable (74[45][578])  */
  48 #define HID0_DOZE       0x00800000  /* Enable doze mode */
  49 #define HID0_NAP        0x00400000  /* Enable nap mode */
  50 #define HID0_SLEEP      0x00200000  /* Enable sleep mode */
  51 #define HID0_DPM        0x00100000  /* Enable Dynamic power management */
  52 #define HID0_RISEG      0x00080000  /* Read I-SEG */
  53 #define HID0_TG         0x00040000  /* Timebase Granularity (OEA64) */
  54 #define HID0_BHTCLR     0x00040000  /* Clear branch history table (7450) */
  55 #define HID0_EIEC       0x00040000  /* Enable internal error checking */
  56 #define HID0_XAEN       0x00020000  /* Enable eXtended Addressing (7450) */
  57 #define HID0_NHR        0x00010000  /* Not hard reset */
  58 #define HID0_ICE        0x00008000  /* Enable i-cache */
  59 #define HID0_DCE        0x00004000  /* Enable d-cache */
  60 #define HID0_ILOCK      0x00002000  /* i-cache lock */
  61 #define HID0_DLOCK      0x00001000  /* d-cache lock */
  62 #define HID0_ICFI       0x00000800  /* i-cache flush invalidate */
  63 #define HID0_DCFI       0x00000400  /* d-cache flush invalidate */
  64 #define HID0_SPD        0x00000200  /* Disable speculative cache access */
  65 #define HID0_XBSEN      0x00000100  /* Extended BAT block-size enable (7457) */
  66 #define HID0_IFEM       0x00000100  /* Enable M-bit for I-fetch */
  67 #define HID0_XBSEN      0x00000100  /* Extended BAT block size enable (7455+)*/
  68 #define HID0_SGE        0x00000080  /* Enable store gathering */
  69 #define HID0_DCFA       0x00000040  /* Data cache flush assist */
  70 #define HID0_BTIC       0x00000020  /* Enable BTIC */
  71 #define HID0_LRSTK      0x00000010  /* Link register stack enable (7450) */
  72 #define HID0_ABE        0x00000008  /* Enable address broadcast */
  73 #define HID0_FOLD       0x00000008  /* Branch folding enable (7450) */
  74 #define HID0_BHT        0x00000004  /* Enable branch history table */
  75 #define HID0_NOPTI      0x00000001  /* No-op the dcbt(st) */
  76
  77 #define HID0_AIM_TBEN   0x04000000  /* Time base enable (7450) */
  78
  79 #define HID0_E500_TBEN          0x00004000 /* Time Base and decr. enable */
  80 #define HID0_E500_SEL_TBCLK     0x00002000 /* Select Time Base clock */
  81 #define HID0_E500_MAS7UPDEN     0x00000080 /* Enable MAS7 update (e500v2) */
  82
  83 #define HID0_E500MC_L2MMU_MHD   0x40000000 /* L2MMU Multiple Hit Detection */
  84
  85 #define HID0_BITMASK                                                    \
  86     "\20"                                                               \
  87     "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR"      \
  88     "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR"    \
  89     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM"   \
  90     "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI"
  91
  92 #define HID0_7450_BITMASK                                               \
  93     "\20"                                                               \
  94     "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN"            \
  95     "\030HBATEN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \
  96     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN"  \
  97     "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
  98
  99 #define HID0_E500_BITMASK                                               \
 100     "\20"                                                               \
 101     "\040EMCP\037b1\036b2\035b3\034b4\033b5\032b6\031b7"                \
 102     "\030DOZE\027NAP\026SLEEP\025b11\024b12\023b13\022b14\021b15"       \
 103     "\020b16\017TBEN\016SEL_TBCLK\015b19\014b20\013b21\012b22\011b23"   \
 104     "\010EN_MAS7_UPDATE\007DCFA\006b26\005b27\004b28\003b29\002b30\001NOPTI"
 105
 106 #define HID0_970_BITMASK                                                \
 107     "\20"                                                               \
 108     "\040ONEPPC\037SINGLE\036ISYNCSC\035SERGP\031DEEPNAP\030DOZE"       \
 109     "\027NAP\025DPM\023TG\022HANGDETECT\021NHR\020INORDER"              \
 110     "\016TBCTRL\015TBEN\012CIABREN\011HDICEEN\001ENATTN"
 111
 112 #define HID0_E500MC_BITMASK                                             \
 113     "\20"                                                               \
 114     "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7"      \
 115     "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15"            \
 116     "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23"          \
 117     "\010EN_MAS7_UPDATE\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI"
 118
 119 #define HID0_E5500_BITMASK                                              \
 120     "\20"                                                               \
 121     "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7"      \
 122     "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15"            \
 123     "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23"          \
 124     "\010b24\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI"
 125
 126 /*
 127  *  HID0 bit definitions per cpu model
 128  *
 129  * bit  603     604     750     7400    7410    7450    7457    e500
 130  *   0  EMCP    EMCP    EMCP    EMCP    EMCP    -       -       EMCP
 131  *   1  -       ECP     DBP     -       -       -       -       -
 132  *   2  EBA     EBA     EBA     EBA     EDA     -       -       -
 133  *   3  EBD     EBD     EBD     EBD     EBD     -       -       -
 134  *   4  SBCLK   -       BCLK    BCKL    BCLK    -       -       -
 135  *   5  EICE    -       -       -       -       TBEN    TBEN    -
 136  *   6  ECLK    -       ECLK    ECLK    ECLK    -       -       -
 137  *   7  PAR     PAR     PAR     PAR     PAR     STEN    STEN    -
 138  *   8  DOZE    -       DOZE    DOZE    DOZE    -       HBATEN  DOZE
 139  *   9  NAP     -       NAP     NAP     NAP     NAP     NAP     NAP
 140  *  10  SLEEP   -       SLEEP   SLEEP   SLEEP   SLEEP   SLEEP   SLEEP
 141  *  11  DPM     -       DPM     DPM     DPM     DPM     DPM     -
 142  *  12  RISEG   -       -       RISEG   -       -       -       -
 143  *  13  -       -       -       EIEC    EIEC    BHTCLR  BHTCLR  -
 144  *  14  -       -       -       -       -       XAEN    XAEN    -
 145  *  15  -       NHR     NHR     NHR     NHR     NHR     NHR     -
 146  *  16  ICE     ICE     ICE     ICE     ICE     ICE     ICE     -
 147  *  17  DCE     DCE     DCE     DCE     DCE     DCE     DCE     TBEN
 148  *  18  ILOCK   ILOCK   ILOCK   ILOCK   ILOCK   ILOCK   ILOCK   SEL_TBCLK
 149  *  19  DLOCK   DLOCK   DLOCK   DLOCK   DLOCK   DLOCK   DLOCK   -
 150  *  20  ICFI    ICFI    ICFI    ICFI    ICFI    ICFI    ICFI    -
 151  *  21  DCFI    DCFI    DCFI    DCFI    DCFI    DCFI    DCFI    -
 152  *  22  -       -       SPD     SPD     SPG     SPD     SPD     -
 153  *  23  -       -       IFEM    IFTT    IFTT    -       XBSEN   -
 154  *  24  -       SIE     SGE     SGE     SGE     SGE     SGE     EN_MAS7_UPDATE
 155  *  25  -       -       DCFA    DCFA    DCFA    -       -       DCFA
 156  *  26  -       -       BTIC    BTIC    BTIC    BTIC    BTIC    -
 157  *  27  FBIOB   -       -       -       -       LRSTK   LRSTK   -
 158  *  28  -       -       ABE     -       -       FOLD    FOLD    -
 159  *  29  -       BHT     BHT     BHT     BHT     BHT     BHT     -
 160  *  30  -       -       -       NOPDST  NOPDST  NOPDST  NOPDST  -
 161  *  31  NOOPTI  -       NOOPTI  NOPTI   NOPTI   NOPTI   NOPTI   NOPTI
 162  *
 163  * bit  e500mc          e5500
 164  *   0  EMCP            EMCP
 165  *   1  EN_L2MMU_MHD    EN_L2MMU_MHD
 166  *   2  -               -
 167  *   3  -               -
 168  *   4  -               -
 169  *   5  -               -
 170  *   6  -               -
 171  *   7  -               -
 172  *   8  -               -
 173  *   9  -               -
 174  *  10  -               -
 175  *  11  -               -
 176  *  12  -               -
 177  *  13  -               -
 178  *  14  -               -
 179  *  15  -               -
 180  *  16  -               -
 181  *  17  -               -
 182  *  18  -               -
 183  *  19  -               -
 184  *  20  -               -
 185  *  21  -               -
 186  *  22  -               -
 187  *  23  -               -
 188  *  24  EN_MAS7_UPDATE  -
 189  *  25  DCFA            DCFA
 190  *  26  -               -
 191  *  27  CIGLSO          CIGLSO
 192  *  28  -               -
 193  *  29  -               -
 194  *  30  -               -
 195  *  31  NOPTI           NOPTI
 196  *
 197  *  604: ECP = Enable cache parity checking
 198  *  604: SIE = Serial instruction execution disable
 199  * 7450: TBEN = Time Base Enable
 200  * 7450: STEN = Software table lookup enable
 201  * 7450: BHTCLR = Branch history clear
 202  * 7450: XAEN = Extended Addressing Enabled
 203  * 7450: LRSTK = Link Register Stack Enable
 204  * 7450: FOLD = Branch folding enable
 205  * 7457: HBATEN = High BAT Enable
 206  * 7457: XBSEN = Extended BAT Block Size Enable
 207  */
 208
 209 #define HID1_E500_ABE   0x00001000  /* Address broadcast enable */
 210 #define HID1_E500_ASTME 0x00002000  /* Address bus streaming mode enable */
 211 #define HID1_E500_RFXE  0x00020000  /* Read fault exception enable */
 212
 213 #define HID0_E500_DEFAULT_SET   (HID0_EMCP | HID0_E500_TBEN | \
 214                                  HID0_E500_MAS7UPDEN)
 215 #define HID1_E500_DEFAULT_SET   (HID1_E500_ABE | HID1_E500_ASTME)
 216 #define HID0_E500MC_DEFAULT_SET (HID0_EMCP | HID0_E500MC_L2MMU_MHD | \
 217                                  HID0_E500_MAS7UPDEN)
 218 #define HID0_E5500_DEFAULT_SET  (HID0_EMCP | HID0_E500MC_L2MMU_MHD)
 219
 220 #define HID5_970_DCBZ_SIZE_HI   0x00000080UL    /* dcbz does a 32-byte store */
 221 #define HID4_970_DISABLE_LG_PG  0x00000004ULL   /* disables large pages */
 222
 223 #endif /* _POWERPC_HID_H_ */