2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2001 Tsubai Masanari. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * NetBSD: ki2c.c,v 1.11 2007/12/06 17:00:33 ad Exp
28 * Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp
32 * Support routines for the Keywest I2C controller.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
46 #include <dev/iicbus/iicbus.h>
47 #include <dev/iicbus/iiconf.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include "iicbus_if.h"
51 /* Keywest I2C Register offsets */
63 #define I2C_SPEED 0x03 /* Speed mask */
64 #define I2C_100kHz 0x00
65 #define I2C_50kHz 0x01
66 #define I2C_25kHz 0x02
67 #define I2C_MODE 0x0c /* Mode mask */
68 #define I2C_DUMBMODE 0x00 /* Dumb mode */
69 #define I2C_STDMODE 0x04 /* Standard mode */
70 #define I2C_STDSUBMODE 0x08 /* Standard mode + sub address */
71 #define I2C_COMBMODE 0x0c /* Combined mode */
72 #define I2C_PORT 0xf0 /* Port mask */
75 #define I2C_CT_AAK 0x01 /* Send AAK */
76 #define I2C_CT_ADDR 0x02 /* Send address(es) */
77 #define I2C_CT_STOP 0x04 /* Send STOP */
78 #define I2C_CT_START 0x08 /* Send START */
81 #define I2C_ST_BUSY 0x01 /* Busy */
82 #define I2C_ST_LASTAAK 0x02 /* Last AAK */
83 #define I2C_ST_LASTRW 0x04 /* Last R/W */
84 #define I2C_ST_SDA 0x08 /* SDA */
85 #define I2C_ST_SCL 0x10 /* SCL */
88 #define I2C_INT_DATA 0x01 /* Data byte sent/received */
89 #define I2C_INT_ADDR 0x02 /* Address sent */
90 #define I2C_INT_STOP 0x04 /* STOP condition sent */
91 #define I2C_INT_START 0x08 /* START condition sent */
95 #define I2C_READING 0x02
96 #define I2C_ERROR 0x04
97 #define I2C_SELECTED 0x08
103 struct resource
*sc_reg
;
105 struct resource
*sc_irq
;
111 uint16_t sc_i2c_base
;
115 static int kiic_probe(device_t dev
);
116 static int kiic_attach(device_t dev
);
117 static void kiic_writereg(struct kiic_softc
*sc
, u_int
, u_int
);
118 static u_int
kiic_readreg(struct kiic_softc
*, u_int
);
119 static void kiic_setport(struct kiic_softc
*, u_int
);
120 static void kiic_setmode(struct kiic_softc
*, u_int
);
121 static void kiic_setspeed(struct kiic_softc
*, u_int
);
122 static void kiic_intr(void *xsc
);
123 static int kiic_transfer(device_t dev
, struct iic_msg
*msgs
,
125 static phandle_t
kiic_get_node(device_t bus
, device_t dev
);
127 static device_method_t kiic_methods
[] = {
128 /* device interface */
129 DEVMETHOD(device_probe
, kiic_probe
),
130 DEVMETHOD(device_attach
, kiic_attach
),
132 /* iicbus interface */
133 DEVMETHOD(iicbus_callback
, iicbus_null_callback
),
134 DEVMETHOD(iicbus_transfer
, kiic_transfer
),
136 /* ofw_bus interface */
137 DEVMETHOD(ofw_bus_get_node
, kiic_get_node
),
141 static driver_t kiic_driver
= {
144 sizeof(struct kiic_softc
)
147 DRIVER_MODULE(kiic
, macio
, kiic_driver
, 0, 0);
148 DRIVER_MODULE(kiic
, unin
, kiic_driver
, 0, 0);
151 kiic_probe(device_t self
)
155 name
= ofw_bus_get_name(self
);
156 if (name
&& strcmp(name
, "i2c") == 0) {
157 device_set_desc(self
, "Keywest I2C controller");
165 kiic_attach(device_t self
)
167 struct kiic_softc
*sc
= device_get_softc(self
);
172 bzero(sc
, sizeof(*sc
));
175 node
= ofw_bus_get_node(self
);
176 if (node
== 0 || node
== -1) {
181 sc
->sc_reg
= bus_alloc_resource_any(self
, SYS_RES_MEMORY
,
183 if (sc
->sc_reg
== NULL
) {
187 if (OF_getencprop(node
, "AAPL,i2c-rate", &rate
, 4) != 4) {
188 device_printf(self
, "cannot get i2c-rate\n");
191 if (OF_getencprop(node
, "AAPL,address-step", &sc
->sc_regstep
, 4) != 4) {
192 device_printf(self
, "unable to find i2c address step\n");
197 * Some Keywest I2C devices have their children attached directly
198 * underneath them. Some have a single 'iicbus' child with the
199 * devices underneath that. Sort this out, and make sure that the
200 * OFW I2C layer has the correct node.
202 * Note: the I2C children of the Uninorth bridges have two ports.
203 * In general, the port is designated in the 9th bit of the I2C
204 * address. However, for kiic devices with children attached below
205 * an i2c-bus node, the port is indicated in the 'reg' property
206 * of the i2c-bus node.
211 node
= OF_child(node
);
212 if (OF_getprop(node
, "name", name
, sizeof(name
)) > 0) {
213 if (strcmp(name
,"i2c-bus") == 0) {
215 if (OF_getprop(node
, "reg", ®
, sizeof(reg
)) > 0)
216 sc
->sc_i2c_base
= reg
<< 8;
222 mtx_init(&sc
->sc_mutex
, "kiic", NULL
, MTX_DEF
);
224 sc
->sc_irq
= bus_alloc_resource_any(self
, SYS_RES_IRQ
, &sc
->sc_irqrid
,
226 bus_setup_intr(self
, sc
->sc_irq
, INTR_TYPE_MISC
| INTR_MPSAFE
, NULL
,
227 kiic_intr
, sc
, &sc
->sc_ih
);
229 kiic_writereg(sc
, ISR
, kiic_readreg(sc
, ISR
));
230 kiic_writereg(sc
, STATUS
, 0);
231 kiic_writereg(sc
, IER
, 0);
233 kiic_setmode(sc
, I2C_STDMODE
);
234 kiic_setspeed(sc
, I2C_100kHz
); /* XXX rate */
236 kiic_writereg(sc
, IER
, I2C_INT_DATA
| I2C_INT_ADDR
| I2C_INT_STOP
);
239 device_printf(self
, "Revision: %02X\n", kiic_readreg(sc
, REV
));
241 /* Add the IIC bus layer */
242 sc
->sc_iicbus
= device_add_child(self
, "iicbus", DEVICE_UNIT_ANY
);
244 bus_attach_children(self
);
249 kiic_writereg(struct kiic_softc
*sc
, u_int reg
, u_int val
)
251 bus_write_4(sc
->sc_reg
, sc
->sc_regstep
* reg
, val
);
252 DELAY(100); /* register access delay */
256 kiic_readreg(struct kiic_softc
*sc
, u_int reg
)
258 return bus_read_4(sc
->sc_reg
, sc
->sc_regstep
* reg
) & 0xff;
262 kiic_setmode(struct kiic_softc
*sc
, u_int mode
)
266 KASSERT((mode
& ~I2C_MODE
) == 0, ("bad mode"));
267 x
= kiic_readreg(sc
, MODE
);
270 kiic_writereg(sc
, MODE
, x
);
274 kiic_setport(struct kiic_softc
*sc
, u_int port
)
278 KASSERT(port
== 1 || port
== 0, ("bad port"));
279 x
= kiic_readreg(sc
, MODE
);
282 kiic_writereg(sc
, MODE
, x
);
286 kiic_setspeed(struct kiic_softc
*sc
, u_int speed
)
290 KASSERT((speed
& ~I2C_SPEED
) == 0, ("bad speed"));
291 x
= kiic_readreg(sc
, MODE
);
294 kiic_writereg(sc
, MODE
, x
);
300 struct kiic_softc
*sc
= xsc
;
304 mtx_lock(&sc
->sc_mutex
);
305 isr
= kiic_readreg(sc
, ISR
);
307 if (isr
& I2C_INT_ADDR
) {
308 sc
->sc_flags
|= I2C_SELECTED
;
310 if (sc
->sc_flags
& I2C_READING
) {
311 if (sc
->sc_resid
> 1) {
312 x
= kiic_readreg(sc
, CONTROL
);
314 kiic_writereg(sc
, CONTROL
, x
);
317 kiic_writereg(sc
, DATA
, *sc
->sc_data
++);
322 if (isr
& I2C_INT_DATA
) {
323 if (sc
->sc_flags
& I2C_READING
) {
324 if (sc
->sc_resid
> 0) {
325 *sc
->sc_data
++ = kiic_readreg(sc
, DATA
);
328 if (sc
->sc_resid
== 0) /* done */
329 kiic_writereg(sc
, CONTROL
, 0);
331 if (sc
->sc_resid
== 0) {
332 x
= kiic_readreg(sc
, CONTROL
);
334 kiic_writereg(sc
, CONTROL
, x
);
336 kiic_writereg(sc
, DATA
, *sc
->sc_data
++);
342 if (isr
& I2C_INT_STOP
) {
343 kiic_writereg(sc
, CONTROL
, 0);
344 sc
->sc_flags
&= ~I2C_SELECTED
;
348 kiic_writereg(sc
, ISR
, isr
);
349 mtx_unlock(&sc
->sc_mutex
);
353 kiic_transfer(device_t dev
, struct iic_msg
*msgs
, uint32_t nmsgs
)
355 struct kiic_softc
*sc
;
360 sc
= device_get_softc(dev
);
364 mtx_lock(&sc
->sc_mutex
);
366 if (sc
->sc_flags
& I2C_BUSY
)
367 mtx_sleep(dev
, &sc
->sc_mutex
, 0, "kiic", timo
);
369 if (sc
->sc_flags
& I2C_BUSY
) {
370 mtx_unlock(&sc
->sc_mutex
);
374 sc
->sc_flags
= I2C_BUSY
;
376 /* Clear pending interrupts, and reset controller */
377 kiic_writereg(sc
, ISR
, kiic_readreg(sc
, ISR
));
378 kiic_writereg(sc
, STATUS
, 0);
380 for (i
= 0; i
< nmsgs
; i
++) {
381 if (msgs
[i
].flags
& IIC_M_NOSTOP
) {
382 if (msgs
[i
+1].flags
& IIC_M_RD
)
383 kiic_setmode(sc
, I2C_COMBMODE
);
385 kiic_setmode(sc
, I2C_STDSUBMODE
);
386 KASSERT(msgs
[i
].len
== 1, ("oversize I2C message"));
387 subaddr
= msgs
[i
].buf
[0];
390 kiic_setmode(sc
, I2C_STDMODE
);
393 sc
->sc_data
= msgs
[i
].buf
;
394 sc
->sc_resid
= msgs
[i
].len
;
395 sc
->sc_flags
= I2C_BUSY
;
396 addr
= msgs
[i
].slave
;
397 timo
= 1000 + sc
->sc_resid
* 200;
400 if (msgs
[i
].flags
& IIC_M_RD
) {
401 sc
->sc_flags
|= I2C_READING
;
405 addr
|= sc
->sc_i2c_base
;
407 kiic_setport(sc
, (addr
& 0x100) >> 8);
408 kiic_writereg(sc
, ADDR
, addr
& 0xff);
409 kiic_writereg(sc
, SUBADDR
, subaddr
);
411 x
= kiic_readreg(sc
, CONTROL
) | I2C_CT_ADDR
;
412 kiic_writereg(sc
, CONTROL
, x
);
414 err
= mtx_sleep(dev
, &sc
->sc_mutex
, 0, "kiic", timo
);
416 msgs
[i
].len
-= sc
->sc_resid
;
418 if ((sc
->sc_flags
& I2C_ERROR
) || err
== EWOULDBLOCK
) {
419 device_printf(sc
->sc_dev
, "I2C error\n");
421 mtx_unlock(&sc
->sc_mutex
);
428 mtx_unlock(&sc
->sc_mutex
);
434 kiic_get_node(device_t bus
, device_t dev
)
436 struct kiic_softc
*sc
;
438 sc
= device_get_softc(bus
);
439 /* We only have one child, the I2C bus, which needs our own node. */