2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright 2002 by Peter Grehan. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Driver for KeyLargo/Pangea, the MacPPC south bridge ASIC.
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
45 #include <machine/bus.h>
46 #include <machine/intr_machdep.h>
47 #include <machine/resource.h>
48 #include <machine/vmparam.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/ofw/openfirm.h>
54 #include <powerpc/powermac/maciovar.h>
55 #include <powerpc/powermac/platform_powermac.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
67 struct rman sc_mem_rman
;
71 struct resource
*sc_memr
;
77 static MALLOC_DEFINE(M_MACIO
, "macio", "macio device information");
79 static int macio_probe(device_t
);
80 static int macio_attach(device_t
);
81 static int macio_print_child(device_t dev
, device_t child
);
82 static void macio_probe_nomatch(device_t
, device_t
);
83 static struct rman
*macio_get_rman(device_t
, int, u_int
);
84 static struct resource
*macio_alloc_resource(device_t
, device_t
, int, int *,
85 rman_res_t
, rman_res_t
, rman_res_t
,
87 static int macio_adjust_resource(device_t
, device_t
, struct resource
*,
88 rman_res_t
, rman_res_t
);
89 static int macio_activate_resource(device_t
, device_t
, struct resource
*);
90 static int macio_deactivate_resource(device_t
, device_t
, struct resource
*);
91 static int macio_release_resource(device_t
, device_t
, struct resource
*);
92 static int macio_map_resource(device_t
, device_t
, struct resource
*,
93 struct resource_map_request
*,
94 struct resource_map
*);
95 static int macio_unmap_resource(device_t
, device_t
, struct resource
*,
96 struct resource_map
*);
97 static struct resource_list
*macio_get_resource_list (device_t
, device_t
);
98 static ofw_bus_get_devinfo_t macio_get_devinfo
;
99 #if !defined(__powerpc64__) && defined(SMP)
100 static void macio_freeze_timebase(device_t
, bool);
104 * Bus interface definition
106 static device_method_t macio_methods
[] = {
107 /* Device interface */
108 DEVMETHOD(device_probe
, macio_probe
),
109 DEVMETHOD(device_attach
, macio_attach
),
110 DEVMETHOD(device_detach
, bus_generic_detach
),
111 DEVMETHOD(device_shutdown
, bus_generic_shutdown
),
112 DEVMETHOD(device_suspend
, bus_generic_suspend
),
113 DEVMETHOD(device_resume
, bus_generic_resume
),
116 DEVMETHOD(bus_print_child
, macio_print_child
),
117 DEVMETHOD(bus_probe_nomatch
, macio_probe_nomatch
),
118 DEVMETHOD(bus_setup_intr
, bus_generic_setup_intr
),
119 DEVMETHOD(bus_teardown_intr
, bus_generic_teardown_intr
),
121 DEVMETHOD(bus_get_rman
, macio_get_rman
),
122 DEVMETHOD(bus_alloc_resource
, macio_alloc_resource
),
123 DEVMETHOD(bus_adjust_resource
, macio_adjust_resource
),
124 DEVMETHOD(bus_release_resource
, macio_release_resource
),
125 DEVMETHOD(bus_activate_resource
, macio_activate_resource
),
126 DEVMETHOD(bus_deactivate_resource
, macio_deactivate_resource
),
127 DEVMETHOD(bus_map_resource
, macio_map_resource
),
128 DEVMETHOD(bus_unmap_resource
, macio_unmap_resource
),
129 DEVMETHOD(bus_get_resource_list
, macio_get_resource_list
),
131 DEVMETHOD(bus_child_pnpinfo
, ofw_bus_gen_child_pnpinfo
),
133 /* ofw_bus interface */
134 DEVMETHOD(ofw_bus_get_devinfo
, macio_get_devinfo
),
135 DEVMETHOD(ofw_bus_get_compat
, ofw_bus_gen_get_compat
),
136 DEVMETHOD(ofw_bus_get_model
, ofw_bus_gen_get_model
),
137 DEVMETHOD(ofw_bus_get_name
, ofw_bus_gen_get_name
),
138 DEVMETHOD(ofw_bus_get_node
, ofw_bus_gen_get_node
),
139 DEVMETHOD(ofw_bus_get_type
, ofw_bus_gen_get_type
),
143 static driver_t macio_pci_driver
= {
146 sizeof(struct macio_softc
)
149 EARLY_DRIVER_MODULE(macio
, pci
, macio_pci_driver
, 0, 0, BUS_PASS_BUS
);
152 * PCI ID search table
154 static struct macio_pci_dev
{
157 } macio_pci_devlist
[] = {
158 { 0x0017106b, "Paddington I/O Controller" },
159 { 0x0022106b, "KeyLargo I/O Controller" },
160 { 0x0025106b, "Pangea I/O Controller" },
161 { 0x003e106b, "Intrepid I/O Controller" },
162 { 0x0041106b, "K2 KeyLargo I/O Controller" },
163 { 0x004f106b, "Shasta I/O Controller" },
168 * Devices to exclude from the probe
169 * XXX some of these may be required in the future...
171 #define MACIO_QUIRK_IGNORE 0x00000001
172 #define MACIO_QUIRK_CHILD_HAS_INTR 0x00000002
173 #define MACIO_QUIRK_USE_CHILD_REG 0x00000004
175 struct macio_quirk_entry
{
180 static struct macio_quirk_entry macio_quirks
[] = {
181 { "escc-legacy", MACIO_QUIRK_IGNORE
},
182 { "timer", MACIO_QUIRK_IGNORE
},
183 { "escc", MACIO_QUIRK_CHILD_HAS_INTR
},
184 { "i2s", MACIO_QUIRK_CHILD_HAS_INTR
|
185 MACIO_QUIRK_USE_CHILD_REG
},
190 macio_get_quirks(const char *name
)
192 struct macio_quirk_entry
*mqe
;
194 for (mqe
= macio_quirks
; mqe
->mq_name
!= NULL
; mqe
++)
195 if (strcmp(name
, mqe
->mq_name
) == 0)
196 return (mqe
->mq_quirks
);
201 * Add an interrupt to the dev's resource list if present
204 macio_add_intr(phandle_t devnode
, struct macio_devinfo
*dinfo
)
211 if (dinfo
->mdi_ninterrupts
>= 6) {
212 printf("macio: device has more than 6 interrupts\n");
216 nintr
= OF_getprop_alloc_multi(devnode
, "interrupts", sizeof(*intr
),
219 nintr
= OF_getprop_alloc_multi(devnode
, "AAPL,interrupts",
220 sizeof(*intr
), (void **)&intr
);
228 if (OF_getprop(devnode
, "interrupt-parent", &iparent
, sizeof(iparent
))
230 panic("Interrupt but no interrupt parent!\n");
232 if (OF_getprop(OF_node_from_xref(iparent
), "#interrupt-cells", &icells
,
233 sizeof(icells
)) <= 0)
236 for (i
= 0; i
< nintr
; i
+=icells
) {
237 u_int irq
= MAP_IRQ(iparent
, intr
[i
]);
239 resource_list_add(&dinfo
->mdi_resources
, SYS_RES_IRQ
,
240 dinfo
->mdi_ninterrupts
, irq
, irq
, 1);
242 dinfo
->mdi_interrupts
[dinfo
->mdi_ninterrupts
] = irq
;
243 dinfo
->mdi_ninterrupts
++;
248 macio_add_reg(phandle_t devnode
, struct macio_devinfo
*dinfo
)
250 struct macio_reg
*reg
, *regp
;
253 int i
, layout_id
= 0, nreg
, res
;
255 nreg
= OF_getprop_alloc_multi(devnode
, "reg", sizeof(*reg
), (void **)®
);
260 * Some G5's have broken properties in the i2s-a area. If so we try
261 * to fix it. Right now we know of two different cases, one for
262 * sound layout-id 36 and the other one for sound layout-id 76.
263 * What is missing is the base address for the memory addresses.
264 * We take them from the parent node (i2s) and use the size
265 * information from the child.
268 if (reg
[0].mr_base
== 0) {
269 child
= OF_child(devnode
);
271 res
= OF_getprop(child
, "name", buf
, sizeof(buf
));
272 if (res
> 0 && strcmp(buf
, "sound") == 0)
274 child
= OF_peer(child
);
277 res
= OF_getprop(child
, "layout-id", &layout_id
,
280 if (res
> 0 && (layout_id
== 36 || layout_id
== 76)) {
281 res
= OF_getprop_alloc_multi(OF_parent(devnode
), "reg",
282 sizeof(*regp
), (void **)®p
);
284 reg
[1].mr_base
= regp
[1].mr_base
;
285 reg
[2].mr_base
= regp
[1].mr_base
+ reg
[1].mr_size
;
289 for (i
= 0; i
< nreg
; i
++) {
290 resource_list_add(&dinfo
->mdi_resources
, SYS_RES_MEMORY
, i
,
291 reg
[i
].mr_base
, reg
[i
].mr_base
+ reg
[i
].mr_size
,
300 macio_probe(device_t dev
)
305 devid
= pci_get_devid(dev
);
306 for (i
= 0; macio_pci_devlist
[i
].mpd_desc
!= NULL
; i
++) {
307 if (devid
== macio_pci_devlist
[i
].mpd_devid
) {
308 device_set_desc(dev
, macio_pci_devlist
[i
].mpd_desc
);
317 * PCI attach: scan Open Firmware child nodes, and attach these as children
321 macio_attach(device_t dev
)
323 struct macio_softc
*sc
;
324 struct macio_devinfo
*dinfo
;
333 sc
= device_get_softc(dev
);
334 root
= sc
->sc_node
= ofw_bus_get_node(dev
);
337 * Locate the device node and it's base address
339 if (OF_getprop(root
, "assigned-addresses",
340 reg
, sizeof(reg
)) < (ssize_t
)sizeof(reg
)) {
344 /* Used later to see if we have to enable the I2S part. */
345 OF_getprop(root
, "compatible", compat
, sizeof(compat
));
347 sc
->sc_base
= reg
[2];
348 sc
->sc_size
= MACIO_REG_SIZE
;
350 sc
->sc_memrid
= PCIR_BAR(0);
351 sc
->sc_memr
= bus_alloc_resource_any(dev
, SYS_RES_MEMORY
,
352 &sc
->sc_memrid
, RF_ACTIVE
);
354 sc
->sc_mem_rman
.rm_type
= RMAN_ARRAY
;
355 sc
->sc_mem_rman
.rm_descr
= "MacIO Device Memory";
356 error
= rman_init(&sc
->sc_mem_rman
);
358 device_printf(dev
, "rman_init() failed. error = %d\n", error
);
361 error
= rman_manage_region(&sc
->sc_mem_rman
, 0, sc
->sc_size
);
364 "rman_manage_region() failed. error = %d\n", error
);
369 * Iterate through the sub-devices
371 for (child
= OF_child(root
); child
!= 0; child
= OF_peer(child
)) {
372 dinfo
= malloc(sizeof(*dinfo
), M_MACIO
, M_WAITOK
| M_ZERO
);
373 if (ofw_bus_gen_setup_devinfo(&dinfo
->mdi_obdinfo
, child
) !=
375 free(dinfo
, M_MACIO
);
378 quirks
= macio_get_quirks(dinfo
->mdi_obdinfo
.obd_name
);
379 if ((quirks
& MACIO_QUIRK_IGNORE
) != 0) {
380 ofw_bus_gen_destroy_devinfo(&dinfo
->mdi_obdinfo
);
381 free(dinfo
, M_MACIO
);
384 resource_list_init(&dinfo
->mdi_resources
);
385 dinfo
->mdi_ninterrupts
= 0;
386 macio_add_intr(child
, dinfo
);
387 if ((quirks
& MACIO_QUIRK_USE_CHILD_REG
) != 0)
388 macio_add_reg(OF_child(child
), dinfo
);
390 macio_add_reg(child
, dinfo
);
391 if ((quirks
& MACIO_QUIRK_CHILD_HAS_INTR
) != 0)
392 for (subchild
= OF_child(child
); subchild
!= 0;
393 subchild
= OF_peer(subchild
))
394 macio_add_intr(subchild
, dinfo
);
395 cdev
= device_add_child(dev
, NULL
, DEVICE_UNIT_ANY
);
397 device_printf(dev
, "<%s>: device_add_child failed\n",
398 dinfo
->mdi_obdinfo
.obd_name
);
399 resource_list_free(&dinfo
->mdi_resources
);
400 ofw_bus_gen_destroy_devinfo(&dinfo
->mdi_obdinfo
);
401 free(dinfo
, M_MACIO
);
404 device_set_ivars(cdev
, dinfo
);
406 /* Set FCRs to enable some devices */
407 if (sc
->sc_memr
== NULL
)
410 if (strcmp(ofw_bus_get_name(cdev
), "bmac") == 0 ||
411 (ofw_bus_get_compat(cdev
) != NULL
&&
412 strcmp(ofw_bus_get_compat(cdev
), "bmac+") == 0)) {
415 fcr
= bus_read_4(sc
->sc_memr
, HEATHROW_FCR
);
417 fcr
|= FCR_ENET_ENABLE
& ~FCR_ENET_RESET
;
418 bus_write_4(sc
->sc_memr
, HEATHROW_FCR
, fcr
);
420 fcr
|= FCR_ENET_RESET
;
421 bus_write_4(sc
->sc_memr
, HEATHROW_FCR
, fcr
);
423 fcr
&= ~FCR_ENET_RESET
;
424 bus_write_4(sc
->sc_memr
, HEATHROW_FCR
, fcr
);
427 bus_write_4(sc
->sc_memr
, HEATHROW_FCR
, fcr
);
431 * Make sure the I2S0 and the I2S0_CLK are enabled.
432 * On certain G5's they are not.
434 if ((strcmp(ofw_bus_get_name(cdev
), "i2s") == 0) &&
435 (strcmp(compat
, "K2-Keylargo") == 0)) {
438 fcr1
= bus_read_4(sc
->sc_memr
, KEYLARGO_FCR1
);
439 fcr1
|= FCR1_I2S0_CLK_ENABLE
| FCR1_I2S0_ENABLE
;
440 bus_write_4(sc
->sc_memr
, KEYLARGO_FCR1
, fcr1
);
444 #if !defined(__powerpc64__) && defined(SMP)
446 * Detect an SMP G4 machine.
448 * On SMP G4, timebase freeze is via a GPIO on macio.
450 * When we are on an SMP G4, we need to install a handler to
451 * perform timebase freeze/unfreeze on behalf of the platform.
453 if ((child
= OF_finddevice("/cpus/PowerPC,G4@0")) != -1 &&
454 OF_peer(child
) != -1) {
455 if (OF_getprop(child
, "timebase-enable", &sc
->sc_timebase
,
456 sizeof(sc
->sc_timebase
)) <= 0)
457 sc
->sc_timebase
= KEYLARGO_GPIO_BASE
+ 0x09;
458 powermac_register_timebase(dev
, macio_freeze_timebase
);
459 device_printf(dev
, "GPIO timebase control at 0x%x\n",
464 bus_attach_children(dev
);
469 macio_print_child(device_t dev
, device_t child
)
471 struct macio_devinfo
*dinfo
;
472 struct resource_list
*rl
;
475 dinfo
= device_get_ivars(child
);
476 rl
= &dinfo
->mdi_resources
;
478 retval
+= bus_print_child_header(dev
, child
);
480 retval
+= resource_list_print_type(rl
, "mem", SYS_RES_MEMORY
, "%#jx");
481 retval
+= resource_list_print_type(rl
, "irq", SYS_RES_IRQ
, "%jd");
483 retval
+= bus_print_child_footer(dev
, child
);
489 macio_probe_nomatch(device_t dev
, device_t child
)
491 struct macio_devinfo
*dinfo
;
492 struct resource_list
*rl
;
496 dinfo
= device_get_ivars(child
);
497 rl
= &dinfo
->mdi_resources
;
499 if ((type
= ofw_bus_get_type(child
)) == NULL
)
501 device_printf(dev
, "<%s, %s>", type
, ofw_bus_get_name(child
));
502 resource_list_print_type(rl
, "mem", SYS_RES_MEMORY
, "%#jx");
503 resource_list_print_type(rl
, "irq", SYS_RES_IRQ
, "%jd");
504 printf(" (no driver attached)\n");
509 macio_get_rman(device_t bus
, int type
, u_int flags
)
511 struct macio_softc
*sc
;
513 sc
= device_get_softc(bus
);
517 return (&sc
->sc_mem_rman
);
523 static struct resource
*
524 macio_alloc_resource(device_t bus
, device_t child
, int type
, int *rid
,
525 rman_res_t start
, rman_res_t end
, rman_res_t count
,
528 rman_res_t adjstart
, adjend
, adjcount
;
529 struct macio_devinfo
*dinfo
;
530 struct resource_list_entry
*rle
;
532 dinfo
= device_get_ivars(child
);
537 rle
= resource_list_find(&dinfo
->mdi_resources
, SYS_RES_MEMORY
,
540 device_printf(bus
, "no rle for %s memory %d\n",
541 device_get_nameunit(child
), *rid
);
545 if (start
< rle
->start
)
546 adjstart
= rle
->start
;
547 else if (start
> rle
->end
)
552 if (end
< rle
->start
)
554 else if (end
> rle
->end
)
559 adjcount
= adjend
- adjstart
;
561 return (bus_generic_rman_alloc_resource(bus
, child
, type
, rid
,
562 adjstart
, adjend
, adjcount
, flags
));
565 /* Check for passthrough from subattachments like macgpio */
566 if (device_get_parent(child
) != bus
)
567 return BUS_ALLOC_RESOURCE(device_get_parent(bus
), child
,
568 type
, rid
, start
, end
, count
, flags
);
570 rle
= resource_list_find(&dinfo
->mdi_resources
, SYS_RES_IRQ
,
573 if (dinfo
->mdi_ninterrupts
>= 6) {
575 "%s has more than 6 interrupts\n",
576 device_get_nameunit(child
));
579 resource_list_add(&dinfo
->mdi_resources
, SYS_RES_IRQ
,
580 dinfo
->mdi_ninterrupts
, start
, start
, 1);
582 dinfo
->mdi_interrupts
[dinfo
->mdi_ninterrupts
] = start
;
583 dinfo
->mdi_ninterrupts
++;
586 return (resource_list_alloc(&dinfo
->mdi_resources
, bus
, child
,
587 type
, rid
, start
, end
, count
, flags
));
590 device_printf(bus
, "unknown resource request from %s\n",
591 device_get_nameunit(child
));
597 macio_adjust_resource(device_t bus
, device_t child
, struct resource
*r
,
598 rman_res_t start
, rman_res_t end
)
600 switch (rman_get_type(r
)) {
603 return (bus_generic_rman_adjust_resource(bus
, child
, r
, start
,
606 return (bus_generic_adjust_resource(bus
, child
, r
, start
, end
));
613 macio_release_resource(device_t bus
, device_t child
, struct resource
*res
)
615 switch (rman_get_type(res
)) {
618 return (bus_generic_rman_release_resource(bus
, child
, res
));
620 return (bus_generic_rl_release_resource(bus
, child
, res
));
627 macio_activate_resource(device_t bus
, device_t child
, struct resource
*res
)
629 switch (rman_get_type(res
)) {
632 return (bus_generic_rman_activate_resource(bus
, child
, res
));
634 return (bus_generic_activate_resource(bus
, child
, res
));
641 macio_deactivate_resource(device_t bus
, device_t child
, struct resource
*res
)
643 switch (rman_get_type(res
)) {
646 return (bus_generic_rman_deactivate_resource(bus
, child
, res
));
648 return (bus_generic_deactivate_resource(bus
, child
, res
));
655 macio_map_resource(device_t bus
, device_t child
, struct resource
*r
,
656 struct resource_map_request
*argsp
, struct resource_map
*map
)
658 struct resource_map_request args
;
659 struct macio_softc
*sc
;
660 rman_res_t length
, start
;
663 /* Resources must be active to be mapped. */
664 if (!(rman_get_flags(r
) & RF_ACTIVE
))
667 /* Mappings are only supported on I/O and memory resources. */
668 switch (rman_get_type(r
)) {
676 resource_init_map_request(&args
);
677 error
= resource_validate_map_request(r
, argsp
, &args
, &start
, &length
);
682 printf("nexus mapdev: start %jx, len %jd\n",
683 (uintmax_t)start
, (uintmax_t)length
);
685 sc
= device_get_softc(bus
);
686 map
->r_vaddr
= pmap_mapdev_attr((vm_paddr_t
)start
+ sc
->sc_base
,
687 length
, args
.memattr
);
688 if (map
->r_vaddr
== NULL
)
690 map
->r_size
= length
;
691 map
->r_bustag
= &bs_le_tag
;
692 map
->r_bushandle
= (bus_space_handle_t
)map
->r_vaddr
;
697 macio_unmap_resource(device_t bus
, device_t child
, struct resource
*r
,
698 struct resource_map
*map
)
701 * If this is a memory resource, unmap it.
703 switch (rman_get_type(r
)) {
706 pmap_unmapdev(map
->r_vaddr
, map
->r_size
);
714 static struct resource_list
*
715 macio_get_resource_list (device_t dev
, device_t child
)
717 struct macio_devinfo
*dinfo
;
719 dinfo
= device_get_ivars(child
);
720 return (&dinfo
->mdi_resources
);
723 static const struct ofw_bus_devinfo
*
724 macio_get_devinfo(device_t dev
, device_t child
)
726 struct macio_devinfo
*dinfo
;
728 dinfo
= device_get_ivars(child
);
729 return (&dinfo
->mdi_obdinfo
);
733 macio_enable_wireless(device_t dev
, bool enable
)
735 struct macio_softc
*sc
= device_get_softc(dev
);
739 x
= bus_read_4(sc
->sc_memr
, KEYLARGO_FCR2
);
741 bus_write_4(sc
->sc_memr
, KEYLARGO_FCR2
, x
);
743 /* Enable card slot. */
744 bus_write_1(sc
->sc_memr
, KEYLARGO_GPIO_BASE
+ 0x0f, 5);
746 bus_write_1(sc
->sc_memr
, KEYLARGO_GPIO_BASE
+ 0x0f, 4);
748 x
= bus_read_4(sc
->sc_memr
, KEYLARGO_FCR2
);
751 bus_write_4(sc
->sc_memr
, KEYLARGO_FCR2
, x
);
752 /* out8(gpio + 0x10, 4); */
754 bus_write_1(sc
->sc_memr
, KEYLARGO_EXTINT_GPIO_REG_BASE
+ 0x0b, 0);
755 bus_write_1(sc
->sc_memr
, KEYLARGO_EXTINT_GPIO_REG_BASE
+ 0x0a, 0x28);
756 bus_write_1(sc
->sc_memr
, KEYLARGO_EXTINT_GPIO_REG_BASE
+ 0x0d, 0x28);
757 bus_write_1(sc
->sc_memr
, KEYLARGO_GPIO_BASE
+ 0x0d, 0x28);
758 bus_write_1(sc
->sc_memr
, KEYLARGO_GPIO_BASE
+ 0x0e, 0x28);
759 bus_write_4(sc
->sc_memr
, 0x1c000, 0);
761 /* Initialize the card. */
762 bus_write_4(sc
->sc_memr
, 0x1a3e0, 0x41);
763 x
= bus_read_4(sc
->sc_memr
, KEYLARGO_FCR2
);
765 bus_write_4(sc
->sc_memr
, KEYLARGO_FCR2
, x
);
767 x
= bus_read_4(sc
->sc_memr
, KEYLARGO_FCR2
);
769 bus_write_4(sc
->sc_memr
, KEYLARGO_FCR2
, x
);
770 /* out8(gpio + 0x10, 0); */
776 #if !defined(__powerpc64__) && defined(SMP)
778 macio_freeze_timebase(device_t dev
, bool freeze
)
780 struct macio_softc
*sc
= device_get_softc(dev
);
783 bus_write_1(sc
->sc_memr
, sc
->sc_timebase
, 4);
785 bus_write_1(sc
->sc_memr
, sc
->sc_timebase
, 0);
787 bus_read_1(sc
->sc_memr
, sc
->sc_timebase
);