src/main/inc/9S12XDP512asm.s

   1 ;    9S12XDP512asm.h
   2 ;
   3 ;    Copyright 2008, 2009 Sean Keys
   4 ;
   5 ;    This file is part of the FreeEMS project.
   6 ;
   7 ;    FreeEMS software is free software: you can redistribute it and/or modify
   8 ;    it under the terms of the GNU General Public License as published by
   9 ;    the Free Software Foundation, either version 3 of the License, or
  10 ;    (at your option) any later version.
  11 ;
  12 ;    FreeEMS software is distributed in the hope that it will be useful,
  13 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;    GNU General Public License for more details.
  16 ;
  17 ;    You should have received a copy of the GNU General Public License
  18 ;    along with any FreeEMS software.  If not, see http://www.gnu.org/licenses/
  19 ;
  20 ;    We ask that if you make any changes to this file you email them upstream to
  21 ;    us at admin(at)diyefi(dot)org or, even better, fork the code on github.com!
  22 ;
  23 ;    Thank you for choosing FreeEMS to run your engine!
  24
  25 ;    Full basic register definitions for the Freescale S912XDP512 processor
  26 ;    MC9S12XDP512V2.pdf Appendix G
  27
  28 ;* Define the cores of the CPU
  29
  30 .equ PIMcore0,   0x0000  ;ports A, B, E, ; inits, test
  31 .equ MMCcore0,   0x000A  ;Module Mapping Control core section 0 modes
  32 .equ PIMcore1,   0x000C  ;PIMcore section 1 TODO add explaination
  33 .equ EBIcore,    0x000E  ;External Bus Interface
  34 .equ MMCcore1,   0x0010  ;MMC core
  35 .equ MISPCcore,  0x0018  ;Miscellaneous Peripheral Core, Device ID Register
  36 .equ PIMcore2,   0x001C  ;memsiz, IRQ, HPRIO-------------------check with c128 to make sure
  37 .equ DBMcore,    0x0020  ;Debug Module S12XDBG
  38 .equ MMCcore2,   0x0030  ;PPAGE
  39 .equ PIMcore3,   0x0032  ;Port K
  40 .equ CRGcore,    0x0034  ;Clock and Reset Generator
  41 .equ SCI0core,   0x00C8  ;Serial Com Interface 0(RS232 on adapt card)
  42 .equ FCRcore,    0x0100  ;Flash Control Registers
  43 .equ EEPROMcore, 0x0110  ;EEPROM Control Registers
  44 ;-----------------------------------------------------------
  45
  46 ;                  PIMcore0
  47 ;*****************************************************************
  48 .equ PORTA,    PIMcore0+0x00  ;I/O port A 8-bit data register
  49 ;
  50 .equ PTA0,     0b00000001    ;port A bit 0
  51 .equ PTA1,     0b00000010    ;port A bit 1
  52 .equ PTA2,     0b00000100    ;port A bit 2
  53 .equ PTA3,     0b00001000    ;port A bit 3
  54 .equ PTA4,     0b00010000    ;port A bit 4
  55 .equ PTA5,     0b00100000    ;port A bit 5
  56 .equ PTA6,     0b01000000    ;port A bit 6
  57 .equ PTA7,     0b10000000    ;port A bit 7
  58
  59
  60 .equ PORTB,    PIMcore0+0x01  ;I/O port B 8-bit data register
  61 ;
  62 .equ PTB0,     0b00000001    ;port B bit 0
  63 .equ PTB1,     0b00000010    ;port B bit 1
  64 .equ PTB2,     0b00000100    ;port B bit 2
  65 .equ PTB3,     0b00001000    ;port B bit 3
  66 .equ PTB4,     0b00010000    ;port B bit 4
  67 .equ PTB5,     0b00100000    ;port B bit 5
  68 .equ PTB6,     0b01000000    ;port B bit 6
  69 .equ PTB7,     0b10000000    ;port B bit 7
  70
  71 .equ DDRA,     PIMcore0+0x02  ; I/O port A 8-bit data direction register
  72 ;
  73 .equ DDRA0,    0b00000001    ;port A bit 0
  74 .equ DDRA1,    0b00000010    ;port A bit 1
  75 .equ DDRA2,    0b00000100    ;port A bit 2
  76 .equ DDRA3,    0b00001000    ;port A bit 3
  77 .equ DDRA4,    0b00010000    ;port A bit 4
  78 .equ DDRA5,    0b00100000    ;port A bit 5
  79 .equ DDRA6,    0b01000000    ;port A bit 6
  80 .equ DDRA7,    0b10000000    ;port A bit 7
  81
  82 .equ DDRB,    PIMcore0+0x03    ;port B 8-bit date direction register
  83 ;
  84 .equ DDRB0,    0b00000001    ;port B bit 0
  85 .equ DDRB1,    0b00000010    ;port B bit 1
  86 .equ DDRB2,    0b00000100    ;port B bit 2
  87 .equ DDRB3,    0b00001000    ;port B bit 3
  88 .equ DDRB4,    0b00010000    ;port B bit 4
  89 .equ DDRB5,    0b00100000    ;port B bit 5
  90 .equ DDRB6,    0b01000000    ;port B bit 6
  91 .equ DDRB7,    0b10000000    ;port B bit 7
  92
  93 .equ PORTC,    PIMcore0+0x04   ;port C 8-bit data register
  94 ;
  95 .equ PTC0,     0b00000001    ;port C bit 0
  96 .equ PTC1,     0b00000010    ;port C bit 1
  97 .equ PTC2,     0b00000100    ;port C bit 2
  98 .equ PTC3,     0b00001000    ;port C bit 3
  99 .equ PTC4,     0b00010000    ;port C bit 4
 100 .equ PTC5,     0b00100000    ;port C bit 5
 101 .equ PTC6,     0b01000000    ;port C bit 6
 102 .equ PTC7,     0b10000000    ;port C bit 7
 103
 104 .equ PORTD,    PIMcore0+0x05   ;port D 8-bit data regsiter
 105 ;
 106 .equ PTD0,     0b00000001    ;port D bit 0
 107 .equ PTD1,     0b00000010    ;port D bit 1
 108 .equ PTD2,     0b00000100    ;port D bit 2
 109 .equ PTD3,     0b00001000    ;port D bit 3
 110 .equ PTD4,     0b00010000    ;port D bit 4
 111 .equ PTD5,     0b00100000    ;port D bit 5
 112 .equ PTD6,     0b01000000    ;port D bit 6
 113 .equ PTD7,     0b10000000    ;port D bit 7
 114
 115 .equ DDRC,    PIMcore0+0x06  ;port C 8-bit data direction register
 116 ;
 117 .equ DDRC0,    0b00000001    ;port C bit 0
 118 .equ DDRC1,    0b00000010    ;port C bit 1
 119 .equ DDRC2,    0b00000100    ;port C bit 2
 120 .equ DDRC3,    0b00001000    ;port C bit 3
 121 .equ DDRC4,    0b00010000    ;port C bit 4
 122 .equ DDRC5,    0b00100000    ;port C bit 5
 123 .equ DDRC6,    0b01000000    ;port C bit 6
 124 .equ DDRC7,    0b10000000    ;port C bit 7
 125
 126 .equ DDRD,    PIMcore0+0x07  ;port D 8-bit data direction register
 127 ;
 128 .equ DDRD0,    0b00000001    ;port D bit 0
 129 .equ DDRD1,    0b00000010    ;port D bit 1
 130 .equ DDRD2,    0b00000100    ;port D bit 2
 131 .equ DDRD3,    0b00001000    ;port D bit 3
 132 .equ DDRD4,    0b00010000    ;port D bit 4
 133 .equ DDRD5,    0b00100000    ;port D bit 5
 134 .equ DDRD6,    0b01000000    ;port D bit 6
 135 .equ DDRD7,    0b10000000    ;port D bit 7
 136
 137 .equ PORTE,   PIMcore0+0x08  ;port E 8-bit data regsiter
 138 ;
 139 .equ PTE0,     0b00000001    ;port E bit 0 ;also see appendix
 140 .equ PTE1,     0b00000010    ;port E bit 1 ;also see appendix
 141 .equ PTE2,     0b00000100    ;port E bit 2
 142 .equ PTE3,     0b00001000    ;port E bit 3
 143 .equ PTE4,     0b00010000    ;port E bit 4
 144 .equ PTE5,     0b00100000    ;port E bit 5
 145 .equ PTE6,     0b01000000    ;port E bit 6
 146 .equ PTE7,     0b10000000    ;port E bit 7
 147
 148
 149 .equ DDRE,   PIMcore0+0x09   ;port E 8-bit data direction register
 150 ;
 151 .equ DDRE0,    0b00000001    ;port E bit 0 ;also see appendix
 152 .equ DDRE1,    0b00000010    ;port E bit 1 ;also see appendix
 153 .equ DDRE2,    0b00000100    ;port E bit 2
 154 .equ DDRE3,    0b00001000    ;port E bit 3
 155 .equ DDRE4,    0b00010000    ;port E bit 4
 156 .equ DDRE5,    0b00100000    ;port E bit 5
 157 .equ DDRE6,    0b01000000    ;port E bit 6
 158 .equ DDRE7,    0b10000000    ;port E bit 7
 159
 160 ;                     MMCcore0
 161 ;****************************************************************
 162 .equ MMCCTLo,MMCcore0+0x00 ;mmctrlo TODO add brief explaination
 163 ;
 164 .equ CS0E,     0b00000001    ;mmctlo bit 0
 165 .equ CS1E,     0b00000010    ;mmctlo bit 1
 166 .equ CS2E,     0b00000100    ;mmctlo bit 2
 167 ;                            ;reserved
 168 ;                            ;reserved
 169 ;                            ;reserved
 170 ;                            ;reserved
 171 ;                            ;reserved
 172
 173 .equ MODE,   MMCcore0+0x01 ;MODE bits
 174 ;
 175 ;                            ;reserved
 176 ;                            ;reserved
 177 ;                            ;reserved
 178 ;                            ;reserved
 179 ;                            ;reserved
 180 .equ MODA,     0b00100000    ;mode bit  A
 181 .equ MODB,     0b01000000    ;mode bit  B
 182 .equ MODC,     0b10000000    ;mode bit  C
 183
 184 ;                         PIMcore1
 185 ;*************************************************************************
 186 .equ PUCR,   PIMcore1+0x00 ;Pull Up Controll Register
 187 ;
 188 .equ PUPAE,    0b00000001    ;pucr A bit enable
 189 .equ PUPBE,    0b00000010    ;pucr B bit enable
 190 .equ PUPCE,    0b00000100    ;pucr C bit enable
 191 .equ PUPDE,    0b00001000    ;pucr D bit enable
 192 .equ PUPEE,    0b00010000    ;pucr E bit enable
 193 ;                            ;reserved
 194 .equ BKPUE,    0b01000000    ;pucr bit 6 TODO add exp
 195 .equ PUPKE,    0b10000000    ;pucr bit 7 TODO add exp
 196
 197 .equ RDRIV,  PIMcore1+0x01 ;rdriv TODO add exp
 198 ;
 199 .equ RDPA,     0b00000001    ;rdriv A bit
 200 .equ RDPB,     0b00000010    ;rdriv B bit
 201 .equ RDPC,     0b00000100    ;rdriv C bit
 202 .equ RDPD,     0b00001000    ;rdriv D bit
 203 .equ RDPE,     0b00010000    ;rdriv E bit
 204 ;                            ;reserved
 205 ;                            ;reserved
 206 .equ RDPK,     0b10000000    ;rdriv bit 7 TODO add exp
 207
 208 ;                         EBIcore
 209 ;*****************************************************************
 210 .equ EBICTRL0, EBIcore+0x00 ;EBI TODO add exp
 211 ;
 212 .equ ASIZ0,    0b00000001    ;ebictrl0 bit 0
 213 .equ ASIZ1,    0b00000010    ;ebictrl0 bit 1
 214 .equ ASIZ2,    0b00000100    ;ebictrl0 bit 2
 215 .equ ASIZ3,    0b00001000    ;ebictrl0 bit 3
 216 .equ ASIZ4,    0b00010000    ;ebictrl0 bit 4
 217 .equ HDBE,     0b00100000    ;ebictrl0 bit 5
 218 ;                            ;bit 6 reserved
 219 .equ ITHRS,    0b10000000    ;ebictrl0 bit 7
 220
 221 .equ EBICTRL1, EBIcore+0x01  ;ebictrl 1  TODO add brief explaination
 222 ;
 223 .equ EXSTR0,   0b00000001    ;ebictrl1 bit 0
 224 .equ EXSTR1,   0b00000010    ;ebictrl1 bit 1
 225 .equ EXSTR2,   0b00000100    ;ebictrl1 bit 2
 226 ;                            ;reserved
 227 ;                            ;reserved
 228 ;                            ;reserved
 229 ;                            ;reserved
 230 .equ EWAITE,   0b10000000    ;ebictrl1 bit 7
 231
 232 ;                     MMCcore1
 233 ;*****************************************************************
 234 .equ GPAGE,  MMCcore1+0x00 ;mmcore1 GPAGE
 235 ;
 236 .equ GP0,      0b00000001    ;gpage bit 0
 237 .equ GP1,      0b00000010    ;gpage bit 1
 238 .equ GP2,      0b00000100    ;gpage bit 2
 239 .equ GP3,      0b00001000    ;gpage bit 3
 240 .equ GP4,      0b00010000    ;gpage bit 4
 241 .equ GP5,      0b00100000    ;gpage bit 5
 242 .equ GP6,      0b01000000    ;gpage bit 6
 243 ;                            ;reserved
 244
 245 .equ DIRECT, MMCcore1+0x01   ;mmcore1 direct
 246 ;
 247 .equ DP8,      0b00000001   ;direct bit 0
 248 .equ DP9,      0b00000010   ;direct bit 1
 249 .equ DP10,     0b00000100   ;direct bit 2
 250 .equ DP11,     0b00001000   ;direct bit 3
 251 .equ DP12,     0b00010000   ;direct bit 4
 252 .equ DP13,     0b00100000   ;direct bit 5
 253 .equ DP14,     0b01000000   ;direct bit 6
 254 .equ DP15,     0b10000000   ;direct bit 7
 255
 256 ;             MMCcore1+0x02        ;reserved
 257
 258 .equ MMCCTL1, MMCcore1+0x03 ;MMCTL1 bits TODO add exp
 259 ;
 260 .equ ROMON,    0b00000001   ; MMCTL1 bit 0
 261 .equ ROMHM,    0b00000010   ; MMCTL1 bit 1
 262 .equ EROMON,   0b00000100   ; MMCTL1 bit 2
 263 ;                           ;reserved
 264 ;                           ;reserved
 265 ;                           ;reserved
 266 ;                           ;reserved
 267 ;                           ;reserved
 268 ;                           ;reserved
 269
 270 ;             MMCcore1+0x04;reserved
 271 ;             MMCcore1+0x05;reserved
 272
 273 .equ RPAGE,   MMCcore1+0x06 ; rpage bits
 274 ;
 275 .equ RP0,      0b00000001   ;rpage bit 0
 276 .equ RP1,      0b00000010   ;rpage bit 1
 277 .equ RP2,      0b00000100   ;rpage bit 2
 278 .equ RP3,      0b00001000   ;rpage bit 3
 279 .equ RP4,      0b00010000   ;rpage bit 4
 280 .equ RP5,      0b00100000   ;rpage bit 5
 281 .equ RP6,      0b01000000   ;rpage bit 6
 282 .equ RP7,      0b10000000   ;rpage bit 7
 283
 284 .equ EPAGE,   MMCcore1+0x07  ; epage bits
 285 ;
 286 .equ EP0,      0b00000001    ;epage bit 0
 287 .equ EP1,      0b00000010    ;epage bit 1
 288 .equ EP2,      0b00000100    ;epage bit 2
 289 .equ EP3,      0b00001000    ;epage bit 3
 290 .equ EP4,      0b00010000    ;epage bit 4
 291 .equ EP5,      0b00100000    ;epage bit 5
 292 .equ EP6,      0b01000000    ;epage bit 6
 293 .equ EP7,      0b10000000    ;epage bit 7
 294
 295 ;                        MISPcore
 296 ;**********************************************************
 297 ;              MISPCcore+0x00;reserved
 298 ;              MISPCcore+0x01;reserved
 299
 300
 301 .equ PARTIDH,   MISPCcore+0x02   ;device ID high register
 302 .equ PARTIDL,   MISCPcore+0x03   ;device ID low register
 303
 304 ;                        PIMcore2
 305 ;**********************************************************
 306 .equ ECLKCTL,  PIMcore2+0x00  ;  todo add exp
 307 ;
 308 .equ EDIV0,    0b00000001     ;ECLKCTL bit 0
 309 .equ EDIV1,    0b00000010     ;ECLKCTL bit 1
 310 ;                             ;reserved
 311 ;                             ;reserved
 312 ;                             ;reserved
 313 ;                             ;reserved
 314 .equ NCLKX2,   0b01000000     ;ECLKCTL bit 6
 315 .equ NECLK,    0b10000000     ;ECLKCTL bit 7
 316
 317 ;              PIMcore2+0x01  ;reserved
 318
 319 .equ IRQCR,    PIMcore2+0x02  ;add explain.
 320 ;
 321 .equ IRQN,     0b01000000     ;IRQCR bit 6
 322 .equ IRQE,     0b10000000     ;IRQCR bit 7
 323 ;                             ;reserved
 324 ;                             ;reserved
 325 ;                             ;reserved
 326 ;                             ;reserved
 327 ;                             ;reserved
 328 ;                             ;reserved
 329
 330 ;               PIMcore2+0x03 ;reserved
 331
 332 ;                             DBMcore
 333 ;*********************************************************
 334 ;DBGXCTL  represents the contents if the Comparator A or C
 335 ;  control register is blended into this address
 336 ;DBGXCTL  represents the contents if the comparator B or D
 337 ;  control register is blended into this address
 338 ;*********************************************************
 339
 340 .equ DBGC1,   DBMcore+0x00    ;Debug control register 1
 341 ;
 342 .equ COMRV,    0b00000011     ;
 343 ;
 344 .equ DBGBRK,   0b00001100     ;
 345 ;
 346 .equ BDM,      0b00010000     ;
 347 .equ XGSBPE,   0b00100000     ;
 348 .equ TRIG,     0b01000000     ;
 349 .equ ARM,      0b10000000     ;
 350
 351 .equ DBGSR,   DBMcore+0x01  ;debug status register
 352 ;
 353 .equ SSF0,     0b00000001     ;
 354 .equ SSF1,     0b00000010     ;
 355 .equ SSF2,     0b00000100     ;
 356 ;                             ;reserved
 357 ;                             ;reserved
 358 ;                             ;reserved
 359
 360 .equ EXTF,     0b01000000     ;
 361 .equ TBF,      0b10000000     ;
 362
 363 .equ DBGTCR,  DBMcore+0x02   ;
 364 ;
 365 .equ TALIGN,   0b00000011    ;
 366 ;
 367 .equ TRCMOD,   0b00001100    ;
 368 ;
 369 .equ TRANGE,   0b00110000    ;
 370 ;
 371 .equ TSOURCE,  0b11000000    ;
 372 ;
 373
 374 .equ DBGC2,   DBMcore+0x03  ;
 375 ;
 376 .equ ABCM,     0b00000011    ;
 377 ;
 378 .equ CDCM,     0b00001100    ;
 379 ;
 380 ;                            ;reserved
 381 ;                            ;reserved
 382 ;                            ;reserved
 383 ;                            ;reserved
 384
 385 .equ DBGTBH,   DBMcore+0x04   ;debug trace buffer high register (bits 8-15)
 386
 387 .equ DBGTBL,   DBMcore+0x05   ;debug trace buffer low register (bits 0-7)
 388
 389 .equ DBGCNT,   DBMcore+0x06   ;debug count regsiter bits 0-6  bit 7 reserved
 390 ;
 391 .equ CNT,      0b011111111    ;
 392
 393 .equ DBGSCRX,  DBMcore+0x07   ;debug comparator c expansion register
 394 ;
 395 .equ SC0,       0b00000001    ;SCO bit
 396 .equ SC1,       0b00000010    ;SC1 bit
 397 .equ SC2,       0b00000100    ;SC2 bit
 398 .equ SC3,       0b00001000    ;SC3 bit
 399 ;                             ;reserved
 400 ;                             ;reserved
 401 ;                             ;reserved
 402 ;                             ;reserved
 403
 404 .equ DBGXCTL,  DBMcore+0x08   ;IF COMPARITOR A or C CONTROL REGISTER IS BLENDED INTO THIS ADDRESS(DEFAULT)
 405 ;
 406 .equ COMPE,     0b00000001    ;
 407 .equ SRC,       0b00000010    ;
 408 .equ RWE,       0b00000100    ;
 409 .equ RW,        0b00001000    ;
 410 .equ BRK,       0b00010000    ;
 411 .equ TAG,       0b00100000    ;
 412 .equ NDB,       0b01000000    ;
 413 ;                             ;reserved
 414
 415 ;.equ DBGXCTL,  DBMcore+0x08   ;IF COMPARITOR B or D CONTROL REGISTER IS BLENDED INTO THE ADDRESS
 416 ;
 417 ;.equ COMPE,     0b00000001    ;
 418 ;.equ SRC,       0b00000010    ;
 419 ;.equ RWE,       0b00000100    ;
 420 ;.equ RW,        0b00001000    ;
 421 ;.equ BRK,       0b00010000    ;
 422 ;.equ TAG,       0b00100000    ;
 423 ;.equ SZ,        0b01000000    ;
 424 ;.equ SZE,       0b10000000    ;reserved
 425
 426 .equ DBGXAH,    DBMcore+0x09  ;TODO add exp
 427
 428 .equ DBGXAM,    DBMcore+0x0A  ;TODO add exp
 429
 430 .equ DBGXAL,    DBMcore+0x0B  ;TODO add exp
 431
 432 .equ DBGXDH,    DBMcore+0x0C  ;TODO add exp
 433
 434 .equ DBGXDL,    DBMcore+0x0D  ;TODO add exp
 435
 436 .equ DBGXDHM,   DBMcore+0x0E  ;TODO add exp
 437
 438 .equ DBGXDLM,   DBMcore+0x0F  ;TODO add exp
 439
 440 .equ PPAGE,    MMCcore2+0x00   ;TODO add exp
 441 ;
 442 .equ PIX0,       0b00000001   ;PIX bit 0
 443 .equ PIX1,       0b00000010   ;PIX bit 1
 444 .equ PIX2,       0b00000100   ;PIX bit 2
 445 .equ PIX3,       0b00001000   ;PIX bit 3
 446 .equ PIX4,       0b00010000   ;PIX bit 4
 447 .equ PIX5,       0b00100000   ;PIX bit 5
 448 .equ PIX6,       0b01000000   ;PIX bit 6
 449 .equ PIX7,       0b10000000   ;PIX bit 7
 450
 451 ;                             ;reserved
 452
 453 .equ PORTK,   PIMcore3+0x00   ; Port K
 454 ;
 455 .equ PTK0,       0b00000001   ;port k bit 0
 456 .equ PTK1,       0b00000010   ;port k bit 1
 457 .equ PTK2,       0b00000100   ;port k bit 2
 458 .equ PTK3,       0b00001000   ;port k bit 3
 459 .equ PTK4,       0b00010000   ;port k bit 4
 460 .equ PTK5,       0b00100000   ;port k bit 5
 461 .equ PTK6,       0b01000000   ;port k bit 6
 462 .equ PTK7,       0b10000000   ;port k bit 7
 463
 464 .equ DDRK,    PIMcore3+01     ;port k data direction register
 465 ;
 466 .equ DDRK0,      0b00000001   ;port k data direction register bit 0
 467 .equ DDRK1,      0b00000010   ;port k data direction register bit 1
 468 .equ DDRK2,      0b00000100   ;port k data direction register bit 2
 469 .equ DDRK3,      0b00001000   ;port k data direction register bit 3
 470 .equ DDRK4,      0b00010000   ;port k data direction register bit 4
 471 .equ DDRK5,      0b00100000   ;port k data direction register bit 5
 472 .equ DDRK6,      0b01000000   ;port k data direction register bit 6
 473 .equ DDRK7,      0b10000000   ;port k data direction register bit 7
 474
 475 .equ SYNR,    CRGcore+0x00    ;CRG synthesizer register
 476 ;
 477 .equ SYN0,       0b00000001   ;CRG synthesizer register 0
 478 .equ SYN1,       0b00000010   ;CRG synthesizer register 1
 479 .equ SYN2,       0b00000100   ;CRG synthesizer register 2
 480 .equ SYN3,       0b00001000   ;CRG synthesizer register 3
 481 .equ SYN4,       0b00010000   ;CRG synthesizer register 4
 482 .equ SYN5,       0b00100000   ;CRG synthesizer register 5
 483 ;                             ;reserved
 484 ;                             ;reserved
 485
 486 .equ REFDV,   CRGcore+0x01    ;CRG reference divider register
 487 ;
 488 .equ REFDV0,     0b00000001   ;CRG reference divider register bit 0
 489 .equ REFDV1,     0b00000010   ;CRG reference divider register bit 2
 490 .equ REFDV2,     0b00000100   ;CRG reference divider register bit 3
 491 .equ REFDV3,     0b00001000   ;CRG reference divider register bit 4
 492 .equ REFDV4,     0b00010000   ;CRG reference divider register bit 5
 493 ;                             ;reserved
 494 ;                             ;reserved
 495
 496 ;.equ CTFLG,  CRGcore+0x02    ;reserved for factory test
 497
 498 .equ CRGFLG,  CRGcore+0x03    ;CRG flags register
 499 ;
 500 .equ SCM,        0b00000001   ;CRG SCM bit
 501 .equ SCMIF,      0b00000010   ;CRG SCMIF bit
 502 .equ TRACK,      0b00000100   ;CRG TRACK bit
 503 .equ LOCK,       0b00001000   ;CRG LOCK bit
 504 .equ LOCKIF,     0b00010000   ;CRG LOCKIF bit
 505 .equ LVRF,       0b00100000   ;CRG LVRF bit
 506 .equ PORF,       0b01000000   ;CRG PORF bit
 507 .equ RTIF,       0b10000000   ;CRG RTIF bit
 508
 509 .equ CRGINT,  CRGcore+0x04    ;CRGINT
 510 ;
 511 ;                             ;reserved
 512 .equ SCMIE,      0b00000010   ;CRGINT SCMIE bit
 513 ;                             ;reserved
 514 ;                             ;reserved
 515 .equ LOCKIE,     0b00010000   ;CRGINT LOCKIE bit
 516 ;                             ;reserved
 517 ;                             ;reserved
 518 .equ ILAF,       0b01000000   ;CRGINT ILAF bit
 519 .equ RTIE,       0b10000000   ;CRGINT RTIE bit
 520
 521 .equ CLKSEL,  CRGcore+0x05    ;CRG clock select register
 522 ;
 523 .equ COPWAI,     0b00000001   ;CLKSEL COPWAI register
 524 .equ RTIWAI,     0b00000010   ;CLKSEL RTIWAI register
 525 ;                             ;reserved
 526 .equ PLLWAI,     0b00000100   ;CLKSEL PLLWAI register
 527 ;                             ;reserved
 528 ;                             ;reserved
 529 .equ PSTP,       0b01000000   ;CLKSEL PST register
 530 .equ PLLSEL,     0b10000000   ;CLKSEL PLLSEL register
 531
 532 .equ PLLCTL,  CRGcore+0x06    ;CRG PLL control register
 533 ;
 534 .equ SCME,       0b00000001   ;PLLCTL SCME bit
 535 .equ PCE,        0b00000010   ;PLLCTL PCE bit
 536 .equ PRE,        0b00000100   ;PLLCTL PRE bit
 537 .equ FSTWKP,     0b00001000   ;PLLCTL FSTWKP bit
 538 .equ ACQ,        0b00010000   ;PLLCTL ACQ bit
 539 .equ AUTO,       0b00100000   ;PLLCTL AUTO bit
 540 .equ PLLON,      0b01000000   ;PLLCTL PLLON bit
 541 .equ CME,        0b10000000   ;PLLCTL CME bit
 542
 543 .equ RTICTL,  CRGcore+0x07    ;RTICTL
 544 ;
 545 .equ RTR0,       0b00000001   ;RTICTL RTR0 bit
 546 .equ RTR1,       0b00000010   ;RTICTL RTR1 bit
 547 .equ RTR2,       0b00000100   ;RTICTL RTR2 bit
 548 .equ RTR3,       0b00001000   ;RTICTL RTR3 bit
 549 .equ RTR4,       0b00010000   ;RTICTL RTR4 bit
 550 .equ RTR5,       0b00100000   ;RTICTL RTR5 bit
 551 .equ RTR6,       0b01000000   ;RTICTL RTR6 bit
 552 .equ RTDEC,      0b10000000   ;RTICTL RTDEC bit
 553
 554 .equ COPCTL,  CRGcore+0x08    ;COP control register
 555 ;
 556 .equ CR0,        0b00000001   ;COP watchdog timer rate select
 557 .equ CR1,        0b00000010   ;COP watchdog timer rate select
 558 .equ CR2,        0b00000100   ;COP watchdog timer rate select
 559 ;                             ;reserved
 560 ;                             ;reserved
 561 ;                             ;reserved
 562 .equ RSBCK,      0b01000000   ;COP and RTI stop in active BDM mode bit
 563 .equ WCOP,       0b10000000   ;TODO add def
 564
 565 ;.equ FORBYP, CRGcore+0x09    ;reserved for factory test
 566
 567 ;.equ CTCL,   CRGcore+0x0A    ;reserved for factory test
 568
 569 .equ ARMCOP,  CRGcore+0x0B    ;CRG COP arm/timer reset register
 570
 571 ;                       SCI0
 572 ;************************************************************************
 573 ;SCI0BDH/SCI0BDL/SCI0BDL registers are accessable if the AMAP bit in the
 574 ;    SCI0SR2 register is set to ZERO
 575 ;SCI0ASR1/SCIACR1/SCI0ACR2 registers are accessible if the AMAP bit in
 576 ;    the SCI0SR2 register is set to ONE
 577 ;
 578 ;************************************************************************
 579 .equ SCI0BDH, SCI0core+0x00  ;SCI0 baud rate registers (8-12 bits)
 580 ; f (as in first) added as prefix so names dont conflict with other SCIs
 581 .equ fSBR8,      0b00000001   ;
 582 .equ fSBR9,      0b00000010   ;
 583 .equ fSBR10,     0b00000100   ;
 584 .equ fSBR11,     0b00001000   ;
 585 .equ fSBR12,     0b00010000   ;
 586 .equ fTNP0,      0b00100000   ;
 587 .equ fTNP1,      0b01000000   ;
 588 .equ fIREN,      0b10000000   ;
 589
 590 .equ SCI0BDL, SCI0core0+0x01 ;SCI baud rate registers (0-7 bits)
 591 ; f (as in first) added as prefix so names dont conflict with other SCIs
 592 .equ fSBR0,      0b00000001   ;
 593 .equ fSBR1,      0b00000010   ;
 594 .equ fSBR2,      0b00000100   ;
 595 .equ fSBR3,      0b00001000   ;
 596 .equ fSBR4,      0b00010000   ;
 597 .equ fSBR5,      0b00100000   ;
 598 .equ fSBR6,      0b01000000   ;
 599 .equ fSBR7,      0b10000000   ;
 600
 601 .equ SCI0CR1,  SCI0core+0x02  ;SCI0 control register 1
 602 ; f (as in first) added as prefix so names dont conflict with other SCIs
 603 .equ fPT,        0b00000001   ;
 604 .equ fPE,        0b00000010   ;
 605 .equ fILT,       0b00000100   ;
 606 .equ fWAKE,      0b00001000   ;
 607 .equ fM,         0b00010000   ;
 608 .equ fRSRC,      0b00100000   ;
 609 .equ fSCSIWAI,   0b01000000   ;
 610 .equ fLOOPS,     0b10000000   ;
 611
 612 .equ SCI0ASR1,  SCI0core+0x03  ;SCI0 status register
 613 ; f (as in first) added as prefix so names dont conflict with other SCIs
 614 .equ fBKDIF,     0b00000001   ;
 615 .equ fBERRIF,    0b00000011   ;
 616 .equ fBERRV,     0b00000100   ;
 617 ;                             ;reserved
 618 ;                             ;reserved
 619 ;                             ;reserved
 620 ;                             ;reserved
 621 .equ fRXEDGIF,   0b10000000   ;
 622
 623 .equ SCI0ACR1,  SCI0core+0x04  ;
 624 ; f (as in first) added as prefix so names dont conflict with other SCIs
 625 .equ fBKDIE,     0b00000001   ;
 626 .equ fBERRIE,    0b00000010   ;
 627 ;                             ;reserved
 628 ;                             ;reserved
 629 ;                             ;reserved
 630 ;                             ;reserved
 631 ;                             ;reserved
 632 .equ RXEDGIE,    0b10000000   ;
 633
 634 .equ SCI0ACR2,  SCI0core+0x05  ;
 635 ; f (as in first) added as prefix so names dont conflict with other SCIs
 636 .equ fBKDFE,     0b00000001   ;
 637 .equ fBERRMO,    0b00000010   ;
 638 .equ fBERMM1,    0b00000100   ;
 639 ;                             ;reserved
 640 ;                             ;reserved
 641 ;                             ;reserved
 642 ;                             ;reserved
 643 ;                             ;reserved
 644
 645 .equ SCI0CR2,   SCI0core+0x06  ;
 646 ; f (as in first) added as prefix so names dont conflict with other SCIs
 647 .equ fSBK,       0b00000001   ;
 648 .equ fRWU,       0b00000010   ;
 649 .equ fRE,        0b00000100   ;
 650 .equ fTE,        0b00001000   ;
 651 .equ fILIE,      0b00010000   ;
 652 .equ fRIE,       0b00100000   ;
 653 .equ fTCIE,      0b01000000   ;
 654 .equ fTIE,       0b10000000   ;
 655
 656 .equ SCI0SR1,   SCI0core+0x07  ;
 657 ; f (as in first) added as prefix so names dont conflict with other SCIs
 658 .equ fPF,        0b00000001   ;
 659 .equ fFE,        0b00000010   ;
 660 .equ fNF,        0b00000100   ;
 661 .equ fOR,        0b00001000   ;
 662 .equ fIDLE,      0b00010000   ;
 663 .equ fRDRF,      0b00100000   ;
 664 .equ fTC,        0b01000000   ;
 665 .equ fTDRE,      0b10000000   ;
 666
 667 .equ SCI0SR2,  SCI0core+0x08   ;
 668 ; f (as in first) added as prefix so names dont conflict with other SCIs
 669 .equ fRAF,       0b00000001   ;
 670 .equ fTXDIR,     0b00000010   ;
 671 .equ fBRK13,     0b00000100   ;
 672 .equ fRXPOL,     0b00001000   ;
 673 .equ fTXPOL,     0b00010000   ;
 674 ;                             ;reserved
 675 ;                             ;reserved
 676 .equ fAMAP,      0b10000000   ;
 677
 678 .equ SCI0DRH,  SCI0core+0x09   ;
 679 ; f (as in first) added as prefix so names dont conflict with other SCIs
 680 ;                             ;reserved
 681 ;                             ;reserved
 682 ;                             ;reserved
 683 ;                             ;reserved
 684 ;                             ;reserved
 685 ;                             ;reserved
 686 .equ fT8,        0b01000000   ;
 687 .equ fR8,        0b10000000   ;
 688
 689 .equ SCI0DRL,  SCI0core+0x0A  ;
 690 ; f (as in first) added as prefix so names dont conflict with other SCIs
 691 .equ fR0,        0b00000001   ;
 692 .equ fR1,        0b00000010   ;
 693 .equ fR2,        0b00000100   ;
 694 .equ fR3,        0b00001000   ;
 695 .equ fR4,        0b00010000   ;
 696 .equ fR5,        0b00100000   ;
 697 .equ fR6,        0b01000000   ;
 698 .equ fR7,        0b10000000   ;
 699 ;
 700 .equ fT0,        0b00000001   ;
 701 .equ fT1,        0b00000010   ;
 702 .equ fT2,        0b00000100   ;
 703 .equ fT3,        0b00001000   ;
 704 .equ fT4,        0b00010000   ;
 705 .equ fT5,        0b00100000   ;
 706 .equ fT6,        0b01000000   ;
 707 .equ fT7,        0b10000000   ;
 708
 709 ;                         FCRcore
 710 ;**********************************************************
 711
 712 .equ FCLKDIV,  FCRcore+0x00   ;Flash clock divide register
 713 ;
 714 .equ FDIV0,      0b00000001   ;
 715 .equ FDIV1,      0b00000010   ;
 716 .equ FDIV2,      0b00000100   ;
 717 .equ FDIV3,      0b00001000   ;
 718 .equ FDIV4,      0b00010000   ;
 719 .equ FDIV5,      0b00100000   ;
 720 .equ PRDIV,      0b01000000   ;
 721 .equ FDIVLD,     0b10000000   ;
 722
 723 .equ FSEC,    FCRcore+0x01    ;Flash Security Revister
 724 ;
 725 .equ SEC0,       0b00000001   ;
 726 .equ SEC1,       0b00000010   ;
 727 .equ RNV2,       0b00000100   ;
 728 .equ RNV3,       0b00001000   ;
 729 .equ RNV4,       0b00010000   ;
 730 .equ RNV5,       0b00100000   ;
 731 .equ KEYEN0,     0b01000000   ;
 732 .equ KEYEN1,     0b10000000   ;
 733
 734 .equ FTSTMOD, FCRcore+0x02    ;
 735 ;
 736 ;                             ;reserved
 737 ;                             ;reserved
 738 ;                             ;reserved
 739 ;                             ;reserved
 740 .equ WRALL,      0b00010000   ;
 741 .equ MRDS,       0b01100000   ;
 742 ;                             ;reserved
 743
 744 .equ FCNFG,   FCRcore+0x03    ;
 745 ;
 746 ;                             ;reserved
 747 ;                             ;reserved
 748 ;                             ;reserved
 749 ;                             ;reserved
 750 ;                             ;reserved
 751 .equ KEYACC,     0b00100000   ;
 752 .equ CCIE,       0b01000000   ;
 753 .equ CBEIE,      0b10000000   ;
 754
 755 .equ FPROT,   FCRcore+0x04    ;
 756 ;
 757 .equ FPLS0,      0b00000001   ;
 758 .equ FPLS1,      0b00000010   ;
 759 .equ FPLDIS,     0b00000100   ;
 760 .equ FPHS0,      0b00001000   ;
 761 .equ FPHS1,      0b00010000   ;
 762 .equ FPHSDIS,    0b00100000   ;
 763 .equ RNV6,       0b01000000   ;
 764 .equ FPOPEN,     0b10000000   ;
 765
 766 .equ FSTAT,   FCRcore+0x05    ;
 767 ;
 768 ;                             ;reserved
 769 ;                             ;reserved
 770 .equ BLANK,      0b00000100   ;
 771 ;                             ;reserved
 772 .equ ACCERR,     0b00010000   ;flash access error
 773 .equ PVIOL,      0b00100000   ;protection violation
 774 .equ CCIF,       0b01000000   ;command complete interrypt flag
 775 .equ CBEIF,      0b10000000   ;command buffer empty mode commands
 776
 777 .equ FCMD,   FCRcore+0x06     ;flash command register
 778 ;
 779 .equ CMDB0,      0b00000001   ;
 780 .equ CMDB1,      0b00000010   ;
 781 .equ CMDB2,      0b00000100   ;
 782 .equ CMDB3,      0b00001000   ;
 783 .equ CMDB4,      0b00010000   ;
 784 .equ CMDB5,      0b00100000   ;
 785 .equ CMDB6,      0b01000000   ;
 786 ;                             ;reserved
 787
 788 .equ ClearMass,     CMDB6+CMDB0  ;
 789 .equ ClearSection,  CMDB6        ;
 790 .equ WriteWord,     CMDB5        ;
 791
 792 .equ FCTL,   FCRcore+0x07    ;
 793 ;
 794 .equ NV0,        0b00000001   ;
 795 .equ NV1,        0b00000010   ;
 796 .equ NV2,        0b00000100   ;
 797 .equ NV3,        0b00001000   ;
 798 .equ NV4,        0b00010000   ;
 799 .equ NV5,        0b00100000   ;
 800 .equ NV6,        0b01000000   ;
 801 .equ NV7,        0b10000000   ;
 802
 803 .equ FADDRHI, FCRcore+0x08    ; bits 0-7
 804
 805 .equ FADDRLO, FCRcore+0x09    ;bits 0-7
 806
 807 .equ FDATAHI, FCRcore+0x0A    ;bits 0-7
 808
 809 .equ FDATALO, FCRcore+0x0B    ;bits 0-7
 810
 811 ; FCRcore+0x0C-0x0F reserved
 812
 813 ;                 EEPROM
 814 ;*******************************************************
 815
 816 .equ ECLKDIV,  EEPROMcore+0x00  ;EEPROM clock divide register
 817 ;
 818 .equ EDIV0,      0b00000001     ;
 819 .equ EDIV1,      0b00000010     ;
 820 .equ EDIV2,      0b00000100     ;
 821 .equ EDIV3,      0b00001000     ;
 822 .equ EDIV4,      0b00010000     ;
 823 .equ EDIV5,      0b00100000     ;
 824 .equ PRDIV8,     0b01000000     ;
 825 .equ EDIVLD,     0b10000000     ;
 826
 827 ;     EEPROMcore+0x01 reserved
 828
 829 ;     EEPROMcore+0x02 reserved
 830
 831 .equ ECNFG,  EEPROMcore+0x03     ;EEPROM configuration register
 832 ;
 833 ;                                ;reserved
 834 ;                                ;reserved
 835 ;                                ;reserved
 836 ;                                ;reserved
 837 ;                                ;reserved
 838 ;                                ;reserved
 839 .equ CCIER,      0b01000000      ;
 840 .equ CBEIER,     0b10000000      ;
 841
 842 .equ EPROT,  EEPROMcore+0x04     ;
 843 ;
 844 .equ EPS0,       0b00000001      ;
 845 .equ EPS1,       0b00000010      ;
 846 .equ EPS2,       0b00000100      ;
 847 .equ EPDIS,      0b00001000      ;
 848 .equ RNV4,       0b00010000      ;
 849 .equ RNV5,       0b00100000      ;
 850 .equ RNV6,       0b01000000      ;
 851 .equ EPOPEN,     0b10000000      ;
 852
 853 .equ ESTAT,  EEPROMcore+0x05     ;EEPROM status register
 854 ;
 855 ;                                ;reserved
 856 ;                                ;reserved
 857 .equ BLANKR,      0b00000100     ;
 858 ;                                ;reserved
 859 .equ ACCERRR,     0b00010000     ;
 860 .equ PVIOLR,      0b00100000     ;
 861 .equ CCIFR,       0b01000000     ;
 862 .equ CBEIFR,      0b10000000     ;
 863
 864 .equ ECMD,   EEPROMcore+0x06     ;EEPROM command buffer and register
 865 ;
 866 .equ CMDB0R,      0b00000001     ;
 867 .equ CMDB1R,      0b00000010     ;
 868 .equ CMDB2R,      0b00000100     ;
 869 .equ CMDB3R,      0b00001000     ;
 870 .equ CMDB4R,      0b00010000     ;
 871 .equ CMDB5R,      0b00100000     ;
 872 .equ CMDB6R,      0b01000000     ;
 873 ;                                ;reserved
 874
 875 ;            EEPROMcore+0x07  reserved
 876
 877 .equ EADDRHI, EEPROMcore+0x08    ;
 878 ;
 879 .equ EABHI,       0b00000111     ;
 880 ;                                ;bits 3-7 reserved
 881
 882 .equ EADDRLO, EEPROMcore+0x09    ;
 883 ;
 884 .equ EABLO,       0b11111111     ;
 885
 886 .equ EDATAHI, EEPROMcore+0x0A    ;
 887 ;
 888 .equ EDHI,        0b11111111     ;
 889
 890 .equ EDATALO, EEPROMcore+0x0B    ;
 891 ;
 892 .equ EDLO,        0b11111111     ;