src/main/inc/9S12XDP512asm.s

   1 ;    9S12XDP512asm.h
   2 ;
   3 ;    Copyright 2008-2009 Fred Cooke
   4 ;
   5 ;    This file is part of the FreeEMS project.
   6 ;
   7 ;    FreeEMS software is free software: you can redistribute it and/or modify
   8 ;    it under the terms of the GNU General Public License as published by
   9 ;    the Free Software Foundation, either version 3 of the License, or
  10 ;    (at your option) any later version.
  11 ;
  12 ;    FreeEMS software is distributed in the hope that it will be useful,
  13 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;    GNU General Public License for more details.
  16 ;
  17 ;    You should have received a copy of the GNU General Public License
  18 ;    along with any FreeEMS software.  If not, see http://www.gnu.org/licenses/
  19 ;
  20 ;    We ask that if you make any changes to this file you email them upstream to
  21 ;    us at admin(at)diyefi(dot)org or, even better, fork the code on github.com!
  22 ;
  23 ;    Thank you for choosing FreeEMS to run your engine!
  24
  25 ;    Full basic register definitions for the Freescale S912XDP512 processor
  26 ;    MC9S12XDP512V2.pdf Appendix G
  27
  28 ; @author Sean Keys
  29
  30 ;* Define the cores of the CPU
  31
  32 .equ PIMcore0,   0x0000  ;ports A, B, E, ; inits, test
  33 .equ MMCcore0,   0x000A  ;Module Mapping Control core section 0 modes
  34 .equ PIMcore1,   0x000C  ;PIMcore section 1 TODO add explaination
  35 .equ EBIcore,    0x000E  ;External Bus Interface
  36 .equ MMCcore1,   0x0010  ;MMC core
  37 .equ MISPCcore,  0x0018  ;Miscellaneous Peripheral Core, Device ID Register
  38 .equ PIMcore2,   0x001C  ;memsiz, IRQ, HPRIO-------------------check with c128 to make sure
  39 .equ DBMcore,    0x0020  ;Debug Module S12XDBG
  40 .equ MMCcore2,   0x0030  ;PPAGE
  41 .equ PIMcore3,   0x0032  ;Port K
  42 .equ CRGcore,    0x0034  ;Clock and Reset Generator
  43 .equ SCI0core,   0x00C8  ;Serial Com Interface 0(RS232 on adapt card)
  44 .equ FCRcore,    0x0100  ;Flash Control Registers
  45 .equ EEPROMcore, 0x0110  ;EEPROM Control Registers
  46 ;-----------------------------------------------------------
  47
  48 ;                  PIMcore0
  49 ;*****************************************************************
  50 .equ PORTA,    PIMcore0+0x00  ;I/O port A 8-bit data register
  51 ;
  52 .equ PTA0,     0b00000001    ;port A bit 0
  53 .equ PTA1,     0b00000010    ;port A bit 1
  54 .equ PTA2,     0b00000100    ;port A bit 2
  55 .equ PTA3,     0b00001000    ;port A bit 3
  56 .equ PTA4,     0b00010000    ;port A bit 4
  57 .equ PTA5,     0b00100000    ;port A bit 5
  58 .equ PTA6,     0b01000000    ;port A bit 6
  59 .equ PTA7,     0b10000000    ;port A bit 7
  60
  61
  62 .equ PORTB,    PIMcore0+0x01  ;I/O port B 8-bit data register
  63 ;
  64 .equ PTB0,     0b00000001    ;port B bit 0
  65 .equ PTB1,     0b00000010    ;port B bit 1
  66 .equ PTB2,     0b00000100    ;port B bit 2
  67 .equ PTB3,     0b00001000    ;port B bit 3
  68 .equ PTB4,     0b00010000    ;port B bit 4
  69 .equ PTB5,     0b00100000    ;port B bit 5
  70 .equ PTB6,     0b01000000    ;port B bit 6
  71 .equ PTB7,     0b10000000    ;port B bit 7
  72
  73 .equ DDRA,     PIMcore0+0x02  ; I/O port A 8-bit data direction register
  74 ;
  75 .equ DDRA0,    0b00000001    ;port A bit 0
  76 .equ DDRA1,    0b00000010    ;port A bit 1
  77 .equ DDRA2,    0b00000100    ;port A bit 2
  78 .equ DDRA3,    0b00001000    ;port A bit 3
  79 .equ DDRA4,    0b00010000    ;port A bit 4
  80 .equ DDRA5,    0b00100000    ;port A bit 5
  81 .equ DDRA6,    0b01000000    ;port A bit 6
  82 .equ DDRA7,    0b10000000    ;port A bit 7
  83
  84 .equ DDRB,    PIMcore0+0x03    ;port B 8-bit date direction register
  85 ;
  86 .equ DDRB0,    0b00000001    ;port B bit 0
  87 .equ DDRB1,    0b00000010    ;port B bit 1
  88 .equ DDRB2,    0b00000100    ;port B bit 2
  89 .equ DDRB3,    0b00001000    ;port B bit 3
  90 .equ DDRB4,    0b00010000    ;port B bit 4
  91 .equ DDRB5,    0b00100000    ;port B bit 5
  92 .equ DDRB6,    0b01000000    ;port B bit 6
  93 .equ DDRB7,    0b10000000    ;port B bit 7
  94
  95 .equ PORTC,    PIMcore0+0x04   ;port C 8-bit data register
  96 ;
  97 .equ PTC0,     0b00000001    ;port C bit 0
  98 .equ PTC1,     0b00000010    ;port C bit 1
  99 .equ PTC2,     0b00000100    ;port C bit 2
 100 .equ PTC3,     0b00001000    ;port C bit 3
 101 .equ PTC4,     0b00010000    ;port C bit 4
 102 .equ PTC5,     0b00100000    ;port C bit 5
 103 .equ PTC6,     0b01000000    ;port C bit 6
 104 .equ PTC7,     0b10000000    ;port C bit 7
 105
 106 .equ PORTD,    PIMcore0+0x05   ;port D 8-bit data regsiter
 107 ;
 108 .equ PTD0,     0b00000001    ;port D bit 0
 109 .equ PTD1,     0b00000010    ;port D bit 1
 110 .equ PTD2,     0b00000100    ;port D bit 2
 111 .equ PTD3,     0b00001000    ;port D bit 3
 112 .equ PTD4,     0b00010000    ;port D bit 4
 113 .equ PTD5,     0b00100000    ;port D bit 5
 114 .equ PTD6,     0b01000000    ;port D bit 6
 115 .equ PTD7,     0b10000000    ;port D bit 7
 116
 117 .equ DDRC,    PIMcore0+0x06  ;port C 8-bit data direction register
 118 ;
 119 .equ DDRC0,    0b00000001    ;port C bit 0
 120 .equ DDRC1,    0b00000010    ;port C bit 1
 121 .equ DDRC2,    0b00000100    ;port C bit 2
 122 .equ DDRC3,    0b00001000    ;port C bit 3
 123 .equ DDRC4,    0b00010000    ;port C bit 4
 124 .equ DDRC5,    0b00100000    ;port C bit 5
 125 .equ DDRC6,    0b01000000    ;port C bit 6
 126 .equ DDRC7,    0b10000000    ;port C bit 7
 127
 128 .equ DDRD,    PIMcore0+0x07  ;port D 8-bit data direction register
 129 ;
 130 .equ DDRD0,    0b00000001    ;port D bit 0
 131 .equ DDRD1,    0b00000010    ;port D bit 1
 132 .equ DDRD2,    0b00000100    ;port D bit 2
 133 .equ DDRD3,    0b00001000    ;port D bit 3
 134 .equ DDRD4,    0b00010000    ;port D bit 4
 135 .equ DDRD5,    0b00100000    ;port D bit 5
 136 .equ DDRD6,    0b01000000    ;port D bit 6
 137 .equ DDRD7,    0b10000000    ;port D bit 7
 138
 139 .equ PORTE,   PIMcore0+0x08  ;port E 8-bit data regsiter
 140 ;
 141 .equ PTE0,     0b00000001    ;port E bit 0 ;also see appendix
 142 .equ PTE1,     0b00000010    ;port E bit 1 ;also see appendix
 143 .equ PTE2,     0b00000100    ;port E bit 2
 144 .equ PTE3,     0b00001000    ;port E bit 3
 145 .equ PTE4,     0b00010000    ;port E bit 4
 146 .equ PTE5,     0b00100000    ;port E bit 5
 147 .equ PTE6,     0b01000000    ;port E bit 6
 148 .equ PTE7,     0b10000000    ;port E bit 7
 149
 150
 151 .equ DDRE,   PIMcore0+0x09   ;port E 8-bit data direction register
 152 ;
 153 .equ DDRE0,    0b00000001    ;port E bit 0 ;also see appendix
 154 .equ DDRE1,    0b00000010    ;port E bit 1 ;also see appendix
 155 .equ DDRE2,    0b00000100    ;port E bit 2
 156 .equ DDRE3,    0b00001000    ;port E bit 3
 157 .equ DDRE4,    0b00010000    ;port E bit 4
 158 .equ DDRE5,    0b00100000    ;port E bit 5
 159 .equ DDRE6,    0b01000000    ;port E bit 6
 160 .equ DDRE7,    0b10000000    ;port E bit 7
 161
 162 ;                     MMCcore0
 163 ;****************************************************************
 164 .equ MMCCTLo,MMCcore0+0x00 ;mmctrlo TODO add brief explaination
 165 ;
 166 .equ CS0E,     0b00000001    ;mmctlo bit 0
 167 .equ CS1E,     0b00000010    ;mmctlo bit 1
 168 .equ CS2E,     0b00000100    ;mmctlo bit 2
 169 ;                            ;reserved
 170 ;                            ;reserved
 171 ;                            ;reserved
 172 ;                            ;reserved
 173 ;                            ;reserved
 174
 175 .equ MODE,   MMCcore0+0x01 ;MODE bits
 176 ;
 177 ;                            ;reserved
 178 ;                            ;reserved
 179 ;                            ;reserved
 180 ;                            ;reserved
 181 ;                            ;reserved
 182 .equ MODA,     0b00100000    ;mode bit  A
 183 .equ MODB,     0b01000000    ;mode bit  B
 184 .equ MODC,     0b10000000    ;mode bit  C
 185
 186 ;                         PIMcore1
 187 ;*************************************************************************
 188 .equ PUCR,   PIMcore1+0x00 ;Pull Up Controll Register
 189 ;
 190 .equ PUPAE,    0b00000001    ;pucr A bit enable
 191 .equ PUPBE,    0b00000010    ;pucr B bit enable
 192 .equ PUPCE,    0b00000100    ;pucr C bit enable
 193 .equ PUPDE,    0b00001000    ;pucr D bit enable
 194 .equ PUPEE,    0b00010000    ;pucr E bit enable
 195 ;                            ;reserved
 196 .equ BKPUE,    0b01000000    ;pucr bit 6 TODO add exp
 197 .equ PUPKE,    0b10000000    ;pucr bit 7 TODO add exp
 198
 199 .equ RDRIV,  PIMcore1+0x01 ;rdriv TODO add exp
 200 ;
 201 .equ RDPA,     0b00000001    ;rdriv A bit
 202 .equ RDPB,     0b00000010    ;rdriv B bit
 203 .equ RDPC,     0b00000100    ;rdriv C bit
 204 .equ RDPD,     0b00001000    ;rdriv D bit
 205 .equ RDPE,     0b00010000    ;rdriv E bit
 206 ;                            ;reserved
 207 ;                            ;reserved
 208 .equ RDPK,     0b10000000    ;rdriv bit 7 TODO add exp
 209
 210 ;                         EBIcore
 211 ;*****************************************************************
 212 .equ EBICTRL0, EBIcore+0x00 ;EBI TODO add exp
 213 ;
 214 .equ ASIZ0,    0b00000001    ;ebictrl0 bit 0
 215 .equ ASIZ1,    0b00000010    ;ebictrl0 bit 1
 216 .equ ASIZ2,    0b00000100    ;ebictrl0 bit 2
 217 .equ ASIZ3,    0b00001000    ;ebictrl0 bit 3
 218 .equ ASIZ4,    0b00010000    ;ebictrl0 bit 4
 219 .equ HDBE,     0b00100000    ;ebictrl0 bit 5
 220 ;                            ;bit 6 reserved
 221 .equ ITHRS,    0b10000000    ;ebictrl0 bit 7
 222
 223 .equ EBICTRL1, EBIcore+0x01  ;ebictrl 1  TODO add brief explaination
 224 ;
 225 .equ EXSTR0,   0b00000001    ;ebictrl1 bit 0
 226 .equ EXSTR1,   0b00000010    ;ebictrl1 bit 1
 227 .equ EXSTR2,   0b00000100    ;ebictrl1 bit 2
 228 ;                            ;reserved
 229 ;                            ;reserved
 230 ;                            ;reserved
 231 ;                            ;reserved
 232 .equ EWAITE,   0b10000000    ;ebictrl1 bit 7
 233
 234 ;                     MMCcore1
 235 ;*****************************************************************
 236 .equ GPAGE,  MMCcore1+0x00 ;mmcore1 GPAGE
 237 ;
 238 .equ GP0,      0b00000001    ;gpage bit 0
 239 .equ GP1,      0b00000010    ;gpage bit 1
 240 .equ GP2,      0b00000100    ;gpage bit 2
 241 .equ GP3,      0b00001000    ;gpage bit 3
 242 .equ GP4,      0b00010000    ;gpage bit 4
 243 .equ GP5,      0b00100000    ;gpage bit 5
 244 .equ GP6,      0b01000000    ;gpage bit 6
 245 ;                            ;reserved
 246
 247 .equ DIRECT, MMCcore1+0x01   ;mmcore1 direct
 248 ;
 249 .equ DP8,      0b00000001   ;direct bit 0
 250 .equ DP9,      0b00000010   ;direct bit 1
 251 .equ DP10,     0b00000100   ;direct bit 2
 252 .equ DP11,     0b00001000   ;direct bit 3
 253 .equ DP12,     0b00010000   ;direct bit 4
 254 .equ DP13,     0b00100000   ;direct bit 5
 255 .equ DP14,     0b01000000   ;direct bit 6
 256 .equ DP15,     0b10000000   ;direct bit 7
 257
 258 ;             MMCcore1+0x02        ;reserved
 259
 260 .equ MMCCTL1, MMCcore1+0x03 ;MMCTL1 bits TODO add exp
 261 ;
 262 .equ ROMON,    0b00000001   ; MMCTL1 bit 0
 263 .equ ROMHM,    0b00000010   ; MMCTL1 bit 1
 264 .equ EROMON,   0b00000100   ; MMCTL1 bit 2
 265 ;                           ;reserved
 266 ;                           ;reserved
 267 ;                           ;reserved
 268 ;                           ;reserved
 269 ;                           ;reserved
 270 ;                           ;reserved
 271
 272 ;             MMCcore1+0x04;reserved
 273 ;             MMCcore1+0x05;reserved
 274
 275 .equ RPAGE,   MMCcore1+0x06 ; rpage bits
 276 ;
 277 .equ RP0,      0b00000001   ;rpage bit 0
 278 .equ RP1,      0b00000010   ;rpage bit 1
 279 .equ RP2,      0b00000100   ;rpage bit 2
 280 .equ RP3,      0b00001000   ;rpage bit 3
 281 .equ RP4,      0b00010000   ;rpage bit 4
 282 .equ RP5,      0b00100000   ;rpage bit 5
 283 .equ RP6,      0b01000000   ;rpage bit 6
 284 .equ RP7,      0b10000000   ;rpage bit 7
 285
 286 .equ EPAGE,   MMCcore1+0x07  ; epage bits
 287 ;
 288 .equ EP0,      0b00000001    ;epage bit 0
 289 .equ EP1,      0b00000010    ;epage bit 1
 290 .equ EP2,      0b00000100    ;epage bit 2
 291 .equ EP3,      0b00001000    ;epage bit 3
 292 .equ EP4,      0b00010000    ;epage bit 4
 293 .equ EP5,      0b00100000    ;epage bit 5
 294 .equ EP6,      0b01000000    ;epage bit 6
 295 .equ EP7,      0b10000000    ;epage bit 7
 296
 297 ;                        MISPcore
 298 ;**********************************************************
 299 ;              MISPCcore+0x00;reserved
 300 ;              MISPCcore+0x01;reserved
 301
 302
 303 .equ PARTIDH,   MISPCcore+0x02   ;device ID high register
 304 .equ PARTIDL,   MISCPcore+0x03   ;device ID low register
 305
 306 ;                        PIMcore2
 307 ;**********************************************************
 308 .equ ECLKCTL,  PIMcore2+0x00  ;  todo add exp
 309 ;
 310 .equ EDIV0,    0b00000001     ;ECLKCTL bit 0
 311 .equ EDIV1,    0b00000010     ;ECLKCTL bit 1
 312 ;                             ;reserved
 313 ;                             ;reserved
 314 ;                             ;reserved
 315 ;                             ;reserved
 316 .equ NCLKX2,   0b01000000     ;ECLKCTL bit 6
 317 .equ NECLK,    0b10000000     ;ECLKCTL bit 7
 318
 319 ;              PIMcore2+0x01  ;reserved
 320
 321 .equ IRQCR,    PIMcore2+0x02  ;add explain.
 322 ;
 323 .equ IRQN,     0b01000000     ;IRQCR bit 6
 324 .equ IRQE,     0b10000000     ;IRQCR bit 7
 325 ;                             ;reserved
 326 ;                             ;reserved
 327 ;                             ;reserved
 328 ;                             ;reserved
 329 ;                             ;reserved
 330 ;                             ;reserved
 331
 332 ;               PIMcore2+0x03 ;reserved
 333
 334 ;                             DBMcore
 335 ;*********************************************************
 336 ;DBGXCTL  represents the contents if the Comparator A or C
 337 ;  control register is blended into this address
 338 ;DBGXCTL  represents the contents if the comparator B or D
 339 ;  control register is blended into this address
 340 ;*********************************************************
 341
 342 .equ DBGC1,   DBMcore+0x00    ;Debug control register 1
 343 ;
 344 .equ COMRV,    0b00000011     ;
 345 ;
 346 .equ DBGBRK,   0b00001100     ;
 347 ;
 348 .equ BDM,      0b00010000     ;
 349 .equ XGSBPE,   0b00100000     ;
 350 .equ TRIG,     0b01000000     ;
 351 .equ ARM,      0b10000000     ;
 352
 353 .equ DBGSR,   DBMcore+0x01  ;debug status register
 354 ;
 355 .equ SSF0,     0b00000001     ;
 356 .equ SSF1,     0b00000010     ;
 357 .equ SSF2,     0b00000100     ;
 358 ;                             ;reserved
 359 ;                             ;reserved
 360 ;                             ;reserved
 361
 362 .equ EXTF,     0b01000000     ;
 363 .equ TBF,      0b10000000     ;
 364
 365 .equ DBGTCR,  DBMcore+0x02   ;
 366 ;
 367 .equ TALIGN,   0b00000011    ;
 368 ;
 369 .equ TRCMOD,   0b00001100    ;
 370 ;
 371 .equ TRANGE,   0b00110000    ;
 372 ;
 373 .equ TSOURCE,  0b11000000    ;
 374 ;
 375
 376 .equ DBGC2,   DBMcore+0x03  ;
 377 ;
 378 .equ ABCM,     0b00000011    ;
 379 ;
 380 .equ CDCM,     0b00001100    ;
 381 ;
 382 ;                            ;reserved
 383 ;                            ;reserved
 384 ;                            ;reserved
 385 ;                            ;reserved
 386
 387 .equ DBGTBH,   DBMcore+0x04   ;debug trace buffer high register (bits 8-15)
 388
 389 .equ DBGTBL,   DBMcore+0x05   ;debug trace buffer low register (bits 0-7)
 390
 391 .equ DBGCNT,   DBMcore+0x06   ;debug count regsiter bits 0-6  bit 7 reserved
 392 ;
 393 .equ CNT,      0b011111111    ;
 394
 395 .equ DBGSCRX,  DBMcore+0x07   ;debug comparator c expansion register
 396 ;
 397 .equ SC0,       0b00000001    ;SCO bit
 398 .equ SC1,       0b00000010    ;SC1 bit
 399 .equ SC2,       0b00000100    ;SC2 bit
 400 .equ SC3,       0b00001000    ;SC3 bit
 401 ;                             ;reserved
 402 ;                             ;reserved
 403 ;                             ;reserved
 404 ;                             ;reserved
 405
 406 .equ DBGXCTL,  DBMcore+0x08   ;IF COMPARITOR A or C CONTROL REGISTER IS BLENDED INTO THIS ADDRESS(DEFAULT)
 407 ;
 408 .equ COMPE,     0b00000001    ;
 409 .equ SRC,       0b00000010    ;
 410 .equ RWE,       0b00000100    ;
 411 .equ RW,        0b00001000    ;
 412 .equ BRK,       0b00010000    ;
 413 .equ TAG,       0b00100000    ;
 414 .equ NDB,       0b01000000    ;
 415 ;                             ;reserved
 416
 417 ;.equ DBGXCTL,  DBMcore+0x08   ;IF COMPARITOR B or D CONTROL REGISTER IS BLENDED INTO THE ADDRESS
 418 ;
 419 ;.equ COMPE,     0b00000001    ;
 420 ;.equ SRC,       0b00000010    ;
 421 ;.equ RWE,       0b00000100    ;
 422 ;.equ RW,        0b00001000    ;
 423 ;.equ BRK,       0b00010000    ;
 424 ;.equ TAG,       0b00100000    ;
 425 ;.equ SZ,        0b01000000    ;
 426 ;.equ SZE,       0b10000000    ;reserved
 427
 428 .equ DBGXAH,    DBMcore+0x09  ;TODO add exp
 429
 430 .equ DBGXAM,    DBMcore+0x0A  ;TODO add exp
 431
 432 .equ DBGXAL,    DBMcore+0x0B  ;TODO add exp
 433
 434 .equ DBGXDH,    DBMcore+0x0C  ;TODO add exp
 435
 436 .equ DBGXDL,    DBMcore+0x0D  ;TODO add exp
 437
 438 .equ DBGXDHM,   DBMcore+0x0E  ;TODO add exp
 439
 440 .equ DBGXDLM,   DBMcore+0x0F  ;TODO add exp
 441
 442 .equ PPAGE,    MMCcore2+0x00   ;TODO add exp
 443 ;
 444 .equ PIX0,       0b00000001   ;PIX bit 0
 445 .equ PIX1,       0b00000010   ;PIX bit 1
 446 .equ PIX2,       0b00000100   ;PIX bit 2
 447 .equ PIX3,       0b00001000   ;PIX bit 3
 448 .equ PIX4,       0b00010000   ;PIX bit 4
 449 .equ PIX5,       0b00100000   ;PIX bit 5
 450 .equ PIX6,       0b01000000   ;PIX bit 6
 451 .equ PIX7,       0b10000000   ;PIX bit 7
 452
 453 ;                             ;reserved
 454
 455 .equ PORTK,   PIMcore3+0x00   ; Port K
 456 ;
 457 .equ PTK0,       0b00000001   ;port k bit 0
 458 .equ PTK1,       0b00000010   ;port k bit 1
 459 .equ PTK2,       0b00000100   ;port k bit 2
 460 .equ PTK3,       0b00001000   ;port k bit 3
 461 .equ PTK4,       0b00010000   ;port k bit 4
 462 .equ PTK5,       0b00100000   ;port k bit 5
 463 .equ PTK6,       0b01000000   ;port k bit 6
 464 .equ PTK7,       0b10000000   ;port k bit 7
 465
 466 .equ DDRK,    PIMcore3+01     ;port k data direction register
 467 ;
 468 .equ DDRK0,      0b00000001   ;port k data direction register bit 0
 469 .equ DDRK1,      0b00000010   ;port k data direction register bit 1
 470 .equ DDRK2,      0b00000100   ;port k data direction register bit 2
 471 .equ DDRK3,      0b00001000   ;port k data direction register bit 3
 472 .equ DDRK4,      0b00010000   ;port k data direction register bit 4
 473 .equ DDRK5,      0b00100000   ;port k data direction register bit 5
 474 .equ DDRK6,      0b01000000   ;port k data direction register bit 6
 475 .equ DDRK7,      0b10000000   ;port k data direction register bit 7
 476
 477 .equ SYNR,    CRGcore+0x00    ;CRG synthesizer register
 478 ;
 479 .equ SYN0,       0b00000001   ;CRG synthesizer register 0
 480 .equ SYN1,       0b00000010   ;CRG synthesizer register 1
 481 .equ SYN2,       0b00000100   ;CRG synthesizer register 2
 482 .equ SYN3,       0b00001000   ;CRG synthesizer register 3
 483 .equ SYN4,       0b00010000   ;CRG synthesizer register 4
 484 .equ SYN5,       0b00100000   ;CRG synthesizer register 5
 485 ;                             ;reserved
 486 ;                             ;reserved
 487
 488 .equ REFDV,   CRGcore+0x01    ;CRG reference divider register
 489 ;
 490 .equ REFDV0,     0b00000001   ;CRG reference divider register bit 0
 491 .equ REFDV1,     0b00000010   ;CRG reference divider register bit 2
 492 .equ REFDV2,     0b00000100   ;CRG reference divider register bit 3
 493 .equ REFDV3,     0b00001000   ;CRG reference divider register bit 4
 494 .equ REFDV4,     0b00010000   ;CRG reference divider register bit 5
 495 ;                             ;reserved
 496 ;                             ;reserved
 497
 498 ;.equ CTFLG,  CRGcore+0x02    ;reserved for factory test
 499
 500 .equ CRGFLG,  CRGcore+0x03    ;CRG flags register
 501 ;
 502 .equ SCM,        0b00000001   ;CRG SCM bit
 503 .equ SCMIF,      0b00000010   ;CRG SCMIF bit
 504 .equ TRACK,      0b00000100   ;CRG TRACK bit
 505 .equ LOCK,       0b00001000   ;CRG LOCK bit
 506 .equ LOCKIF,     0b00010000   ;CRG LOCKIF bit
 507 .equ LVRF,       0b00100000   ;CRG LVRF bit
 508 .equ PORF,       0b01000000   ;CRG PORF bit
 509 .equ RTIF,       0b10000000   ;CRG RTIF bit
 510
 511 .equ CRGINT,  CRGcore+0x04    ;CRGINT
 512 ;
 513 ;                             ;reserved
 514 .equ SCMIE,      0b00000010   ;CRGINT SCMIE bit
 515 ;                             ;reserved
 516 ;                             ;reserved
 517 .equ LOCKIE,     0b00010000   ;CRGINT LOCKIE bit
 518 ;                             ;reserved
 519 ;                             ;reserved
 520 .equ ILAF,       0b01000000   ;CRGINT ILAF bit
 521 .equ RTIE,       0b10000000   ;CRGINT RTIE bit
 522
 523 .equ CLKSEL,  CRGcore+0x05    ;CRG clock select register
 524 ;
 525 .equ COPWAI,     0b00000001   ;CLKSEL COPWAI register
 526 .equ RTIWAI,     0b00000010   ;CLKSEL RTIWAI register
 527 ;                             ;reserved
 528 .equ PLLWAI,     0b00000100   ;CLKSEL PLLWAI register
 529 ;                             ;reserved
 530 ;                             ;reserved
 531 .equ PSTP,       0b01000000   ;CLKSEL PST register
 532 .equ PLLSEL,     0b10000000   ;CLKSEL PLLSEL register
 533
 534 .equ PLLCTL,  CRGcore+0x06    ;CRG PLL control register
 535 ;
 536 .equ SCME,       0b00000001   ;PLLCTL SCME bit
 537 .equ PCE,        0b00000010   ;PLLCTL PCE bit
 538 .equ PRE,        0b00000100   ;PLLCTL PRE bit
 539 .equ FSTWKP,     0b00001000   ;PLLCTL FSTWKP bit
 540 .equ ACQ,        0b00010000   ;PLLCTL ACQ bit
 541 .equ AUTO,       0b00100000   ;PLLCTL AUTO bit
 542 .equ PLLON,      0b01000000   ;PLLCTL PLLON bit
 543 .equ CME,        0b10000000   ;PLLCTL CME bit
 544
 545 .equ RTICTL,  CRGcore+0x07    ;RTICTL
 546 ;
 547 .equ RTR0,       0b00000001   ;RTICTL RTR0 bit
 548 .equ RTR1,       0b00000010   ;RTICTL RTR1 bit
 549 .equ RTR2,       0b00000100   ;RTICTL RTR2 bit
 550 .equ RTR3,       0b00001000   ;RTICTL RTR3 bit
 551 .equ RTR4,       0b00010000   ;RTICTL RTR4 bit
 552 .equ RTR5,       0b00100000   ;RTICTL RTR5 bit
 553 .equ RTR6,       0b01000000   ;RTICTL RTR6 bit
 554 .equ RTDEC,      0b10000000   ;RTICTL RTDEC bit
 555
 556 .equ COPCTL,  CRGcore+0x08    ;COP control register
 557 ;
 558 .equ CR0,        0b00000001   ;COP watchdog timer rate select
 559 .equ CR1,        0b00000010   ;COP watchdog timer rate select
 560 .equ CR2,        0b00000100   ;COP watchdog timer rate select
 561 ;                             ;reserved
 562 ;                             ;reserved
 563 ;                             ;reserved
 564 .equ RSBCK,      0b01000000   ;COP and RTI stop in active BDM mode bit
 565 .equ WCOP,       0b10000000   ;TODO add def
 566
 567 ;.equ FORBYP, CRGcore+0x09    ;reserved for factory test
 568
 569 ;.equ CTCL,   CRGcore+0x0A    ;reserved for factory test
 570
 571 .equ ARMCOP,  CRGcore+0x0B    ;CRG COP arm/timer reset register
 572
 573 ;                       SCI0
 574 ;************************************************************************
 575 ;SCI0BDH/SCI0BDL/SCI0BDL registers are accessable if the AMAP bit in the
 576 ;    SCI0SR2 register is set to ZERO
 577 ;SCI0ASR1/SCIACR1/SCI0ACR2 registers are accessible if the AMAP bit in
 578 ;    the SCI0SR2 register is set to ONE
 579 ;
 580 ;************************************************************************
 581 .equ SCI0BDH, SCI0core+0x00  ;SCI0 baud rate registers (8-12 bits)
 582 ; f (as in first) added as prefix so names dont conflict with other SCIs
 583 .equ fSBR8,      0b00000001   ;
 584 .equ fSBR9,      0b00000010   ;
 585 .equ fSBR10,     0b00000100   ;
 586 .equ fSBR11,     0b00001000   ;
 587 .equ fSBR12,     0b00010000   ;
 588 .equ fTNP0,      0b00100000   ;
 589 .equ fTNP1,      0b01000000   ;
 590 .equ fIREN,      0b10000000   ;
 591
 592 .equ SCI0BDL, SCI0core0+0x01 ;SCI baud rate registers (0-7 bits)
 593 ; f (as in first) added as prefix so names dont conflict with other SCIs
 594 .equ fSBR0,      0b00000001   ;
 595 .equ fSBR1,      0b00000010   ;
 596 .equ fSBR2,      0b00000100   ;
 597 .equ fSBR3,      0b00001000   ;
 598 .equ fSBR4,      0b00010000   ;
 599 .equ fSBR5,      0b00100000   ;
 600 .equ fSBR6,      0b01000000   ;
 601 .equ fSBR7,      0b10000000   ;
 602
 603 .equ SCI0CR1,  SCI0core+0x02  ;SCI0 control register 1
 604 ; f (as in first) added as prefix so names dont conflict with other SCIs
 605 .equ fPT,        0b00000001   ;
 606 .equ fPE,        0b00000010   ;
 607 .equ fILT,       0b00000100   ;
 608 .equ fWAKE,      0b00001000   ;
 609 .equ fM,         0b00010000   ;
 610 .equ fRSRC,      0b00100000   ;
 611 .equ fSCSIWAI,   0b01000000   ;
 612 .equ fLOOPS,     0b10000000   ;
 613
 614 .equ SCI0ASR1,  SCI0core+0x03  ;SCI0 status register
 615 ; f (as in first) added as prefix so names dont conflict with other SCIs
 616 .equ fBKDIF,     0b00000001   ;
 617 .equ fBERRIF,    0b00000011   ;
 618 .equ fBERRV,     0b00000100   ;
 619 ;                             ;reserved
 620 ;                             ;reserved
 621 ;                             ;reserved
 622 ;                             ;reserved
 623 .equ fRXEDGIF,   0b10000000   ;
 624
 625 .equ SCI0ACR1,  SCI0core+0x04  ;
 626 ; f (as in first) added as prefix so names dont conflict with other SCIs
 627 .equ fBKDIE,     0b00000001   ;
 628 .equ fBERRIE,    0b00000010   ;
 629 ;                             ;reserved
 630 ;                             ;reserved
 631 ;                             ;reserved
 632 ;                             ;reserved
 633 ;                             ;reserved
 634 .equ RXEDGIE,    0b10000000   ;
 635
 636 .equ SCI0ACR2,  SCI0core+0x05  ;
 637 ; f (as in first) added as prefix so names dont conflict with other SCIs
 638 .equ fBKDFE,     0b00000001   ;
 639 .equ fBERRMO,    0b00000010   ;
 640 .equ fBERMM1,    0b00000100   ;
 641 ;                             ;reserved
 642 ;                             ;reserved
 643 ;                             ;reserved
 644 ;                             ;reserved
 645 ;                             ;reserved
 646
 647 .equ SCI0CR2,   SCI0core+0x06  ;
 648 ; f (as in first) added as prefix so names dont conflict with other SCIs
 649 .equ fSBK,       0b00000001   ;
 650 .equ fRWU,       0b00000010   ;
 651 .equ fRE,        0b00000100   ;
 652 .equ fTE,        0b00001000   ;
 653 .equ fILIE,      0b00010000   ;
 654 .equ fRIE,       0b00100000   ;
 655 .equ fTCIE,      0b01000000   ;
 656 .equ fTIE,       0b10000000   ;
 657
 658 .equ SCI0SR1,   SCI0core+0x07  ;
 659 ; f (as in first) added as prefix so names dont conflict with other SCIs
 660 .equ fPF,        0b00000001   ;
 661 .equ fFE,        0b00000010   ;
 662 .equ fNF,        0b00000100   ;
 663 .equ fOR,        0b00001000   ;
 664 .equ fIDLE,      0b00010000   ;
 665 .equ fRDRF,      0b00100000   ;
 666 .equ fTC,        0b01000000   ;
 667 .equ fTDRE,      0b10000000   ;
 668
 669 .equ SCI0SR2,  SCI0core+0x08   ;
 670 ; f (as in first) added as prefix so names dont conflict with other SCIs
 671 .equ fRAF,       0b00000001   ;
 672 .equ fTXDIR,     0b00000010   ;
 673 .equ fBRK13,     0b00000100   ;
 674 .equ fRXPOL,     0b00001000   ;
 675 .equ fTXPOL,     0b00010000   ;
 676 ;                             ;reserved
 677 ;                             ;reserved
 678 .equ fAMAP,      0b10000000   ;
 679
 680 .equ SCI0DRH,  SCI0core+0x09   ;
 681 ; f (as in first) added as prefix so names dont conflict with other SCIs
 682 ;                             ;reserved
 683 ;                             ;reserved
 684 ;                             ;reserved
 685 ;                             ;reserved
 686 ;                             ;reserved
 687 ;                             ;reserved
 688 .equ fT8,        0b01000000   ;
 689 .equ fR8,        0b10000000   ;
 690
 691 .equ SCI0DRL,  SCI0core+0x0A  ;
 692 ; f (as in first) added as prefix so names dont conflict with other SCIs
 693 .equ fR0,        0b00000001   ;
 694 .equ fR1,        0b00000010   ;
 695 .equ fR2,        0b00000100   ;
 696 .equ fR3,        0b00001000   ;
 697 .equ fR4,        0b00010000   ;
 698 .equ fR5,        0b00100000   ;
 699 .equ fR6,        0b01000000   ;
 700 .equ fR7,        0b10000000   ;
 701 ;
 702 .equ fT0,        0b00000001   ;
 703 .equ fT1,        0b00000010   ;
 704 .equ fT2,        0b00000100   ;
 705 .equ fT3,        0b00001000   ;
 706 .equ fT4,        0b00010000   ;
 707 .equ fT5,        0b00100000   ;
 708 .equ fT6,        0b01000000   ;
 709 .equ fT7,        0b10000000   ;
 710
 711 ;                         FCRcore
 712 ;**********************************************************
 713
 714 .equ FCLKDIV,  FCRcore+0x00   ;Flash clock divide register
 715 ;
 716 .equ FDIV0,      0b00000001   ;
 717 .equ FDIV1,      0b00000010   ;
 718 .equ FDIV2,      0b00000100   ;
 719 .equ FDIV3,      0b00001000   ;
 720 .equ FDIV4,      0b00010000   ;
 721 .equ FDIV5,      0b00100000   ;
 722 .equ PRDIV,      0b01000000   ;
 723 .equ FDIVLD,     0b10000000   ;
 724
 725 .equ FSEC,    FCRcore+0x01    ;Flash Security Revister
 726 ;
 727 .equ SEC0,       0b00000001   ;
 728 .equ SEC1,       0b00000010   ;
 729 .equ RNV2,       0b00000100   ;
 730 .equ RNV3,       0b00001000   ;
 731 .equ RNV4,       0b00010000   ;
 732 .equ RNV5,       0b00100000   ;
 733 .equ KEYEN0,     0b01000000   ;
 734 .equ KEYEN1,     0b10000000   ;
 735
 736 .equ FTSTMOD, FCRcore+0x02    ;
 737 ;
 738 ;                             ;reserved
 739 ;                             ;reserved
 740 ;                             ;reserved
 741 ;                             ;reserved
 742 .equ WRALL,      0b00010000   ;
 743 .equ MRDS,       0b01100000   ;
 744 ;                             ;reserved
 745
 746 .equ FCNFG,   FCRcore+0x03    ;
 747 ;
 748 ;                             ;reserved
 749 ;                             ;reserved
 750 ;                             ;reserved
 751 ;                             ;reserved
 752 ;                             ;reserved
 753 .equ KEYACC,     0b00100000   ;
 754 .equ CCIE,       0b01000000   ;
 755 .equ CBEIE,      0b10000000   ;
 756
 757 .equ FPROT,   FCRcore+0x04    ;
 758 ;
 759 .equ FPLS0,      0b00000001   ;
 760 .equ FPLS1,      0b00000010   ;
 761 .equ FPLDIS,     0b00000100   ;
 762 .equ FPHS0,      0b00001000   ;
 763 .equ FPHS1,      0b00010000   ;
 764 .equ FPHSDIS,    0b00100000   ;
 765 .equ RNV6,       0b01000000   ;
 766 .equ FPOPEN,     0b10000000   ;
 767
 768 .equ FSTAT,   FCRcore+0x05    ;
 769 ;
 770 ;                             ;reserved
 771 ;                             ;reserved
 772 .equ BLANK,      0b00000100   ;
 773 ;                             ;reserved
 774 .equ ACCERR,     0b00010000   ;flash access error
 775 .equ PVIOL,      0b00100000   ;protection violation
 776 .equ CCIF,       0b01000000   ;command complete interrypt flag
 777 .equ CBEIF,      0b10000000   ;command buffer empty mode commands
 778
 779 .equ FCMD,   FCRcore+0x06     ;flash command register
 780 ;
 781 .equ CMDB0,      0b00000001   ;
 782 .equ CMDB1,      0b00000010   ;
 783 .equ CMDB2,      0b00000100   ;
 784 .equ CMDB3,      0b00001000   ;
 785 .equ CMDB4,      0b00010000   ;
 786 .equ CMDB5,      0b00100000   ;
 787 .equ CMDB6,      0b01000000   ;
 788 ;                             ;reserved
 789
 790 .equ ClearMass,     CMDB6+CMDB0  ;
 791 .equ ClearSection,  CMDB6        ;
 792 .equ WriteWord,     CMDB5        ;
 793
 794 .equ FCTL,   FCRcore+0x07    ;
 795 ;
 796 .equ NV0,        0b00000001   ;
 797 .equ NV1,        0b00000010   ;
 798 .equ NV2,        0b00000100   ;
 799 .equ NV3,        0b00001000   ;
 800 .equ NV4,        0b00010000   ;
 801 .equ NV5,        0b00100000   ;
 802 .equ NV6,        0b01000000   ;
 803 .equ NV7,        0b10000000   ;
 804
 805 .equ FADDRHI, FCRcore+0x08    ; bits 0-7
 806
 807 .equ FADDRLO, FCRcore+0x09    ;bits 0-7
 808
 809 .equ FDATAHI, FCRcore+0x0A    ;bits 0-7
 810
 811 .equ FDATALO, FCRcore+0x0B    ;bits 0-7
 812
 813 ; FCRcore+0x0C-0x0F reserved
 814
 815 ;                 EEPROM
 816 ;*******************************************************
 817
 818 .equ ECLKDIV,  EEPROMcore+0x00  ;EEPROM clock divide register
 819 ;
 820 .equ EDIV0,      0b00000001     ;
 821 .equ EDIV1,      0b00000010     ;
 822 .equ EDIV2,      0b00000100     ;
 823 .equ EDIV3,      0b00001000     ;
 824 .equ EDIV4,      0b00010000     ;
 825 .equ EDIV5,      0b00100000     ;
 826 .equ PRDIV8,     0b01000000     ;
 827 .equ EDIVLD,     0b10000000     ;
 828
 829 ;     EEPROMcore+0x01 reserved
 830
 831 ;     EEPROMcore+0x02 reserved
 832
 833 .equ ECNFG,  EEPROMcore+0x03     ;EEPROM configuration register
 834 ;
 835 ;                                ;reserved
 836 ;                                ;reserved
 837 ;                                ;reserved
 838 ;                                ;reserved
 839 ;                                ;reserved
 840 ;                                ;reserved
 841 .equ CCIER,      0b01000000      ;
 842 .equ CBEIER,     0b10000000      ;
 843
 844 .equ EPROT,  EEPROMcore+0x04     ;
 845 ;
 846 .equ EPS0,       0b00000001      ;
 847 .equ EPS1,       0b00000010      ;
 848 .equ EPS2,       0b00000100      ;
 849 .equ EPDIS,      0b00001000      ;
 850 .equ RNV4,       0b00010000      ;
 851 .equ RNV5,       0b00100000      ;
 852 .equ RNV6,       0b01000000      ;
 853 .equ EPOPEN,     0b10000000      ;
 854
 855 .equ ESTAT,  EEPROMcore+0x05     ;EEPROM status register
 856 ;
 857 ;                                ;reserved
 858 ;                                ;reserved
 859 .equ BLANKR,      0b00000100     ;
 860 ;                                ;reserved
 861 .equ ACCERRR,     0b00010000     ;
 862 .equ PVIOLR,      0b00100000     ;
 863 .equ CCIFR,       0b01000000     ;
 864 .equ CBEIFR,      0b10000000     ;
 865
 866 .equ ECMD,   EEPROMcore+0x06     ;EEPROM command buffer and register
 867 ;
 868 .equ CMDB0R,      0b00000001     ;
 869 .equ CMDB1R,      0b00000010     ;
 870 .equ CMDB2R,      0b00000100     ;
 871 .equ CMDB3R,      0b00001000     ;
 872 .equ CMDB4R,      0b00010000     ;
 873 .equ CMDB5R,      0b00100000     ;
 874 .equ CMDB6R,      0b01000000     ;
 875 ;                                ;reserved
 876
 877 ;            EEPROMcore+0x07  reserved
 878
 879 .equ EADDRHI, EEPROMcore+0x08    ;
 880 ;
 881 .equ EABHI,       0b00000111     ;
 882 ;                                ;bits 3-7 reserved
 883
 884 .equ EADDRLO, EEPROMcore+0x09    ;
 885 ;
 886 .equ EABLO,       0b11111111     ;
 887
 888 .equ EDATAHI, EEPROMcore+0x0A    ;
 889 ;
 890 .equ EDHI,        0b11111111     ;
 891
 892 .equ EDATALO, EEPROMcore+0x0B    ;
 893 ;
 894 .equ EDLO,        0b11111111     ;