src/inc/9S12XDP512.h

   1 /**     @file 9S12XDP512.h
   2
   3         Copyright 2008, 2009 Fred Cooke
   4
   5         This is the device header for the FreeScale MC9S12XDP512 MCU. It contains
   6         declarations that allow access to all of the devices control registers.
   7
   8         This file is part of the FreeEMS project.
   9
  10         FreeEMS software is free software: you can redistribute it and/or modify
  11         it under the terms of the GNU General Public License as published by
  12         the Free Software Foundation, either version 3 of the License, or
  13         (at your option) any later version.
  14
  15         FreeEMS software is distributed in the hope that it will be useful,
  16         but WITHOUT ANY WARRANTY; without even the implied warranty of
  17         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18         GNU General Public License for more details.
  19
  20         You should have received a copy of the GNU General Public License
  21         along with any FreeEMS software.  If not, see http://www.gnu.org/licenses/
  22
  23         We ask that if you make any changes to this file you email them upstream to
  24         us at admin(at)diyefi(dot)org or, even better, fork the code on github.com!
  25
  26         Thank you for choosing FreeEMS to run your engine! */
  27
  28
  29 /* Full basic register definitions for the Freescale S912XDP512 processor */
  30 /* MC9S12XDP512V2.pdf Appendix G */
  31
  32
  33 /* see if we've seen this, if not, mark seen and process */
  34 #ifndef FILE_9S12XDP512_H_SEEN
  35 #define FILE_9S12XDP512_H_SEEN
  36
  37
  38 /* shortcuts to speed formatting */
  39 /* www.atmel.com/dyn/resources/prod_documents/avr_3_04.pdf First page, second column */
  40 /* http://www.ee.nmt.edu/~rison/ee308_spr06/homepage.html */
  41 /* extra parentheses for clarity and guarantee of precedence */
  42
  43 /* Dereferenced Volatile Unsigned Char Pointer */
  44 #define DVUCP(address) (*((volatile unsigned char*)(address)))
  45 /* Dereferenced Volatile Unsigned Short Pointer */
  46 #define DVUSP(address) (*((volatile unsigned short*)(address)))
  47
  48 /* Address Volatile Unsigned Char Pointer */
  49 #define AVUCP(address) ((volatile unsigned char*)(address))
  50 /* Address Volatile Unsigned Short Pointer */
  51 #define AVUSP(address) ((volatile unsigned short*)(address))
  52
  53
  54
  55 /* Port Integration Module - Reordered within sections for clarity */
  56 /* PIM information from 5 tables the last of which is spread over three pages */
  57
  58 /* Plain ports output switch, input state registers */
  59 #define PORTS_BA DVUSP(0x0001) /* Both A and B combined as a 16 bit register for ignition access */
  60 #define PORTA DVUCP(0x0000)
  61 #define PORTB DVUCP(0x0001)
  62 #define PORTE DVUCP(0x0008)
  63 #define PORTK DVUCP(0x0032)
  64 /* #define PORTC DVUCP(0x0004) these pins are not bonded on the 112 pin package */
  65 /* #define PORTD DVUCP(0x0005) these pins are not bonded on the 112 pin package */
  66
  67
  68 /* Plain ports Data Direction Registers */
  69 #define DDRA DVUCP(0x0002)
  70 #define DDRB DVUCP(0x0003)
  71 #define DDRE DVUCP(0x0009)
  72 #define DDRK DVUCP(0x0033)
  73
  74
  75 #define DDRC DVUCP(0x0006) /* these pins are not bonded on the 112 pin package but need switching to output */
  76 #define DDRD DVUCP(0x0007) /* these pins are not bonded on the 112 pin package but need switching to output */
  77
  78
  79 /* 0b1//1//00 */
  80 /* --K//E//BA */
  81 /* TODO NOTE: the sixth bit controls pull up on BKGD and VREGEN pins set this to ???? */
  82 /* NOTE: pull up on port E is for 0-4 and 7, ports 5 and 6 are pulled down during reset and never pulled up. */
  83 #define PUCR DVUCP(0x000C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
  84
  85
  86 /* 0b1//0//00 */
  87 /* --K//E//BA */
  88 /* NOTE: reduced drive affects all pins of all ports listed above. */
  89 #define RDRIV DVUCP(0x000D) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
  90
  91
  92 #define ECLKCTL DVUCP(0x001C) /* Comes up 0b_1100_0000 = both pins off in normal single chip mode */
  93 #define IRQCR DVUCP(0x001E) /* 0 in bit 7 makes it ultra sensitive, 1 makes it falling edge sensitive. 0 in bit 6 turns interrupts off, 1 in bit 6 turns them on. */
  94
  95
  96 /* Port T registers */
  97 #define PTT DVUCP(0x0240) /* GPIO output register, can not be read from reliably, use PTIT instead */
  98 #define PORTT DVUCP(0x0240) /* Duplicate definition for consistency */
  99 #define PTIT DVUCP(0x0241) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 100 #define DDRT DVUCP(0x0242) /* TODO configure all IO as outputs until we need it */
 101 #define RDRT DVUCP(0x0243) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 102 #define PERT DVUCP(0x0244) /* pull up/down enable when used as an input, 0 = no pull up, 1 = pull up on */
 103 #define PPST DVUCP(0x0245) /* 0 = pull up, 1 = pull down */
 104
 105
 106 /* Port S registers */
 107 #define PTS DVUCP(0x0248)
 108 #define PORTS DVUCP(0x0248) /* Duplicate definition for consistency */
 109 #define PTIS DVUCP(0x0249) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 110 #define DDRS DVUCP(0x024A) /* TODO configure all IO as outputs until we need it */
 111 #define RDRS DVUCP(0x024B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 112 #define PERS DVUCP(0x024C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 113 #define PPSS DVUCP(0x024D) /* 0 = pull up, 1 = pull down */
 114 #define WOMS DVUCP(0x024E) /* wired OR mode TODO find out what this actually means in real terms. */
 115
 116
 117 /* Port M registers */
 118 #define PTM DVUCP(0x0250)
 119 #define PORTM DVUCP(0x0250) /* Duplicate definition for consistency */
 120 #define PTIM DVUCP(0x0251) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 121 #define DDRM DVUCP(0x0252) /* TODO configure all IO as outputs until we need it */
 122 #define RDRM DVUCP(0x0253) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 123 #define PERM DVUCP(0x0254) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 124 #define PPSM DVUCP(0x0255) /* 0 = pull up, 1 = pull down */
 125 #define WOMM DVUCP(0x0256) /* wired OR mode TODO find out what this actually means in real terms. */
 126
 127
 128 /* this should be set to the following bit mask xx????00 */
 129 #define MODRR DVUCP(0x0257)
 130
 131
 132 /* Port P registers */
 133 #define PTP DVUCP(0x0258)
 134 #define PORTP DVUCP(0x0258) /* Duplicate definition for consistency */
 135 #define PTIP DVUCP(0x0259) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 136 #define DDRP DVUCP(0x025A) /* TODO configure all IO as outputs until we need it */
 137 #define RDRP DVUCP(0x025B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 138 #define PERP DVUCP(0x025C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 139 #define PPSP DVUCP(0x025D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 140 #define PIEP DVUCP(0x025E) /* interrupt enable, turns on interrupts */
 141 #define PIFP DVUCP(0x025F) /* interrupt flag, write a 1 to clear it */
 142
 143
 144 /* Port H registers */
 145 #define PTH DVUCP(0x0260)
 146 #define PORTH DVUCP(0x0260) /* Duplicate definition for consistency */
 147 #define PTIH DVUCP(0x0261) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 148 #define DDRH DVUCP(0x0262) /* TODO configure all IO as outputs until we need it */
 149 #define RDRH DVUCP(0x0263) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 150 #define PERH DVUCP(0x0264) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 151 #define PPSH DVUCP(0x0265) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 152 #define PIEH DVUCP(0x0266) /* interrupt enable, turns on interrupts */
 153 #define PIFH DVUCP(0x0267) /* interrupt flag, write a 1 to clear it */
 154
 155
 156 /* Port J registers */
 157 #define PTJ DVUCP(0x0268)
 158 #define PORTJ DVUCP(0x0268) /* Duplicate definition for consistency */
 159 #define PTIJ DVUCP(0x0269) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 160 #define DDRJ DVUCP(0x026A) /* TODO configure all IO as outputs until we need it */
 161 #define RDRJ DVUCP(0x026B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 162 #define PERJ DVUCP(0x026C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 163 #define PPSJ DVUCP(0x026D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 164 #define PIEJ DVUCP(0x026E) /* interrupt enable, turns on interrupts */
 165 #define PIFJ DVUCP(0x026F) /* interrupt flag, write a 1 to clear it */
 166
 167
 168 /* #define ATD0PT1 DVUCP(0x0271)        we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
 169 /* #define ATD0DDR1 DVUCP(0x0273) for use as an input, ATD0DIEN has to be set to 1. for use as an output? */
 170 /* #define ATD0RDR1 DVUCP(0x0275) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 171 #define ATD0PER1 DVUCP(0x0277) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 172
 173 /* #define ATD1PT1 DVUCP(0x0279)        we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
 174 /* #define ATD1DDR1 DVUCP(0x027B)       for use as an input, ATD1DIEN1 has to be set to 1. for use as an output? */
 175 /* #define ATD1RDR1 DVUCP(0x027D)       reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 176 /* #define ATD1PER1 DVUCP(0x027F)       pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 177
 178 /* Not available on 112 pin version     */
 179 /* #define ATD1DDR0 DVUCP(0x027A) */
 180 /* 0x0278 #define ATD1PT0 DVUCP() */
 181 /* 0x027C #define ATD1RDR0 DVUCP() */
 182 /* 0x027E #define ATD1PER0 DVUCP() */
 183
 184
 185 /* Memory Mapping Control registers TODO configure these to suit our application. */
 186 /* MMC 1/4 */
 187 //0x000B MODE DVUCP()
 188 //0x000A MMCCTL0 DVUCP()
 189 //0x0013 MMCCTL1 DVUCP()
 190
 191
 192 /* Page control registers */
 193 #define RPAGE DVUCP(0x0016) /* Used to page table data in and out of visible memory. */
 194 //0x0017 EPAGE DVUCP() /* /* TODO similar to above if we need another 2k of eeprom. what are advantages/disadvantages of eeprom over flash?? */
 195 #define PPAGE DVUCP(0x0030) /* TODO look at the best way to use the flash space in a complete system with a lot of code and data. used by compiler and maybe us to switch flash pages for loading/unloading data. */
 196 //0x0010 GPAGE DVUCP() /* /* Global page register for global instruction addressing. I doubt we will use this. */
 197 //0x0011 DIRECT DVUCP() /* /* Direct addressing mode control register. I doubt we will use this. */
 198
 199
 200 //// MMC 4/4
 201 //0x011C RAMWPC /* RAM Write Protection register, the pdf document appears to be incorrect for this, best not to touch it. */
 202 //0x011D RAMXGU /* XGATE Upper region limit, this defines how much RAM we give the xgate to work with. */
 203 //0x011E RAMSHL /* Shared memory lower boundary register, this defines the lower limit of the overlap between XGATE RAM and CPU RAM */
 204 //0x011F RAMSHU /* Shared memory upper boundary register, this defines the upper limit of the overlap between XGATE RAM and CPU RAM */
 205
 206
 207 //// EBI
 208 //0x000E EBICTL0 DVUCP() /*
 209 //0x000F EBICTL1 DVUCP() /*
 210
 211
 212 //// Misc Peripheral
 213 //0x001A PARTIDH DVUCP() /*
 214 //0x001B PARTIDL DVUCP() /*
 215
 216
 217 /* Clock and Reset Generator */
 218 #define SYNR DVUCP(0x0034) /* Multiplier of result of division by REFDV below, output is new PLL/Bus freqency. */
 219 #define REFDV DVUCP(0x0035) /* Divisor of external clock frequency pre being multiplied by SYNR above. */
 220 //0x0036 CTFLG DVUCP() /*
 221 #define CRGFLG DVUCP(0x0037) /* Clock and Reset Generator flags, we use this to determine when the PLL is stable and ready to use. Also to reset the RTI flag. */
 222 #define CRGINT DVUCP(0x0038) /* Bit 7 is RTIE RTI enable bit. */
 223 #define CLKSEL DVUCP(0x0039) /* Clock select register, choose PLL or external clock with this. */
 224 #define PLLCTL DVUCP(0x003A) /* PLL frequency generator control register, used for setting the bus frequency. */
 225 #define RTICTL DVUCP(0x003B) /* Divider select register */
 226 #define COPCTL DVUCP(0x003C) /* COP watch dog control register */
 227 //0x003D FORBYP DVUCP() /*
 228 #define ARMCOP DVUCP(0x003F) /* Computer operating properly timer, we won't be using this at least until we have profiled the running application. it will just cause headaches otherwise. */
 229
 230
 231 /* Enhanced Capture Timer */
 232 /* see reference document from Huang course overview/notes : http://www.ee.nmt.edu/~rison/ee308_spr06/lectures.html */
 233 /* see this link for a discussion of the old 68hc12 timer http://www.seattlerobotics.org/encoder/nov97/68hc12.html */
 234
 235 #define TCNT DVUSP(0x0044) /* Timer counter 16 bit (0x0044 TCNT (hi), 0x0045 TCNT (lo)) */
 236
 237 /* Behavioural control registers (dual purpose) */
 238 #define TIOS DVUCP(0x0040) /* Selects input capture or output compare mode for each timer pin */
 239 #define TIE DVUCP(0x004C) /* Timer channel interrupt enable register */
 240 #define TSCR1 DVUCP(0x0046) /* Timer System Control Register 1 */
 241 #define TSCR2 DVUCP(0x004D) /* Timer System Control Register 2 */
 242 #define TFLG DVUCP(0x004E) /* Timer channel flags */
 243 #define TFLGOF DVUCP(0x004F) /* Timer over flow flag */
 244 #define PTPSR DVUCP(0x006E) /* Precision prescaler for the main timer */
 245
 246 /* Output compare control registers */
 247 #define TTOV DVUCP(0x0047) /* Timer Toggle on Overflow output compare control */
 248 #define CFORC DVUCP(0x0041) /* Output compare force, write a 1 to make the programmed action occur now */
 249 #define OC7M DVUCP(0x0042) /* Channel 7 output compare other pins control mask */
 250 #define OC7D DVUCP(0x0043) /* Channel 7 output compare other pins states */
 251
 252 /*      Timer output compare action control registers
 253  *      OMx     OLx     Action
 254  *      0       0       Timer disconnected from output pin logic
 255  *      0       1       Toggle OCx output line
 256  *      1       0       Clear OCx output line to zero
 257  *      1       1       Set OCx output line to one */
 258 #define TCTL1 DVUCP(0x0048) /* (M,L) 77,66,55,44 */
 259 #define TCTL2 DVUCP(0x0049) /* (M,L) 33,22,11,00 */
 260 #define TCTL1_ADDR AVUCP(0x0048) /* (M,L) 77,66,55,44 */
 261 #define TCTL2_ADDR AVUCP(0x0049) /* (M,L) 33,22,11,00 */
 262
 263
 264 /* Input capture control registers */
 265 #define DLYCT DVUCP(0x0069) /* Delay counter control register (minimum tooth width) */
 266 #define ICSYS DVUCP(0x006B) /* Input capture behaviour control register */
 267 #define ICOVW DVUCP(0x006A) /* Input capture overwrite allow */
 268
 269 /*      Timer input capture edge detection control registers
 270  *      EDGxB   EDGxA   Configuration
 271  *      0               0               Capture disabled
 272  *      0               1               Capture on rising edges only
 273  *      1               0               Capture on falling edges only
 274  *      1               1               Capture on any edge (rising or falling) */
 275 #define TCTL3 DVUCP(0x004A) /* (B,A) 77,66,55,44 */
 276 #define TCTL4 DVUCP(0x004B) /* (B,A) 33,22,11,00 */
 277
 278 /* Input capture holding registers for 0 - 3 */
 279 #define TC0H DVUSP(0x0078) /* 16 bit (0x0078 TC0H (hi), 0x0079 TC0H (lo)) */
 280 #define TC1H DVUSP(0x007A) /* 16 bit (0x007A TC1H (hi), 0x007B TC1H (lo)) */
 281 #define TC2H DVUSP(0x007C) /* 16 bit (0x007C TC2H (hi), 0x007D TC2H (lo)) */
 282 #define TC3H DVUSP(0x007E) /* 16 bit (0x007E TC3H (hi), 0x007F TC3H (lo)) */
 283
 284 /* Time value comparison/storage registers for each timer channel */
 285 #define TC0 DVUSP(0x0050) /* 16 bit (0x0050 TC0 (hi), 0x0051 TC0 (lo)) */
 286 #define TC1 DVUSP(0x0052) /* 16 bit (0x0052 TC1 (hi), 0x0053 TC1 (lo)) */
 287 #define TC2 DVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
 288 #define TC3 DVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
 289 #define TC4 DVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
 290 #define TC5 DVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
 291 #define TC6 DVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
 292 #define TC7 DVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
 293
 294 #define TC2_ADDR AVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
 295 #define TC3_ADDR AVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
 296 #define TC4_ADDR AVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
 297 #define TC5_ADDR AVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
 298 #define TC6_ADDR AVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
 299 #define TC7_ADDR AVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
 300
 301
 302
 303 /* Pulse accumulator control registers */
 304 //0x0068 ICPAR DVUCP() /*
 305 //0x0060 PACTL DVUCP() /*
 306 //0x0061 PAFLG DVUCP() /*
 307 //0x0070 PBCTL DVUCP() /*
 308 //0x0071 PBFLG DVUCP() /*
 309 // one short for each hi lo par based on hi address.
 310 /* Pulse accumulator registers */
 311 //0x0062 PACN3 (hi)
 312 //0x0063 PACN2 (lo)
 313 //0x0064 PACN1 (hi)
 314 //0x0065 PACN0 (lo)
 315 /* Pulse accumulator holding registers */
 316 //0x0072 PA3H DVUCP() /* hi?
 317 //0x0073 PA2H DVUCP() /* lo?
 318 //0x0074 PA1H DVUCP() /* hi?
 319 //0x0075 PA0H DVUCP() /* lo?
 320
 321
 322 /* Modulus down counter control registers */
 323 #define MCCTL DVUCP(0x0066) /* Modulus control register */
 324 #define MCFLG DVUCP(0x0067) /* Modulus flag (high bit) and input edge indicators (low 4 bits) */
 325 #define MCCNT DVUSP(0x0076) /* 16 bit (0x0076 MCCNT (hi), 0x0077 MCCNT (lo)) */
 326 #define PTMCPSR DVUCP(0x006F) /* Precision prescaler for the modulus down counter */
 327
 328
 329 /* Analog To Digital converter 1 */
 330 /* TODO Configure these and disable the non functional 16 - 23 144 pin section! */
 331 #define ATD1CTL0 DVUCP(0x0080) /* 0 - 3 define which ADC channel to wrap on when doing multiple channels */
 332 #define ATD1CTL1 DVUCP(0x0081) /* External trigger select when enabled in other control register */
 333 #define ATD1CTL2 DVUCP(0x0082) /* bit 7 turns the ADC block on. */
 334 #define ATD1CTL3 DVUCP(0x0083) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
 335 #define ATD1CTL4 DVUCP(0x0084) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
 336 #define ATD1CTL5 DVUCP(0x0085) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
 337 //0x0086 ATD1STAT0 DVUCP() /*
 338 //0x0088 ATD1TEST0 DVUCP() /*
 339 //0x0089 ATD1TEST1 DVUCP() /*
 340 //0x008A ATD1STAT2 DVUCP() /*
 341 //0x008B ATD1STAT1 DVUCP() /*
 342 #define ATD1DIEN0 DVUCP(0x008C) /* Digital input enable - these pins are not bonded on the 112 pin package */
 343 #define ATD1DIEN1 DVUCP(0x008D) /* Digital input enable */
 344 //0x008E ATD1PTAD0 DVUCP() /* digital use only */
 345 //0x008F ATD1PTAD1 DVUCP() /* digital use only */
 346 // one short for each hi lo par based on hi address. label with WORD for consistency
 347 #define ATD1_BASE 0x0090
 348 #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ /* SpareADC (NC)         */
 349 #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ /* SpareADC (NC)         */
 350 #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ /* SpareADC (NC)         */
 351 #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ /* SpareADC (NC)         */
 352 #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ /* SpareADC (NC)         */
 353 #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ /* SpareADC (NC)         */
 354 #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ /* SpareADC (NC)         */
 355 #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ /* SpareADC (NC)         */
 356
 357
 358 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
 359 //0x00A0 ATD1DR8H
 360 //0x00A1 ATD1DR8L
 361 //0x00A2 ATD1DR9H
 362 //0x00A3 ATD1DR9L
 363 //0x00A4 ATD1DR10H
 364 //0x00A5 ATD1DR10L
 365 //0x00A6 ATD1DR11H
 366 //0x00A7 ATD1DR11L
 367 //0x00A8 ATD1DR12H
 368 //0x00A9 ATD1DR12L
 369 //0x00AA ATD1DR13H
 370 //0x00AB ATD1DR13L
 371 //0x00AC ATD1DR14H
 372 //0x00AD ATD1DR14L
 373 //0x00AE ATD1DR15H
 374 //0x00AF ATD1DR15L
 375 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
 376
 377
 378 /* IIC1 - Inter Intergrated Circuit interface 1 TODO configure and use */
 379 //0x00B0 IBAD DVUCP() /*
 380 //0x00B1 IBFD DVUCP() /*
 381 //0x00B2 IBCR DVUCP() /*
 382 //0x00B3 IBSR DVUCP() /*
 383 //0x00B4 IBDR DVUCP() /*
 384
 385
 386 /* SCI2 */
 387 //0x00B8 SCI2BDH
 388 //0x00B8 SCI2ASR1
 389 //0x00B9 SCI2BDL
 390 //0x00B9 SCI2ACR1
 391 //0x00BA SCI2CR1
 392 //0x00BA SCI2ACR2
 393 //0x00BB SCI2CR2
 394 //0x00BC SCI2SR1
 395 //0x00BD SCI2SR2
 396 //0x00BE SCI2DRH
 397 //0x00BF SCI2DRL
 398
 399
 400 /* SCI3 */
 401 //0x00C0 SCI3BDH
 402 //0x00C0 SCI3ASR1
 403 //0x00C1 SCI3BDL
 404 //0x00C1 SCI3ACR1
 405 //0x00C2 SCI3CR1
 406 //0x00C2 SCI3ACR2
 407 //0x00C3 SCI3CR2
 408 //0x00C4 SCI3SR1
 409 //0x00C5 SCI3SR2
 410 //0x00C6 SCI3DRH
 411 //0x00C7 SCI3DRL
 412
 413
 414 /* SCI0 debug/comms/datalogging TODO this is our primary serial interface for flash loading, setup serial comms software to communicate with MTX or similar for testing. */
 415 #define SCI0_BASE 0x00C8
 416
 417 #define SCI0BD DVUSP(SCI0_BASE + 0x0)           /* #define SCI0BDH DVUCP(0x00C8), #define SCI0BDL DVUCP(0x00C9) (IR and baud control) */
 418 #define SCI0CR1 DVUCP(SCI0_BASE + 0x2)  /* Control reg 1 */
 419
 420 #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) /* Status reg 1a (rx flags) */
 421 #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) /* Control reg 1a (rx conf) */
 422 #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) /* Control reg 2a (rx conf) */
 423
 424 #define SCI0CR2 DVUCP(SCI0_BASE + 0x3)  /* Control reg 2 */
 425 #define SCI0SR1 DVUCP(SCI0_BASE + 0x4)  /* Status reg 1 (isr flags) */
 426 #define SCI0SR2 DVUCP(SCI0_BASE + 0x5)  /* Status reg 2 (config/control) */
 427 #define SCI0DRH DVUCP(SCI0_BASE + 0x6)  /* Data reg high (9th bit bit 7 receive bit 6 send) */
 428 #define SCI0DRL DVUCP(SCI0_BASE + 0x7)  /* Data reg low (read and write for receive and send respectively)*/
 429
 430
 431 /* SCI1 debug/comms/datalogging TODO this is our secondary serial interface, setup serial comms software to communicate with MTX or similar for testing. */
 432 //0x00D0 SCI1BDH
 433 //0x00D1 SCI1BDL
 434 //0x00D2 SCI1CR1
 435
 436 //0x00D0 SCI1ASR1
 437 //0x00D1 SCI1ACR1
 438 //0x00D2 SCI1ACR2
 439
 440 //0x00D3 SCI1CR2
 441 //0x00D4 SCI1SR1
 442 //0x00D5 SCI1SR2
 443 //0x00D6 SCI1DRH
 444 //0x00D7 SCI1DRL
 445
 446
 447 /* SPI0 */
 448 //0x00D8 SPI0CR1
 449 //0x00D9 SPI0CR2
 450 //0x00DA SPI0BR
 451 //0x00DB SPI0SR
 452 //0x00DD SPI0DR
 453
 454
 455 /* IIC0  */
 456 //0x00E0 IBAD
 457 //0x00E1 IBFD
 458 //0x00E2 IBCR
 459 //0x00E3 IBSR
 460 //0x00E4 IBDR
 461
 462
 463 /* SPI1 */
 464 //0x00F0 SPI1CR1
 465 //0x00F1 SPI1CR2
 466 //0x00F2 SPI1BR
 467 //0x00F3 SPI1SR
 468 //0x00F5 SPI1DR
 469
 470
 471 /* SPI2 */
 472 //0x00F8 SPI2CR1
 473 //0x00F9 SPI2CR2
 474 //0x00FA SPI2BR
 475 //0x00FB SPI2SR
 476 //0x00FD SPI2DR
 477
 478
 479 /* Flash Control Registers */
 480 #define FCLKDIV DVUCP(0x0100)   /* Flash Clock Divider Register R/W             */
 481 #define FSEC DVUCP(0x0101)              /* Flash Security Register R                    */
 482 #define FCNFG DVUCP(0x0103)             /* Flash Configuration Register R/W             */
 483 #define FPROT DVUCP(0x0104)             /* Flash Protection Register R/W                */
 484 #define FSTAT DVUCP(0x0105)             /* Flash Status Register R/W                    */
 485 #define FCMD DVUCP(0x0106)              /* Flash Command Register R/W                   */
 486 #define FCTL DVUCP(0x0107)              /* Flash Control Register R                             */
 487
 488 #define FADDR DVUSP(0x0108)             /* Flash Low Address Register R (0x0108 FADDRHI, 0x0109 FADDRLO)        */
 489 #define FDATA DVUSP(0x010A)             /* Flash High Data Register R (0x010A FDATAHI, 0x010B FDATALO)          */
 490
 491
 492 /* EEPROM Control Registers TODO learn how to use these to write data to the eeprom through serial comms. */
 493 //0x0110 ECLKDIV
 494 //0x0113 ECNFG
 495 //0x0114 EPROT
 496 //0x0115 ESTAT
 497 //0x0116 ECMD
 498 //0x0118 EADDRHI
 499 //0x0119 EADDRLO
 500 //0x011A EDATAHI
 501 //0x011B EDATALO
 502
 503
 504 //// IM
 505 #define IVBR DVUCP(0x0121) /* Interrupt vector table base location first byte (second is always 0x00) */
 506 //0x0126 INT_XGPRIO
 507 //0x0127 INT_CFADDR
 508 //0x0128 INT_CFDATA0
 509 //0x0129 INT_CFDATA1
 510 //0x012A INT_CFDATA2
 511 //0x012B INT_CFDATA3
 512 //0x012C INT_CFDATA4
 513 //0x012D INT_CFDATA5
 514 //0x012E INT_CFDATA6
 515 //0x012F INT_CFDATA7
 516
 517
 518 /* SCI4 */
 519 //0x0130 SCI4BDH
 520 //0x0130 SCI4ASR1
 521 //0x0131 SCI4BDL
 522 //0x0131 SCI4ACR1
 523 //0x0132 SCI4CR1
 524 //0x0132 SCI4ACR2
 525 //0x0133 SCI4CR2
 526 //0x0134 SCI4SR1
 527 //0x0135 SCI4SR2
 528 //0x0136 SCI4DRH
 529 //0x0137 SCI4DRL
 530
 531
 532 /* SCI5 */
 533 //0x0138 SCI5BDH
 534 //0x0138 SCI5ASR1
 535 //0x0139 SCI5BDL
 536 //0x0139 SCI5ACR1
 537 //0x013A SCI5CR1
 538 //0x013A SCI5ACR2
 539 //0x013B SCI5CR2
 540 //0x013C SCI5SR1
 541 //0x013D SCI5SR2
 542 //0x013E SCI5DRH
 543 //0x013F SCI5DRL
 544
 545
 546 /* CAN0 don't want this for now, leave it disabled too. CAN0CTL1 bit 7 should be set to zero to disable this. */
 547 //0x0140 CAN0CTL0
 548 #define CAN0CTL1 DVUCP(0x0141)
 549 //0x0142 CAN0BTR0
 550 //0x0143 CAN0BTR1
 551 //0x0144 CAN0RFLG
 552 //0x0145 CAN0RIER
 553 //0x0146 CAN0TFLG
 554 //0x0147 CAN0TIER
 555 //0x0148 CAN0TARQ
 556 //0x0149 CAN0TAAK
 557 //0x014A CAN0TBSEL
 558 //0x014B CAN0IDAC
 559 //0x014D CAN0MISC
 560 //0x014E CAN0RXERR
 561 //0x014F CAN0TXERR
 562 //0x0150 – 0x0153 : CAN0IDAR0 – CAN0IDAR3
 563 //0x0154 – 0x0157 : CAN0IDMR0 – CAN0IDMR3
 564 //0x0158 – 0x015B : CAN0IDAR4 – CAN0IDAR7
 565 //0x015C – 0x015F : CAN0IDMR4 – CAN0IDMR7
 566 //0x0160 – 0x016F : CAN0RXFG
 567 //0x0170 – 0x017F : CAN0TXFG
 568
 569
 570 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
 571 //this block applies to all can maps!!!
 572 //
 573 //0xXXX0
 574 //Extended ID
 575 //Standard ID
 576 //CANxRIDR0
 577 //0xXXX1
 578 //Extended ID
 579 //Standard ID
 580 //CANxRIDR1
 581 //0xXXX2
 582 //Extended ID
 583 //Standard ID
 584 //CANxRIDR2
 585 //0xXXX3
 586 //Extended ID
 587 //Standard ID
 588 //CANxRIDR3
 589 //
 590 //0xXXX4–
 591 //0xXXXB
 592 //CANxRDSR0–
 593 //CANxRDSR7
 594 //0xXXXC CANRxDLR
 595 //0xXXXD Reserved
 596 //0xXXXE CANxRTSRH
 597 //0xXXXF CANxRTSRL
 598 //0xXX10
 599 //Extended ID
 600 //CANxTIDR0
 601 //Standard ID
 602 //
 603 //0xXX0x
 604 //XX10
 605 //Extended ID
 606 //CANxTIDR1
 607 //Standard ID
 608 //0xXX12
 609 //Extended ID
 610 //CANxTIDR2
 611 //Standard ID
 612 //0xXX13
 613 //Extended ID
 614 //CANxTIDR3
 615 //Standard ID
 616 //
 617 //0xXX14–
 618 //0xXX1B
 619 //CANxTDSR0–
 620 //CANxTDSR7
 621 //
 622 //0xXX1C CANxTDLR
 623 //0xXX1D CANxTTBPR
 624 //0xXX1E CANxTTSRH
 625 //0xXX1F CANxTTSRL
 626
 627 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&77
 628
 629
 630 /* CAN1 don't want this for now, leave it disabled too. CAN1CTL1 bit 7 should be set to zero to disable this. */
 631 //0x0180 CAN1CTL0
 632 #define CAN1CTL1 DVUCP(0x0181)
 633 //0x0182 CAN1BTR0
 634 //0x0183 CAN1BTR1
 635 //0x0184 CAN1RFLG
 636 //0x0185 CAN1RIER
 637 //0x0186 CAN1TFLG
 638 //0x0187 CAN1TIER
 639 //0x0188 CAN1TARQ
 640 //0x0189 CAN1TAAK
 641 //0x018A CAN1TBSEL
 642 //0x018B CAN1IDAC
 643 //0x018D CAN1MISC
 644 //0x018E CAN1RXERR
 645 //0x018F CAN1TXERR
 646 //0x0190 CAN1IDAR0
 647 //0x0191 CAN1IDAR1
 648 //0x0192 CAN1IDAR2
 649 //0x0193 CAN1IDAR3
 650 //0x0194 CAN1IDMR0
 651 //0x0195 CAN1IDMR1
 652 //0x0196 CAN1IDMR2
 653 //0x0197 CAN1IDMR3
 654 //0x0198 CAN1IDAR4
 655 //0x0199 CAN1IDAR5
 656 //0x019A CAN1IDAR6
 657 //0x019B CAN1IDAR7
 658 //0x019C CAN1IDMR4
 659 //0x019D CAN1IDMR5
 660 //0x019E CAN1IDMR6
 661 //0x019F CAN1IDMR7
 662 //0x01A0 – 0x01AF : CAN1RXFG
 663 //0x01B0 – 0x01BF : CAN1TXFG
 664
 665
 666 /* CAN2 CAN2CTL1 bit 7 should be set to zero to disable this. */
 667 //0x01C0 CAN2CTL0
 668 //0x01C1 CAN2CTL1
 669 //0x01C2 CAN2BTR0
 670 //0x01C3 CAN2BTR1
 671 //0x01C4 CAN2RFLG
 672 //0x01C5 CAN2RIER
 673 //0x01C6 CAN2TFLG
 674 //0x01C7 CAN2TIER
 675 //0x01C8 CAN2TARQ
 676 //0x01C9 CAN2TAAK
 677 //0x01CA CAN2TBSEL
 678 //0x01CB CAN2IDAC
 679 //0x01CD CAN2MISC
 680 //0x01CE CAN2RXERR
 681 //0x01CF CAN2TXERR
 682 //0x01D0 CAN2IDAR0
 683 //0x01D1 CAN2IDAR1
 684 //0x01D2 CAN2IDAR2
 685 //0x01D3 CAN2IDAR3
 686 //0x01D4 CAN2IDMR0
 687 //0x01D5 CAN2IDMR1
 688 //0x01D6 CAN2IDMR2
 689 //0x01D7 CAN2IDMR3
 690 //0x01D8 CAN2IDAR4
 691 //0x01D9 CAN2IDAR5
 692 //0x01DA CAN2IDAR6
 693 //0x01DB CAN2IDAR7
 694 //0x01DC CAN2IDMR4
 695 //0x01DD CAN2IDMR5
 696 //0x01DE CAN2IDMR6
 697 //0x01DF CAN2IDMR7
 698 //0x01E0 – 0x01EF : CAN2RXFG
 699 //0x01F0 – 0x01FF : CAN2TXFG
 700
 701
 702 /* CAN3 CAN3CTL1 bit 7 should be set to zero to disable this. */
 703 //0x0200 CAN3CTL0
 704 #define CAN3CTL1 DVUCP(0x0201)
 705 //0x0202 CAN3BTR0
 706 //0x0203 CAN3BTR1
 707 //0x0204 CAN3RFLG
 708 //0x0205 CAN3RIER
 709 //0x0206 CAN3TFLG
 710 //0x0207 CAN3TIER
 711 //0x0208 CAN3TARQ
 712 //0x0209 CAN3TAAK
 713 //0x020A CAN3TBSEL
 714 //0x020B CAN3IDAC
 715 //0x020E CAN3RXERR
 716 //0x020F CAN3TXERR
 717 //0x0210 CAN3IDAR0
 718 //0x0211 CAN3IDAR1
 719 //0x0212 CAN3IDAR2
 720 //0x0213 CAN3IDAR3
 721 //0x0214 CAN3IDMR0
 722 //0x0215 CAN3IDMR1
 723 //0x0216 CAN3IDMR2
 724 //0x0217 CAN3IDMR3
 725 //0x0218 CAN3IDAR4
 726 //0x0219 CAN3IDAR5
 727 //0x021A CAN3IDAR6
 728 //0x021B CAN3IDAR7
 729 //0x021C CAN3IDMR4
 730 //0x021D CAN3IDMR5
 731 //0x021E CAN3IDMR6
 732 //0x021F CAN3IDMR7
 733 //0x0220 – 0x022F : CAN3RXFG
 734 //0x0230 – 0x023F : CAN3TXFG
 735
 736
 737 /* CAN4 CAN4CTL1 bit 7 should be set to zero to disable this. */
 738 //0x0280 CAN4CTL0
 739 #define CAN4CTL1 DVUCP(0x0281)
 740 //0x0282 CAN4BTR0
 741 //0x0283 CAN4BTR1
 742 //0x0284 CAN4RFLG
 743 //0x0285 CAN4RIER
 744 //0x0286 CAN4TFLG
 745 //0x0287 CAN4TIER
 746 //0x0288 CAN4TARQ
 747 //0x0289 CAN4TAAK
 748 //0x028A CAN4TBSEL
 749 //0x028B CAN4IDAC
 750 //0x028D CAN4MISC
 751 //0x028E CAN4RXERR
 752 //0x028F CAN4TXERR
 753 //0x0290 CAN4IDAR0
 754 //0x0291 CAN4IDAR1
 755 //0x0292 CAN4IDAR2
 756 //0x0293 CAN4IDAR3
 757 //0x0294 CAN4IDMR0
 758 //0x0295 CAN4IDMR1
 759 //0x0296 CAN4IDMR2
 760 //0x0297 CAN4IDMR3
 761 //0x0298 CAN4IDAR4
 762 //0x0299 CAN4IDAR5
 763 //0x029A CAN4IDAR6
 764 //0x029B CAN4IDAR7
 765 //0x029C CAN4IDMR4
 766 //0x029D CAN4IDMR5
 767 //0x029E CAN4IDMR6
 768 //0x029F CAN4IDMR7
 769 //0x02A0 – 0x02AF : CAN4RXFG
 770 //0x02B0 – 0x02BF : CAN4TXFG
 771
 772
 773 /* ATD0 TODO configure this as ATD inputs and try them out to control rate of flashing of leds etc, or even, which LED's are flashing etc */
 774 #define ATD0CTL0 DVUCP(0x02C0) /* 0 - 2 define which ADC channel to wrap on when doing multiple channels */
 775 #define ATD0CTL1 DVUCP(0x02C1) /* External trigger select when enabled in other control register */
 776 #define ATD0CTL2 DVUCP(0x02C2) /* bit 7 turns the ADC block on. */
 777 #define ATD0CTL3 DVUCP(0x02C3) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
 778 #define ATD0CTL4 DVUCP(0x02C4) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
 779 #define ATD0CTL5 DVUCP(0x02C5) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
 780 //0x02C6 ATD0STAT0
 781 //0x02CB ATD0STAT1
 782 #define ATD0DIEN DVUCP(0x02CD) /* Digital input enable */
 783 //0x02CF ATD0PTAD0 digital use only
 784 #define ATD0_BASE 0x02D0 /* Maybe use this with a loop to sample them in a compact way. */
 785 #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ /* IAT/MAT on my JimStim setup                   */
 786 #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ /* CHT/CLT on my JimStim setup                   */
 787 #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ /* TPS/TPS on my JimStim setup                   */
 788 #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ /* EGO/O2 on my JimStim setup                            */
 789 #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ /* BRV  left of 3 one end of my h1 board */
 790 #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ /* MAP   mid of 3 one end of my h1 board */
 791 #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ /* AAP right of 3 one end of my h1 board */
 792 #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ /* SpareADC/SPARE on my JimStim setup            */
 793
 794
 795 /* VREG unit, Low Voltage Interrupt and Autonomous Periodical Interrupt */
 796 #define VREGCTRL DVUCP(0x02F1) /* VReg Control Register */
 797 #define VREGAPICL DVUCP(0x02F2) /* Autonomous Periodical Interrupt Control Register */
 798 #define VREGAPITR DVUCP(0x02F3) /* Autonomous Periodical Interrupt Trimming Register */
 799 #define VREGAPIR DVUSP(0x02F4) /* Autonomous Periodical Interrupt Rate High and Low Registers (VREGAPIRH DVUCP(0x02F4), VREGAPIRL DVUCP(0x02F5)) */
 800
 801
 802 #define PWME DVUCP(0x0300) /* PWM enable register */
 803 #define PWMPOL DVUCP(0x0301) /* PWM polarity register */
 804 #define PWMCLK DVUCP(0x0302) /* PWM clock choice register */
 805 #define PWMPRCLK DVUCP(0x0303) /* PWM Clock prescalers (bits 0,1,2 and bits 4,5,6 control 4 pins each) */
 806 #define PWMCAE DVUCP(0x0304) /* PWM Center Align Enable Register */
 807 #define PWMCTL DVUCP(0x0305) /* PWM Concatenate, stop, wait, freeze register */
 808 #define PWMSCLA DVUCP(0x0308) /* PWM Scale A register */
 809 #define PWMSCLB DVUCP(0x0309) /* PWM Scale B register */
 810 #define PWMCNT0 DVUCP(0x030C) /* PWM 8 bit counter      */
 811 #define PWMCNT1 DVUCP(0x030D) /*                                        */
 812 #define PWMCNT2 DVUCP(0x030E) /*                                        */
 813 #define PWMCNT3 DVUCP(0x030F) /*                                        */
 814 #define PWMCNT4 DVUCP(0x0310) /*                                        */
 815 #define PWMCNT5 DVUCP(0x0311) /*                                        */
 816 #define PWMCNT6 DVUCP(0x0312) /*                                        */
 817 #define PWMCNT7 DVUCP(0x0313) /* PWM 8 bit counter      */
 818 #define PWMPER0 DVUCP(0x0314) /* PWM period value       */ /* Ign LED 6 on my JimStim */
 819 #define PWMPER1 DVUCP(0x0315) /*                                        */ /* Ign LED 4 on my JimStim */
 820 #define PWMPER2 DVUCP(0x0316) /*                                        */ /* Ign LED 2 on my JimStim */
 821 #define PWMPER3 DVUCP(0x0317) /*                                        */ /* Ign LED 1 on my JimStim */
 822 #define PWMPER4 DVUCP(0x0318) /*                                        */ /* Ign LED 3 on my JimStim */
 823 #define PWMPER5 DVUCP(0x0319) /*                                        */ /* Ign LED 5 on my JimStim */
 824 #define PWMPER6 DVUCP(0x031A) /*                                        */ /* NC yet */
 825 #define PWMPER7 DVUCP(0x031B) /* PWM period value       */ /* NC yet */
 826 #define PWMDTY0 DVUCP(0x031C) /* PWM duty cycle value   */
 827 #define PWMDTY1 DVUCP(0x031D) /*                                                */
 828 #define PWMDTY2 DVUCP(0x031E) /*                                                */
 829 #define PWMDTY3 DVUCP(0x031F) /*                                                */
 830 #define PWMDTY4 DVUCP(0x0320) /*                                                */
 831 #define PWMDTY5 DVUCP(0x0321) /*                                                */
 832 #define PWMDTY6 DVUCP(0x0322) /*                                                */
 833 #define PWMDTY7 DVUCP(0x0323) /* PWM duty cycle value   */
 834 #define PWMSDN DVUCP(0x0324) /* PWM shutdown behaviour register */
 835
 836
 837 /* Periodic Interupt Timer with down counter */
 838 #define PITCFLMT DVUCP(0x0340)  /* PIT Control and Force Load Micro Timer Register, high bit enables, low 2 bits force load micro timers */
 839 #define PITFLT DVUCP(0x0341)    /* PIT Force Load Timer Register, low 4 bits force load timers */
 840 #define PITCE DVUCP(0x0342)             /* PIT Channel Enable Register, low 4 bits let the channel count */
 841 #define PITMUX DVUCP(0x0343)    /* PIT Multiplex Register, low 4 bits set which micro time base is used */
 842 #define PITINTE DVUCP(0x0344)   /* PIT Interrupt Enable Register, low four bits control the ISRs */
 843 #define PITTF DVUCP(0x0345)             /* PIT Time-Out Flag Register, low 4 bits set when each counter reaches 0 */
 844 #define PITMTLD0 DVUCP(0x0346)  /* PIT Micro Timer Load Register 0, time to start counting from when reaching zero */
 845 #define PITMTLD1 DVUCP(0x0347)  /* PIT Micro Timer Load Register 1, time to start counting from when reaching zero */
 846 #define PITLD0 DVUSP(0x0348)    /* PIT Load Register 0, time to start counting from when reaching zero (0x0348 PITLD0 (hi), 0x0349 PITLD0 (lo)) */
 847 #define PITLD1 DVUSP(0x034C)    /* PIT Load Register 1, time to start counting from when reaching zero (0x034C PITLD1 (hi), 0x034D PITLD1 (lo)) */
 848 #define PITLD2 DVUSP(0x0350)    /* PIT Load Register 2, time to start counting from when reaching zero (0x0350 PITLD2 (hi), 0x0351 PITLD2 (lo)) */
 849 #define PITLD3 DVUSP(0x0354)    /* PIT Load Register 3, time to start counting from when reaching zero (0x0354 PITLD3 (hi), 0x0355 PITLD3 (lo)) */
 850 #define PITCNT0 DVUSP(0x034A)   /* PIT Count Register 0, current value of down counter (0x034A PITCNT0 (hi), 0x034B PITCNT0 (lo)) */
 851 #define PITCNT1 DVUSP(0x034E)   /* PIT Count Register 1, current value of down counter (0x034E PITCNT1 (hi), 0x034F PITCNT1 (lo)) */
 852 #define PITCNT2 DVUSP(0x0352)   /* PIT Count Register 2, current value of down counter (0x0352 PITCNT2 (hi), 0x0353 PITCNT2 (lo)) */
 853 #define PITCNT3 DVUSP(0x0356)   /* PIT Count Register 3, current value of down counter (0x0356 PITCNT3 (hi), 0x0357 PITCNT3 (lo)) */
 854
 855
 856 // TODO XGATE Set up stuff
 857 #define XGMCTL DVUSP(0x0380) /* TODO: 7th bit of this should be set to 0 for now to turn the XGATE off */
 858 #define XGMCTLHI DVUCP(0x0380)
 859 #define XGMCTLLO DVUCP(0x0381) /* TODO: or 7th bit of this should be set to 0 for now to turn the XGATE off */
 860 //0x0382 XGCHID
 861 //0x0384 XGVBR
 862 //0x0385 XGVBR
 863 //0x0386 XGVBR
 864 //0x0387 XGVBR
 865 //0x0388 XGIF
 866 //0x0389 XGIF
 867 //0x038A XGIF
 868 //0x023B XGIF /* TODO WRONG value 0x023B stated in the manual as being both xgate and can3!!!!! should be 0x038B i believe!!!!! */
 869 //0x023C XGIF /* TODO WRONG value 0x023C stated in the manual as being both xgate and can3!!!!! should be 0x038C i believe!!!!! */
 870 //0x038D XGIF
 871 //0x038E XGIF
 872 //0x038F XGIF
 873 //0x0390 XGIF
 874 //0x0391 XGIF
 875 //0x0392 XGIF
 876 //0x0393 XGIF
 877 //0x0394 XGIF
 878 //0x0395 XGIF
 879 //0x0396 XGIF
 880 //0x0397 XGIF
 881 //0x0398 XGSWT (hi)
 882 //0x0399 XGSWT (lo)
 883 //0x039A XGSEM (hi)
 884 //0x039B XGSEM (lo)
 885 //0x039D XGCCR
 886 //0x039E XGPC (hi)
 887 //0x039F XGPC (lo)
 888 //0x03A2 XGR1 (hi)
 889 //0x03A3 XGR1 (lo)
 890 //0x03A4 XGR2 (hi)
 891 //0x03A5 XGR2 (lo)
 892 //0x03A6 XGR3 (hi)
 893 //0x03A7 XGR3 (lo)
 894 //0x03A8 XGR4 (hi)
 895 //0x03A9 XGR4 (lo)
 896 //0x03AA XGR5 (hi)
 897 //0x03AB XGR5(lo)
 898 //0x03AC XGR6 (hi)
 899 //0x03AD XGR6 (lo)
 900 //0x03AE XGR7 (hi)
 901 //0x03AF XGR7 (lo)
 902
 903
 904 //// DBG
 905 //0x0020 DBGC1 DVUCP() /*
 906 //0x0021 DBGSR DVUCP() /*
 907 //0x0022 DBGTCR DVUCP() /*
 908 //0x0023 DBGC2 DVUCP() /*
 909 //0x0024 DBGTBH DVUCP() /*
 910 //0x0025 DBGTBL DVUCP() /*
 911 //0x0026 DBGCNT DVUCP() /*
 912 //0x0027 DBGSCRX DVUCP() /*
 913 //COMPA 0x0028 DVUCP() /*
 914 //COMPC 0x0028 DVUCP() /*
 915 //DBGXCTL 0x0028 DVUCP() /*
 916 //COMPB 0x0028 DVUCP() /*
 917 //COMPD 0x0028 DVUCP() /*
 918 //0x0029 DBGXAH DVUCP() /*
 919 //0x002A DBGXAM DVUCP() /*
 920 //0x002B DBGXAL DVUCP() /*
 921 //0x002C DBGXDH DVUCP() /*
 922 //0x002D DBGXDL DVUCP() /*
 923 //0x002E DBGXDHM DVUCP() /*
 924 //0x002F DBGXDLM DVUCP() /*
 925
 926
 927 /* All reserved registers/blocks are listed here for reference */
 928
 929 /* 0x003E CTCTL COP test register */
 930 /* 0x006D TIMTST Timer test register */
 931 /* 0x0102 FTSTMOD Flash test register */
 932 /* 0x02C8 ATD0TEST0 ADC test register */
 933 /* 0x02C9 ATD0TEST1 ADC test register */
 934 /* 0x02F0 VREGHTCL VReg test register */
 935 /* 0x0306 PWMTST PWM test register */
 936 /* 0x0307 PWMPRSC PWM test register 2 */
 937 /* 0x030A PWMSCNTA PWM test register 3 */
 938 /* 0x030B PWMSCNTB PWM test register 4 */
 939
 940
 941 /* 0x001D Reserved                              */
 942 /* 0x001F Reserved                              */
 943 /* 0x0012 Reserved                              */
 944 /* 0x0014 - 0x0015 : Reserved   */
 945 /* 0x0018 - 0x0019 : Reserved   */
 946 /* 0x0031 Reserved                              */
 947 /* 0x006C Reserved                              */
 948 /* 0x00B5 - 0x00B7 : Reserved   */
 949 /* 0x0087 Reserved                              */
 950 /* 0x00DC Reserved                              */
 951 /* 0x00DE - 0x00DF : Reserved   */
 952 /* 0x00E5 - 0x00EF : Reserved   */
 953 /* 0x00F4 Reserved                              */
 954 /* 0x00F6 Reserved                              */
 955 /* 0x00F7 Reserved                              */
 956 /* 0x00FC Reserved                              */
 957 /* 0x00FE - 0x00FF : Reserved   */
 958 /* 0x010C - 0x010F : Reserved   */
 959 /* 0x0111 Reserved                              */
 960 /* 0x0112 Reserved                              */
 961 /* 0x0117 Reserved                              */
 962 /* 0x0120 Reserved                              */
 963 /* 0x0122 - 0x0125 : Reserved   */
 964 /* 0x014C Reserved                              */
 965 /* 0x018C Reserved                              */
 966 /* 0x01CC Reserved                              */
 967 /* 0x020C - 0x020D : Reserved   */
 968 /* 0x0246 - 0x0247 : Reserved   */
 969 /* 0x024F Reserved                              */
 970 /* 0x0270 Reserved                              */
 971 /* 0x0272 Reserved                              */
 972 /* 0x0274 Reserved                              */
 973 /* 0x0276 Reserved                              */
 974 /* 0x028C Reserved                              */
 975 /* 0x02C7 Reserved                              */
 976 /* 0x02CA Reserved                              */
 977 /* 0x02CC Reserved                              */
 978 /* 0x02CE Reserved                              */
 979 /* 0x02E0 – 0x02EF : Reserved */
 980 /* 0x02F6 – 0x02FF : Reserved */
 981 /* 0x0325 – 0x033F : Reserved */
 982 /* 0x0358 – 0x037F : Reserved */
 983 /* 0x0383 Reserved                              */
 984 /* 0x039C Reserved                              */
 985 /* 0x03A0 Reserved                              */
 986 /* 0x03A1 Reserved                              */
 987 /* 0x03B0 – 0x07FF : Reserved */
 988
 989
 990 /* Clear any accidental use of Reserved from typing mistakes. */
 991 #ifdef Reserved
 992         #error "We have accidentally defined reserved as Reserved in here, find it and fix it."
 993 #endif
 994
 995
 996 #else
 997         /* let us know if we are being untidy with headers */
 998         #warning "Header file 9S12XDP512_H seen before, sort it out!"
 999 /* end of the wrapper ifdef from the very top */
1000 #endif